zs.c revision 1.45.8.3
1 /* $NetBSD: zs.c,v 1.45.8.3 2006/08/11 15:41:19 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * 12 * All advertising materials mentioning features or use of this software 13 * must display the following acknowledgement: 14 * This product includes software developed by the University of 15 * California, Lawrence Berkeley Laboratory. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions 19 * are met: 20 * 1. Redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer. 22 * 2. Redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution. 25 * 3. Neither the name of the University nor the names of its contributors 26 * may be used to endorse or promote products derived from this software 27 * without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 30 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 37 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 38 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 39 * SUCH DAMAGE. 40 * 41 * @(#)zs.c 8.1 (Berkeley) 7/19/93 42 */ 43 44 /*- 45 * Copyright (c) 1995 The NetBSD Foundation, Inc. (Atari modifications) 46 * All rights reserved. 47 * 48 * This code is derived from software contributed to The NetBSD Foundation 49 * by Leo Weppelman. 50 * 51 * Redistribution and use in source and binary forms, with or without 52 * modification, are permitted provided that the following conditions 53 * are met: 54 * 1. Redistributions of source code must retain the above copyright 55 * notice, this list of conditions and the following disclaimer. 56 * 2. Redistributions in binary form must reproduce the above copyright 57 * notice, this list of conditions and the following disclaimer in the 58 * documentation and/or other materials provided with the distribution. 59 * 3. Neither the name of The NetBSD Foundation nor the names of its 60 * contributors may be used to endorse or promote products derived 61 * from this software without specific prior written permission. 62 * 63 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 64 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 65 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 66 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 67 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 68 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 69 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 70 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 71 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 72 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 73 * POSSIBILITY OF SUCH DAMAGE. 74 */ 75 76 /* 77 * Zilog Z8530 (ZSCC) driver. 78 * 79 * Runs two tty ports (modem2 and serial2) on zs0. 80 * 81 * This driver knows far too much about chip to usage mappings. 82 */ 83 84 #include <sys/cdefs.h> 85 __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.45.8.3 2006/08/11 15:41:19 yamt Exp $"); 86 87 #include <sys/param.h> 88 #include <sys/systm.h> 89 #include <sys/proc.h> 90 #include <sys/device.h> 91 #include <sys/conf.h> 92 #include <sys/file.h> 93 #include <sys/ioctl.h> 94 #include <sys/malloc.h> 95 #include <sys/tty.h> 96 #include <sys/time.h> 97 #include <sys/kernel.h> 98 #include <sys/syslog.h> 99 #include <sys/kauth.h> 100 101 #include <machine/cpu.h> 102 #include <machine/iomap.h> 103 #include <machine/scu.h> 104 #include <machine/mfp.h> 105 #include <atari/dev/ym2149reg.h> 106 107 #include <dev/ic/z8530reg.h> 108 #include <atari/dev/zsvar.h> 109 #include "zs.h" 110 #if NZS > 1 111 #error "This driver supports only 1 85C30!" 112 #endif 113 114 #if NZS > 0 115 116 #define PCLK (8053976) /* PCLK pin input clock rate */ 117 #define PCLK_HD (9600 * 1536) /* PCLK on Hades pin input clock rate */ 118 119 #define splzs spl5 120 121 /* 122 * Software state per found chip. 123 */ 124 struct zs_softc { 125 struct device zi_dev; /* base device */ 126 volatile struct zsdevice *zi_zs; /* chip registers */ 127 struct zs_chanstate zi_cs[2]; /* chan A and B software state */ 128 }; 129 130 static u_char cb_scheduled = 0; /* Already asked for callback? */ 131 /* 132 * Define the registers for a closed port 133 */ 134 static u_char zs_init_regs[16] = { 135 /* 0 */ 0, 136 /* 1 */ 0, 137 /* 2 */ 0x60, 138 /* 3 */ 0, 139 /* 4 */ 0, 140 /* 5 */ 0, 141 /* 6 */ 0, 142 /* 7 */ 0, 143 /* 8 */ 0, 144 /* 9 */ ZSWR9_MASTER_IE | ZSWR9_VECTOR_INCL_STAT, 145 /* 10 */ ZSWR10_NRZ, 146 /* 11 */ ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 147 /* 12 */ 0, 148 /* 13 */ 0, 149 /* 14 */ ZSWR14_BAUD_FROM_PCLK | ZSWR14_BAUD_ENA, 150 /* 15 */ 0 151 }; 152 153 /* 154 * Define the machine dependant clock frequencies 155 * If BRgen feeds sender/receiver we always use a 156 * divisor 16, therefor the division by 16 can as 157 * well be done here. 158 */ 159 static u_long zs_freqs_tt[] = { 160 /* 161 * Atari TT, RTxCB is generated by TT-MFP timer C, 162 * which is set to 307.2 kHz during initialisation 163 * and never changed afterwards. 164 */ 165 PCLK/16, /* BRgen, PCLK, divisor 16 */ 166 229500, /* BRgen, RTxCA, divisor 16 */ 167 3672000, /* RTxCA, from PCLK4 */ 168 0, /* TRxCA, external */ 169 170 PCLK/16, /* BRgen, PCLK, divisor 16 */ 171 19200, /* BRgen, RTxCB, divisor 16 */ 172 307200, /* RTxCB, from TT-MFP TCO */ 173 2457600 /* TRxCB, from BCLK */ 174 }; 175 176 static u_long zs_freqs_falcon[] = { 177 /* 178 * Atari Falcon, XXX no specs available, this might be wrong 179 */ 180 PCLK/16, /* BRgen, PCLK, divisor 16 */ 181 229500, /* BRgen, RTxCA, divisor 16 */ 182 3672000, /* RTxCA, ??? */ 183 0, /* TRxCA, external */ 184 185 PCLK/16, /* BRgen, PCLK, divisor 16 */ 186 229500, /* BRgen, RTxCB, divisor 16 */ 187 3672000, /* RTxCB, ??? */ 188 2457600 /* TRxCB, ??? */ 189 }; 190 191 static u_long zs_freqs_hades[] = { 192 /* 193 * XXX: Channel-A unchecked!!!!! 194 */ 195 PCLK_HD/16, /* BRgen, PCLK, divisor 16 */ 196 229500, /* BRgen, RTxCA, divisor 16 */ 197 3672000, /* RTxCA, from PCLK4 */ 198 0, /* TRxCA, external */ 199 200 PCLK_HD/16, /* BRgen, PCLK, divisor 16 */ 201 235550, /* BRgen, RTxCB, divisor 16 */ 202 3768800, /* RTxCB, 3.7688MHz */ 203 3768800 /* TRxCB, 3.7688MHz */ 204 }; 205 206 static u_long zs_freqs_generic[] = { 207 /* 208 * other machines, assume only PCLK is available 209 */ 210 PCLK/16, /* BRgen, PCLK, divisor 16 */ 211 0, /* BRgen, RTxCA, divisor 16 */ 212 0, /* RTxCA, unknown */ 213 0, /* TRxCA, unknown */ 214 215 PCLK/16, /* BRgen, PCLK, divisor 16 */ 216 0, /* BRgen, RTxCB, divisor 16 */ 217 0, /* RTxCB, unknown */ 218 0 /* TRxCB, unknown */ 219 }; 220 static u_long *zs_frequencies; 221 222 /* Definition of the driver for autoconfig. */ 223 static int zsmatch __P((struct device *, struct cfdata *, void *)); 224 static void zsattach __P((struct device *, struct device *, void *)); 225 226 CFATTACH_DECL(zs, sizeof(struct zs_softc), 227 zsmatch, zsattach, NULL, NULL); 228 229 extern struct cfdriver zs_cd; 230 231 /* {b,c}devsw[] function prototypes */ 232 dev_type_open(zsopen); 233 dev_type_close(zsclose); 234 dev_type_read(zsread); 235 dev_type_write(zswrite); 236 dev_type_ioctl(zsioctl); 237 dev_type_stop(zsstop); 238 dev_type_tty(zstty); 239 dev_type_poll(zspoll); 240 241 const struct cdevsw zs_cdevsw = { 242 zsopen, zsclose, zsread, zswrite, zsioctl, 243 zsstop, zstty, zspoll, nommap, ttykqfilter, D_TTY 244 }; 245 246 /* Interrupt handlers. */ 247 int zshard __P((long)); 248 static int zssoft __P((long)); 249 static int zsrint __P((struct zs_chanstate *, volatile struct zschan *)); 250 static int zsxint __P((struct zs_chanstate *, volatile struct zschan *)); 251 static int zssint __P((struct zs_chanstate *, volatile struct zschan *)); 252 253 static struct zs_chanstate *zslist; 254 255 /* Routines called from other code. */ 256 static void zsstart __P((struct tty *)); 257 258 /* Routines purely local to this driver. */ 259 static void zsoverrun __P((int, long *, const char *)); 260 static int zsparam __P((struct tty *, struct termios *)); 261 static int zsbaudrate __P((int, int, int *, int *, int *, int *)); 262 static int zs_modem __P((struct zs_chanstate *, int, int)); 263 static void zs_loadchannelregs __P((volatile struct zschan *, u_char *)); 264 static void zs_shutdown __P((struct zs_chanstate *)); 265 266 static int zsshortcuts; /* number of "shortcut" software interrupts */ 267 268 static int 269 zsmatch(pdp, cfp, auxp) 270 struct device *pdp; 271 struct cfdata *cfp; 272 void *auxp; 273 { 274 static int zs_matched = 0; 275 276 if(strcmp("zs", auxp) || zs_matched) 277 return(0); 278 zs_matched = 1; 279 return(1); 280 } 281 282 /* 283 * Attach a found zs. 284 */ 285 static void 286 zsattach(parent, dev, aux) 287 struct device *parent; 288 struct device *dev; 289 void *aux; 290 { 291 register struct zs_softc *zi; 292 register struct zs_chanstate *cs; 293 register volatile struct zsdevice *addr; 294 char tmp; 295 296 addr = (struct zsdevice *)AD_SCC; 297 zi = (struct zs_softc *)dev; 298 zi->zi_zs = addr; 299 cs = zi->zi_cs; 300 301 /* 302 * Get the command register into a known state. 303 */ 304 tmp = addr->zs_chan[ZS_CHAN_A].zc_csr; 305 tmp = addr->zs_chan[ZS_CHAN_A].zc_csr; 306 tmp = addr->zs_chan[ZS_CHAN_B].zc_csr; 307 tmp = addr->zs_chan[ZS_CHAN_B].zc_csr; 308 309 /* 310 * Do a hardware reset. 311 */ 312 ZS_WRITE(&addr->zs_chan[ZS_CHAN_A], 9, ZSWR9_HARD_RESET); 313 delay(50000); /*enough ? */ 314 ZS_WRITE(&addr->zs_chan[ZS_CHAN_A], 9, 0); 315 316 /* 317 * Initialize both channels 318 */ 319 zs_loadchannelregs(&addr->zs_chan[ZS_CHAN_A], zs_init_regs); 320 zs_loadchannelregs(&addr->zs_chan[ZS_CHAN_B], zs_init_regs); 321 322 if(machineid & ATARI_TT) { 323 /* 324 * ininitialise TT-MFP timer C: 307200Hz 325 * timer C and D share one control register: 326 * bits 0-2 control timer D 327 * bits 4-6 control timer C 328 */ 329 int cr = MFP2->mf_tcdcr & 7; 330 MFP2->mf_tcdcr = cr; /* stop timer C */ 331 MFP2->mf_tcdr = 1; /* counter 1 */ 332 cr |= T_Q004 << 4; /* divisor 4 */ 333 MFP2->mf_tcdcr = cr; /* start timer C */ 334 /* 335 * enable scc related interrupts 336 */ 337 SCU->vme_mask |= SCU_SCC; 338 339 zs_frequencies = zs_freqs_tt; 340 } else if (machineid & ATARI_FALCON) { 341 zs_frequencies = zs_freqs_falcon; 342 } else if (machineid & ATARI_HADES) { 343 zs_frequencies = zs_freqs_hades; 344 } else { 345 zs_frequencies = zs_freqs_generic; 346 } 347 348 /* link into interrupt list with order (A,B) (B=A+1) */ 349 cs[0].cs_next = &cs[1]; 350 cs[1].cs_next = zslist; 351 zslist = cs; 352 353 cs->cs_unit = 0; 354 cs->cs_zc = &addr->zs_chan[ZS_CHAN_A]; 355 cs++; 356 cs->cs_unit = 1; 357 cs->cs_zc = &addr->zs_chan[ZS_CHAN_B]; 358 359 printf(": serial2 on channel a and modem2 on channel b\n"); 360 } 361 362 /* 363 * Open a zs serial port. 364 */ 365 int 366 zsopen(dev, flags, mode, l) 367 dev_t dev; 368 int flags; 369 int mode; 370 struct lwp *l; 371 { 372 register struct tty *tp; 373 register struct zs_chanstate *cs; 374 struct zs_softc *zi; 375 int unit = ZS_UNIT(dev); 376 int zs = unit >> 1; 377 int error, s; 378 379 if(zs >= zs_cd.cd_ndevs || (zi = zs_cd.cd_devs[zs]) == NULL) 380 return (ENXIO); 381 cs = &zi->zi_cs[unit & 1]; 382 383 /* 384 * When port A (ser02) is selected on the TT, make sure 385 * the port is enabled. 386 */ 387 if((machineid & ATARI_TT) && !(unit & 1)) 388 ym2149_ser2(1); 389 390 if (cs->cs_rbuf == NULL) { 391 cs->cs_rbuf = malloc(ZLRB_RING_SIZE * sizeof(int), M_DEVBUF, 392 M_WAITOK); 393 } 394 395 tp = cs->cs_ttyp; 396 if(tp == NULL) { 397 cs->cs_ttyp = tp = ttymalloc(); 398 tty_attach(tp); 399 tp->t_dev = dev; 400 tp->t_oproc = zsstart; 401 tp->t_param = zsparam; 402 } 403 404 if ((tp->t_state & TS_ISOPEN) && 405 (tp->t_state & TS_XCLUDE) && 406 kauth_authorize_generic(l->l_cred, KAUTH_GENERIC_ISSUSER, 407 &l->l_acflag) != 0) 408 return (EBUSY); 409 410 s = spltty(); 411 412 /* 413 * Do the following iff this is a first open. 414 */ 415 if (!(tp->t_state & TS_ISOPEN) && tp->t_wopen == 0) { 416 if(tp->t_ispeed == 0) { 417 tp->t_iflag = TTYDEF_IFLAG; 418 tp->t_oflag = TTYDEF_OFLAG; 419 tp->t_cflag = TTYDEF_CFLAG; 420 tp->t_lflag = TTYDEF_LFLAG; 421 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 422 } 423 ttychars(tp); 424 ttsetwater(tp); 425 426 (void)zsparam(tp, &tp->t_termios); 427 428 /* 429 * Turn on DTR. We must always do this, even if carrier is not 430 * present, because otherwise we'd have to use TIOCSDTR 431 * immediately after setting CLOCAL, which applications do not 432 * expect. We always assert DTR while the device is open 433 * unless explicitly requested to deassert it. 434 */ 435 zs_modem(cs, ZSWR5_RTS|ZSWR5_DTR, DMSET); 436 /* May never get a status intr. if DCD already on. -gwr */ 437 if((cs->cs_rr0 = cs->cs_zc->zc_csr) & ZSRR0_DCD) 438 tp->t_state |= TS_CARR_ON; 439 if(cs->cs_softcar) 440 tp->t_state |= TS_CARR_ON; 441 } 442 443 splx(s); 444 445 error = ttyopen(tp, ZS_DIALOUT(dev), (flags & O_NONBLOCK)); 446 if (error) 447 goto bad; 448 449 error = tp->t_linesw->l_open(dev, tp); 450 if(error) 451 goto bad; 452 return (0); 453 454 bad: 455 if (!(tp->t_state & TS_ISOPEN) && tp->t_wopen == 0) { 456 /* 457 * We failed to open the device, and nobody else had it opened. 458 * Clean up the state as appropriate. 459 */ 460 zs_shutdown(cs); 461 } 462 return(error); 463 } 464 465 /* 466 * Close a zs serial port. 467 */ 468 int 469 zsclose(dev, flags, mode, l) 470 dev_t dev; 471 int flags; 472 int mode; 473 struct lwp *l; 474 { 475 register struct zs_chanstate *cs; 476 register struct tty *tp; 477 struct zs_softc *zi; 478 int unit = ZS_UNIT(dev); 479 480 zi = zs_cd.cd_devs[unit >> 1]; 481 cs = &zi->zi_cs[unit & 1]; 482 tp = cs->cs_ttyp; 483 484 tp->t_linesw->l_close(tp, flags); 485 ttyclose(tp); 486 487 if (!(tp->t_state & TS_ISOPEN) && tp->t_wopen == 0) { 488 /* 489 * Although we got a last close, the device may still be in 490 * use; e.g. if this was the dialout node, and there are still 491 * processes waiting for carrier on the non-dialout node. 492 */ 493 zs_shutdown(cs); 494 } 495 return (0); 496 } 497 498 /* 499 * Read/write zs serial port. 500 */ 501 int 502 zsread(dev, uio, flags) 503 dev_t dev; 504 struct uio *uio; 505 int flags; 506 { 507 register struct zs_chanstate *cs; 508 register struct zs_softc *zi; 509 register struct tty *tp; 510 int unit; 511 512 unit = ZS_UNIT(dev); 513 zi = zs_cd.cd_devs[unit >> 1]; 514 cs = &zi->zi_cs[unit & 1]; 515 tp = cs->cs_ttyp; 516 517 return(tp->t_linesw->l_read(tp, uio, flags)); 518 } 519 520 int 521 zswrite(dev, uio, flags) 522 dev_t dev; 523 struct uio *uio; 524 int flags; 525 { 526 register struct zs_chanstate *cs; 527 register struct zs_softc *zi; 528 register struct tty *tp; 529 int unit; 530 531 unit = ZS_UNIT(dev); 532 zi = zs_cd.cd_devs[unit >> 1]; 533 cs = &zi->zi_cs[unit & 1]; 534 tp = cs->cs_ttyp; 535 536 return(tp->t_linesw->l_write(tp, uio, flags)); 537 } 538 539 int 540 zspoll(dev, events, l) 541 dev_t dev; 542 int events; 543 struct lwp *l; 544 { 545 register struct zs_chanstate *cs; 546 register struct zs_softc *zi; 547 register struct tty *tp; 548 int unit; 549 550 unit = ZS_UNIT(dev); 551 zi = zs_cd.cd_devs[unit >> 1]; 552 cs = &zi->zi_cs[unit & 1]; 553 tp = cs->cs_ttyp; 554 555 return ((*tp->t_linesw->l_poll)(tp, events, l)); 556 } 557 558 struct tty * 559 zstty(dev) 560 dev_t dev; 561 { 562 register struct zs_chanstate *cs; 563 register struct zs_softc *zi; 564 int unit; 565 566 unit = ZS_UNIT(dev); 567 zi = zs_cd.cd_devs[unit >> 1]; 568 cs = &zi->zi_cs[unit & 1]; 569 return(cs->cs_ttyp); 570 } 571 572 /* 573 * ZS hardware interrupt. Scan all ZS channels. NB: we know here that 574 * channels are kept in (A,B) pairs. 575 * 576 * Do just a little, then get out; set a software interrupt if more 577 * work is needed. 578 * 579 * We deliberately ignore the vectoring Zilog gives us, and match up 580 * only the number of `reset interrupt under service' operations, not 581 * the order. 582 */ 583 584 int 585 zshard(sr) 586 long sr; 587 { 588 register struct zs_chanstate *a; 589 #define b (a + 1) 590 register volatile struct zschan *zc; 591 register int rr3, intflags = 0, v, i; 592 593 do { 594 intflags &= ~4; 595 for(a = zslist; a != NULL; a = b->cs_next) { 596 rr3 = ZS_READ(a->cs_zc, 3); 597 if(rr3 & (ZSRR3_IP_A_RX|ZSRR3_IP_A_TX|ZSRR3_IP_A_STAT)) { 598 intflags |= 4|2; 599 zc = a->cs_zc; 600 i = a->cs_rbput; 601 if(rr3 & ZSRR3_IP_A_RX && (v = zsrint(a, zc)) != 0) { 602 a->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 603 intflags |= 1; 604 } 605 if(rr3 & ZSRR3_IP_A_TX && (v = zsxint(a, zc)) != 0) { 606 a->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 607 intflags |= 1; 608 } 609 if(rr3 & ZSRR3_IP_A_STAT && (v = zssint(a, zc)) != 0) { 610 a->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 611 intflags |= 1; 612 } 613 a->cs_rbput = i; 614 } 615 if(rr3 & (ZSRR3_IP_B_RX|ZSRR3_IP_B_TX|ZSRR3_IP_B_STAT)) { 616 intflags |= 4|2; 617 zc = b->cs_zc; 618 i = b->cs_rbput; 619 if(rr3 & ZSRR3_IP_B_RX && (v = zsrint(b, zc)) != 0) { 620 b->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 621 intflags |= 1; 622 } 623 if(rr3 & ZSRR3_IP_B_TX && (v = zsxint(b, zc)) != 0) { 624 b->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 625 intflags |= 1; 626 } 627 if(rr3 & ZSRR3_IP_B_STAT && (v = zssint(b, zc)) != 0) { 628 b->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 629 intflags |= 1; 630 } 631 b->cs_rbput = i; 632 } 633 } 634 } while(intflags & 4); 635 #undef b 636 637 if(intflags & 1) { 638 if(BASEPRI(sr)) { 639 spl1(); 640 zsshortcuts++; 641 return(zssoft(sr)); 642 } 643 else if(!cb_scheduled) { 644 cb_scheduled++; 645 add_sicallback((si_farg)zssoft, 0, 0); 646 } 647 } 648 return(intflags & 2); 649 } 650 651 static int 652 zsrint(cs, zc) 653 register struct zs_chanstate *cs; 654 register volatile struct zschan *zc; 655 { 656 register int c; 657 658 /* 659 * First read the status, because read of the received char 660 * destroy the status of this char. 661 */ 662 c = ZS_READ(zc, 1); 663 c |= (zc->zc_data << 8); 664 665 /* clear receive error & interrupt condition */ 666 zc->zc_csr = ZSWR0_RESET_ERRORS; 667 zc->zc_csr = ZSWR0_CLR_INTR; 668 669 return(ZRING_MAKE(ZRING_RINT, c)); 670 } 671 672 static int 673 zsxint(cs, zc) 674 register struct zs_chanstate *cs; 675 register volatile struct zschan *zc; 676 { 677 register int i = cs->cs_tbc; 678 679 if(i == 0) { 680 zc->zc_csr = ZSWR0_RESET_TXINT; 681 zc->zc_csr = ZSWR0_CLR_INTR; 682 return(ZRING_MAKE(ZRING_XINT, 0)); 683 } 684 cs->cs_tbc = i - 1; 685 zc->zc_data = *cs->cs_tba++; 686 zc->zc_csr = ZSWR0_CLR_INTR; 687 return (0); 688 } 689 690 static int 691 zssint(cs, zc) 692 register struct zs_chanstate *cs; 693 register volatile struct zschan *zc; 694 { 695 register int rr0; 696 697 rr0 = zc->zc_csr; 698 zc->zc_csr = ZSWR0_RESET_STATUS; 699 zc->zc_csr = ZSWR0_CLR_INTR; 700 /* 701 * The chip's hardware flow control is, as noted in zsreg.h, 702 * busted---if the DCD line goes low the chip shuts off the 703 * receiver (!). If we want hardware CTS flow control but do 704 * not have it, and carrier is now on, turn HFC on; if we have 705 * HFC now but carrier has gone low, turn it off. 706 */ 707 if(rr0 & ZSRR0_DCD) { 708 if(cs->cs_ttyp->t_cflag & CCTS_OFLOW && 709 (cs->cs_creg[3] & ZSWR3_HFC) == 0) { 710 cs->cs_creg[3] |= ZSWR3_HFC; 711 ZS_WRITE(zc, 3, cs->cs_creg[3]); 712 } 713 } 714 else { 715 if (cs->cs_creg[3] & ZSWR3_HFC) { 716 cs->cs_creg[3] &= ~ZSWR3_HFC; 717 ZS_WRITE(zc, 3, cs->cs_creg[3]); 718 } 719 } 720 return(ZRING_MAKE(ZRING_SINT, rr0)); 721 } 722 723 /* 724 * Print out a ring or fifo overrun error message. 725 */ 726 static void 727 zsoverrun(unit, ptime, what) 728 int unit; 729 long *ptime; 730 const char *what; 731 { 732 733 if(*ptime != time.tv_sec) { 734 *ptime = time.tv_sec; 735 log(LOG_WARNING, "zs%d%c: %s overrun\n", unit >> 1, 736 (unit & 1) + 'a', what); 737 } 738 } 739 740 /* 741 * ZS software interrupt. Scan all channels for deferred interrupts. 742 */ 743 int 744 zssoft(sr) 745 long sr; 746 { 747 register struct zs_chanstate *cs; 748 register volatile struct zschan *zc; 749 register struct linesw *line; 750 register struct tty *tp; 751 register int get, n, c, cc, unit, s; 752 int retval = 0; 753 754 cb_scheduled = 0; 755 s = spltty(); 756 for(cs = zslist; cs != NULL; cs = cs->cs_next) { 757 get = cs->cs_rbget; 758 again: 759 n = cs->cs_rbput; /* atomic */ 760 if(get == n) /* nothing more on this line */ 761 continue; 762 retval = 1; 763 unit = cs->cs_unit; /* set up to handle interrupts */ 764 zc = cs->cs_zc; 765 tp = cs->cs_ttyp; 766 line = tp->t_linesw; 767 /* 768 * Compute the number of interrupts in the receive ring. 769 * If the count is overlarge, we lost some events, and 770 * must advance to the first valid one. It may get 771 * overwritten if more data are arriving, but this is 772 * too expensive to check and gains nothing (we already 773 * lost out; all we can do at this point is trade one 774 * kind of loss for another). 775 */ 776 n -= get; 777 if(n > ZLRB_RING_SIZE) { 778 zsoverrun(unit, &cs->cs_rotime, "ring"); 779 get += n - ZLRB_RING_SIZE; 780 n = ZLRB_RING_SIZE; 781 } 782 while(--n >= 0) { 783 /* race to keep ahead of incoming interrupts */ 784 c = cs->cs_rbuf[get++ & ZLRB_RING_MASK]; 785 switch (ZRING_TYPE(c)) { 786 787 case ZRING_RINT: 788 c = ZRING_VALUE(c); 789 if(c & ZSRR1_DO) 790 zsoverrun(unit, &cs->cs_fotime, "fifo"); 791 cc = c >> 8; 792 if(c & ZSRR1_FE) 793 cc |= TTY_FE; 794 if(c & ZSRR1_PE) 795 cc |= TTY_PE; 796 line->l_rint(cc, tp); 797 break; 798 799 case ZRING_XINT: 800 /* 801 * Transmit done: change registers and resume, 802 * or clear BUSY. 803 */ 804 if(cs->cs_heldchange) { 805 int sps; 806 807 sps = splzs(); 808 c = zc->zc_csr; 809 if((c & ZSRR0_DCD) == 0) 810 cs->cs_preg[3] &= ~ZSWR3_HFC; 811 bcopy((caddr_t)cs->cs_preg, 812 (caddr_t)cs->cs_creg, 16); 813 zs_loadchannelregs(zc, cs->cs_creg); 814 splx(sps); 815 cs->cs_heldchange = 0; 816 if(cs->cs_heldtbc 817 && (tp->t_state & TS_TTSTOP) == 0) { 818 cs->cs_tbc = cs->cs_heldtbc - 1; 819 zc->zc_data = *cs->cs_tba++; 820 goto again; 821 } 822 } 823 tp->t_state &= ~TS_BUSY; 824 if(tp->t_state & TS_FLUSH) 825 tp->t_state &= ~TS_FLUSH; 826 else ndflush(&tp->t_outq,cs->cs_tba 827 - (caddr_t)tp->t_outq.c_cf); 828 line->l_start(tp); 829 break; 830 831 case ZRING_SINT: 832 /* 833 * Status line change. HFC bit is run in 834 * hardware interrupt, to avoid locking 835 * at splzs here. 836 */ 837 c = ZRING_VALUE(c); 838 if((c ^ cs->cs_rr0) & ZSRR0_DCD) { 839 cc = (c & ZSRR0_DCD) != 0; 840 if(line->l_modem(tp, cc) == 0) 841 zs_modem(cs, ZSWR5_RTS|ZSWR5_DTR, 842 cc ? DMBIS : DMBIC); 843 } 844 cs->cs_rr0 = c; 845 break; 846 847 default: 848 log(LOG_ERR, "zs%d%c: bad ZRING_TYPE (%x)\n", 849 unit >> 1, (unit & 1) + 'a', c); 850 break; 851 } 852 } 853 cs->cs_rbget = get; 854 goto again; 855 } 856 splx(s); 857 return (retval); 858 } 859 860 int 861 zsioctl(dev, cmd, data, flag, l) 862 dev_t dev; 863 u_long cmd; 864 caddr_t data; 865 int flag; 866 struct lwp *l; 867 { 868 int unit = ZS_UNIT(dev); 869 struct zs_softc *zi = zs_cd.cd_devs[unit >> 1]; 870 register struct tty *tp = zi->zi_cs[unit & 1].cs_ttyp; 871 register int error, s; 872 register struct zs_chanstate *cs = &zi->zi_cs[unit & 1]; 873 874 error = tp->t_linesw->l_ioctl(tp, cmd, data, flag, l); 875 if(error != EPASSTHROUGH) 876 return(error); 877 878 error = ttioctl(tp, cmd, data, flag, l); 879 if(error !=EPASSTHROUGH) 880 return (error); 881 882 switch (cmd) { 883 case TIOCSBRK: 884 s = splzs(); 885 cs->cs_preg[5] |= ZSWR5_BREAK; 886 cs->cs_creg[5] |= ZSWR5_BREAK; 887 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 888 splx(s); 889 break; 890 case TIOCCBRK: 891 s = splzs(); 892 cs->cs_preg[5] &= ~ZSWR5_BREAK; 893 cs->cs_creg[5] &= ~ZSWR5_BREAK; 894 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 895 splx(s); 896 break; 897 case TIOCGFLAGS: { 898 int bits = 0; 899 900 if(cs->cs_softcar) 901 bits |= TIOCFLAG_SOFTCAR; 902 if(cs->cs_creg[15] & ZSWR15_DCD_IE) 903 bits |= TIOCFLAG_CLOCAL; 904 if(cs->cs_creg[3] & ZSWR3_HFC) 905 bits |= TIOCFLAG_CRTSCTS; 906 *(int *)data = bits; 907 break; 908 } 909 case TIOCSFLAGS: { 910 int userbits = 0; 911 912 error = kauth_authorize_generic(l->l_cred, 913 KAUTH_GENERIC_ISSUSER, &l->l_acflag); 914 if(error != 0) 915 return (EPERM); 916 917 userbits = *(int *)data; 918 919 /* 920 * can have `local' or `softcar', and `rtscts' or `mdmbuf' 921 # defaulting to software flow control. 922 */ 923 if(userbits & TIOCFLAG_SOFTCAR && userbits & TIOCFLAG_CLOCAL) 924 return(EINVAL); 925 if(userbits & TIOCFLAG_MDMBUF) /* don't support this (yet?) */ 926 return(ENODEV); 927 928 s = splzs(); 929 if((userbits & TIOCFLAG_SOFTCAR)) { 930 cs->cs_softcar = 1; /* turn on softcar */ 931 cs->cs_preg[15] &= ~ZSWR15_DCD_IE; /* turn off dcd */ 932 cs->cs_creg[15] &= ~ZSWR15_DCD_IE; 933 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 934 } 935 else if(userbits & TIOCFLAG_CLOCAL) { 936 cs->cs_softcar = 0; /* turn off softcar */ 937 cs->cs_preg[15] |= ZSWR15_DCD_IE; /* turn on dcd */ 938 cs->cs_creg[15] |= ZSWR15_DCD_IE; 939 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 940 tp->t_termios.c_cflag |= CLOCAL; 941 } 942 if(userbits & TIOCFLAG_CRTSCTS) { 943 cs->cs_preg[15] |= ZSWR15_CTS_IE; 944 cs->cs_creg[15] |= ZSWR15_CTS_IE; 945 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 946 cs->cs_preg[3] |= ZSWR3_HFC; 947 cs->cs_creg[3] |= ZSWR3_HFC; 948 ZS_WRITE(cs->cs_zc, 3, cs->cs_creg[3]); 949 tp->t_termios.c_cflag |= CRTSCTS; 950 } 951 else { 952 /* no mdmbuf, so we must want software flow control */ 953 cs->cs_preg[15] &= ~ZSWR15_CTS_IE; 954 cs->cs_creg[15] &= ~ZSWR15_CTS_IE; 955 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 956 cs->cs_preg[3] &= ~ZSWR3_HFC; 957 cs->cs_creg[3] &= ~ZSWR3_HFC; 958 ZS_WRITE(cs->cs_zc, 3, cs->cs_creg[3]); 959 tp->t_termios.c_cflag &= ~CRTSCTS; 960 } 961 splx(s); 962 break; 963 } 964 case TIOCSDTR: 965 zs_modem(cs, ZSWR5_DTR, DMBIS); 966 break; 967 case TIOCCDTR: 968 zs_modem(cs, ZSWR5_DTR, DMBIC); 969 break; 970 case TIOCMGET: 971 zs_modem(cs, 0, DMGET); 972 break; 973 case TIOCMSET: 974 case TIOCMBIS: 975 case TIOCMBIC: 976 default: 977 return (EPASSTHROUGH); 978 } 979 return (0); 980 } 981 982 /* 983 * Start or restart transmission. 984 */ 985 static void 986 zsstart(tp) 987 register struct tty *tp; 988 { 989 register struct zs_chanstate *cs; 990 register int s, nch; 991 int unit = ZS_UNIT(tp->t_dev); 992 struct zs_softc *zi = zs_cd.cd_devs[unit >> 1]; 993 994 cs = &zi->zi_cs[unit & 1]; 995 s = spltty(); 996 997 /* 998 * If currently active or delaying, no need to do anything. 999 */ 1000 if(tp->t_state & (TS_TIMEOUT | TS_BUSY | TS_TTSTOP)) 1001 goto out; 1002 1003 /* 1004 * If there are sleepers, and output has drained below low 1005 * water mark, awaken. 1006 */ 1007 if(tp->t_outq.c_cc <= tp->t_lowat) { 1008 if(tp->t_state & TS_ASLEEP) { 1009 tp->t_state &= ~TS_ASLEEP; 1010 wakeup((caddr_t)&tp->t_outq); 1011 } 1012 selwakeup(&tp->t_wsel); 1013 } 1014 1015 nch = ndqb(&tp->t_outq, 0); /* XXX */ 1016 if(nch) { 1017 register char *p = tp->t_outq.c_cf; 1018 1019 /* mark busy, enable tx done interrupts, & send first byte */ 1020 tp->t_state |= TS_BUSY; 1021 (void) splzs(); 1022 cs->cs_preg[1] |= ZSWR1_TIE; 1023 cs->cs_creg[1] |= ZSWR1_TIE; 1024 ZS_WRITE(cs->cs_zc, 1, cs->cs_creg[1]); 1025 cs->cs_zc->zc_data = *p; 1026 cs->cs_tba = p + 1; 1027 cs->cs_tbc = nch - 1; 1028 } else { 1029 /* 1030 * Nothing to send, turn off transmit done interrupts. 1031 * This is useful if something is doing polled output. 1032 */ 1033 (void) splzs(); 1034 cs->cs_preg[1] &= ~ZSWR1_TIE; 1035 cs->cs_creg[1] &= ~ZSWR1_TIE; 1036 ZS_WRITE(cs->cs_zc, 1, cs->cs_creg[1]); 1037 } 1038 out: 1039 splx(s); 1040 } 1041 1042 /* 1043 * Stop output, e.g., for ^S or output flush. 1044 */ 1045 void 1046 zsstop(tp, flag) 1047 register struct tty *tp; 1048 int flag; 1049 { 1050 register struct zs_chanstate *cs; 1051 register int s, unit = ZS_UNIT(tp->t_dev); 1052 struct zs_softc *zi = zs_cd.cd_devs[unit >> 1]; 1053 1054 cs = &zi->zi_cs[unit & 1]; 1055 s = splzs(); 1056 if(tp->t_state & TS_BUSY) { 1057 /* 1058 * Device is transmitting; must stop it. 1059 */ 1060 cs->cs_tbc = 0; 1061 if ((tp->t_state & TS_TTSTOP) == 0) 1062 tp->t_state |= TS_FLUSH; 1063 } 1064 splx(s); 1065 } 1066 1067 static void 1068 zs_shutdown(cs) 1069 struct zs_chanstate *cs; 1070 { 1071 struct tty *tp = cs->cs_ttyp; 1072 int s; 1073 1074 s = splzs(); 1075 1076 /* 1077 * Hang up if necessary. Wait a bit, so the other side has time to 1078 * notice even if we immediately open the port again. 1079 */ 1080 if(tp->t_cflag & HUPCL) { 1081 zs_modem(cs, 0, DMSET); 1082 (void)tsleep((caddr_t)cs, TTIPRI, ttclos, hz); 1083 } 1084 1085 /* Clear any break condition set with TIOCSBRK. */ 1086 if(cs->cs_creg[5] & ZSWR5_BREAK) { 1087 cs->cs_preg[5] &= ~ZSWR5_BREAK; 1088 cs->cs_creg[5] &= ~ZSWR5_BREAK; 1089 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 1090 } 1091 1092 /* 1093 * Drop all lines and cancel interrupts 1094 */ 1095 zs_loadchannelregs(cs->cs_zc, zs_init_regs); 1096 splx(s); 1097 } 1098 1099 /* 1100 * Set ZS tty parameters from termios. 1101 * 1102 * This routine makes use of the fact that only registers 1103 * 1, 3, 4, 5, 9, 10, 11, 12, 13, 14, and 15 are written. 1104 */ 1105 static int 1106 zsparam(tp, t) 1107 register struct tty *tp; 1108 register struct termios *t; 1109 { 1110 int unit = ZS_UNIT(tp->t_dev); 1111 struct zs_softc *zi = zs_cd.cd_devs[unit >> 1]; 1112 register struct zs_chanstate *cs = &zi->zi_cs[unit & 1]; 1113 int cdiv = 0, /* XXX gcc4 -Wuninitialized */ 1114 clkm = 0, /* XXX gcc4 -Wuninitialized */ 1115 brgm = 0, /* XXX gcc4 -Wuninitialized */ 1116 tcon = 0; /* XXX gcc4 -Wuninitialized */ 1117 register int tmp, tmp5, cflag, s; 1118 1119 tmp = t->c_ospeed; 1120 tmp5 = t->c_ispeed; 1121 if(tmp < 0 || (tmp5 && tmp5 != tmp)) 1122 return(EINVAL); 1123 if(tmp == 0) { 1124 /* stty 0 => drop DTR and RTS */ 1125 zs_modem(cs, 0, DMSET); 1126 return(0); 1127 } 1128 tmp = zsbaudrate(unit, tmp, &cdiv, &clkm, &brgm, &tcon); 1129 if (tmp < 0) 1130 return(EINVAL); 1131 tp->t_ispeed = tp->t_ospeed = tmp; 1132 1133 cflag = tp->t_cflag = t->c_cflag; 1134 if (cflag & CSTOPB) 1135 cdiv |= ZSWR4_TWOSB; 1136 else 1137 cdiv |= ZSWR4_ONESB; 1138 if (!(cflag & PARODD)) 1139 cdiv |= ZSWR4_EVENP; 1140 if (cflag & PARENB) 1141 cdiv |= ZSWR4_PARENB; 1142 1143 switch(cflag & CSIZE) { 1144 case CS5: 1145 tmp = ZSWR3_RX_5; 1146 tmp5 = ZSWR5_TX_5; 1147 break; 1148 case CS6: 1149 tmp = ZSWR3_RX_6; 1150 tmp5 = ZSWR5_TX_6; 1151 break; 1152 case CS7: 1153 tmp = ZSWR3_RX_7; 1154 tmp5 = ZSWR5_TX_7; 1155 break; 1156 case CS8: 1157 default: 1158 tmp = ZSWR3_RX_8; 1159 tmp5 = ZSWR5_TX_8; 1160 break; 1161 } 1162 tmp |= ZSWR3_RX_ENABLE; 1163 tmp5 |= ZSWR5_TX_ENABLE | ZSWR5_DTR | ZSWR5_RTS; 1164 1165 /* 1166 * Block interrupts so that state will not 1167 * be altered until we are done setting it up. 1168 */ 1169 s = splzs(); 1170 cs->cs_preg[4] = cdiv; 1171 cs->cs_preg[11] = clkm; 1172 cs->cs_preg[12] = tcon; 1173 cs->cs_preg[13] = tcon >> 8; 1174 cs->cs_preg[14] = brgm; 1175 cs->cs_preg[1] = ZSWR1_RIE | ZSWR1_TIE | ZSWR1_SIE; 1176 cs->cs_preg[9] = ZSWR9_MASTER_IE | ZSWR9_VECTOR_INCL_STAT; 1177 cs->cs_preg[10] = ZSWR10_NRZ; 1178 cs->cs_preg[15] = ZSWR15_BREAK_IE | ZSWR15_DCD_IE; 1179 1180 /* 1181 * Output hardware flow control on the chip is horrendous: if 1182 * carrier detect drops, the receiver is disabled. Hence we 1183 * can only do this when the carrier is on. 1184 */ 1185 if(cflag & CCTS_OFLOW && cs->cs_zc->zc_csr & ZSRR0_DCD) 1186 tmp |= ZSWR3_HFC; 1187 cs->cs_preg[3] = tmp; 1188 cs->cs_preg[5] = tmp5; 1189 1190 /* 1191 * If nothing is being transmitted, set up new current values, 1192 * else mark them as pending. 1193 */ 1194 if(cs->cs_heldchange == 0) { 1195 if (cs->cs_ttyp->t_state & TS_BUSY) { 1196 cs->cs_heldtbc = cs->cs_tbc; 1197 cs->cs_tbc = 0; 1198 cs->cs_heldchange = 1; 1199 } else { 1200 bcopy((caddr_t)cs->cs_preg, (caddr_t)cs->cs_creg, 16); 1201 zs_loadchannelregs(cs->cs_zc, cs->cs_creg); 1202 } 1203 } 1204 splx(s); 1205 return (0); 1206 } 1207 1208 /* 1209 * search for the best matching baudrate 1210 */ 1211 static int 1212 zsbaudrate(unit, wanted, divisor, clockmode, brgenmode, timeconst) 1213 int unit, wanted, *divisor, *clockmode, *brgenmode, *timeconst; 1214 { 1215 int bestdiff, bestbps, source; 1216 1217 bestdiff = bestbps = 0; 1218 unit = (unit & 1) << 2; 1219 for (source = 0; source < 4; ++source) { 1220 long freq = zs_frequencies[unit + source]; 1221 int diff, bps, div, clkm, brgm, tcon; 1222 1223 bps = div = clkm = brgm = tcon = 0; 1224 switch (source) { 1225 case 0: /* BRgen, PCLK */ 1226 brgm = ZSWR14_BAUD_ENA|ZSWR14_BAUD_FROM_PCLK; 1227 break; 1228 case 1: /* BRgen, RTxC */ 1229 brgm = ZSWR14_BAUD_ENA; 1230 break; 1231 case 2: /* RTxC */ 1232 clkm = ZSWR11_RXCLK_RTXC|ZSWR11_TXCLK_RTXC; 1233 break; 1234 case 3: /* TRxC */ 1235 clkm = ZSWR11_RXCLK_TRXC|ZSWR11_TXCLK_TRXC; 1236 break; 1237 } 1238 switch (source) { 1239 case 0: 1240 case 1: 1241 div = ZSWR4_CLK_X16; 1242 clkm = ZSWR11_RXCLK_BAUD|ZSWR11_TXCLK_BAUD; 1243 tcon = BPS_TO_TCONST(freq, wanted); 1244 if (tcon < 0) 1245 tcon = 0; 1246 bps = TCONST_TO_BPS(freq, tcon); 1247 break; 1248 case 2: 1249 case 3: 1250 { int b1 = freq / 16, d1 = abs(b1 - wanted); 1251 int b2 = freq / 32, d2 = abs(b2 - wanted); 1252 int b3 = freq / 64, d3 = abs(b3 - wanted); 1253 1254 if (d1 < d2 && d1 < d3) { 1255 div = ZSWR4_CLK_X16; 1256 bps = b1; 1257 } else if (d2 < d3 && d2 < d1) { 1258 div = ZSWR4_CLK_X32; 1259 bps = b2; 1260 } else { 1261 div = ZSWR4_CLK_X64; 1262 bps = b3; 1263 } 1264 brgm = tcon = 0; 1265 break; 1266 } 1267 } 1268 diff = abs(bps - wanted); 1269 if (!source || diff < bestdiff) { 1270 *divisor = div; 1271 *clockmode = clkm; 1272 *brgenmode = brgm; 1273 *timeconst = tcon; 1274 bestbps = bps; 1275 bestdiff = diff; 1276 if (diff == 0) 1277 break; 1278 } 1279 } 1280 /* Allow deviations upto 5% */ 1281 if (20 * bestdiff > wanted) 1282 return -1; 1283 return bestbps; 1284 } 1285 1286 /* 1287 * Raise or lower modem control (DTR/RTS) signals. If a character is 1288 * in transmission, the change is deferred. 1289 */ 1290 static int 1291 zs_modem(cs, bits, how) 1292 struct zs_chanstate *cs; 1293 int bits, how; 1294 { 1295 int s, mbits; 1296 1297 bits &= ZSWR5_DTR | ZSWR5_RTS; 1298 1299 s = splzs(); 1300 mbits = cs->cs_preg[5] & (ZSWR5_DTR | ZSWR5_RTS); 1301 1302 switch(how) { 1303 case DMSET: 1304 mbits = bits; 1305 break; 1306 case DMBIS: 1307 mbits |= bits; 1308 break; 1309 case DMBIC: 1310 mbits &= ~bits; 1311 break; 1312 case DMGET: 1313 splx(s); 1314 return(mbits); 1315 } 1316 1317 cs->cs_preg[5] = (cs->cs_preg[5] & ~(ZSWR5_DTR | ZSWR5_RTS)) | mbits; 1318 if(cs->cs_heldchange == 0) { 1319 if(cs->cs_ttyp->t_state & TS_BUSY) { 1320 cs->cs_heldtbc = cs->cs_tbc; 1321 cs->cs_tbc = 0; 1322 cs->cs_heldchange = 1; 1323 } 1324 else { 1325 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 1326 } 1327 } 1328 splx(s); 1329 return(0); 1330 } 1331 1332 /* 1333 * Write the given register set to the given zs channel in the proper order. 1334 * The channel must not be transmitting at the time. The receiver will 1335 * be disabled for the time it takes to write all the registers. 1336 */ 1337 static void 1338 zs_loadchannelregs(zc, reg) 1339 volatile struct zschan *zc; 1340 u_char *reg; 1341 { 1342 int i; 1343 1344 zc->zc_csr = ZSM_RESET_ERR; /* reset error condition */ 1345 i = zc->zc_data; /* drain fifo */ 1346 i = zc->zc_data; 1347 i = zc->zc_data; 1348 ZS_WRITE(zc, 4, reg[4]); 1349 ZS_WRITE(zc, 10, reg[10]); 1350 ZS_WRITE(zc, 3, reg[3] & ~ZSWR3_RX_ENABLE); 1351 ZS_WRITE(zc, 5, reg[5] & ~ZSWR5_TX_ENABLE); 1352 ZS_WRITE(zc, 1, reg[1]); 1353 ZS_WRITE(zc, 9, reg[9]); 1354 ZS_WRITE(zc, 11, reg[11]); 1355 ZS_WRITE(zc, 12, reg[12]); 1356 ZS_WRITE(zc, 13, reg[13]); 1357 ZS_WRITE(zc, 14, reg[14]); 1358 ZS_WRITE(zc, 15, reg[15]); 1359 ZS_WRITE(zc, 3, reg[3]); 1360 ZS_WRITE(zc, 5, reg[5]); 1361 } 1362 #endif /* NZS > 1 */ 1363
Indexes created Wed Oct 01 15:09:59 GMT 2025