zs.c revision 1.53.20.2
1 /* zs.c,v 1.53.20.1 2008/01/09 01:45:32 matt Exp */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * 12 * All advertising materials mentioning features or use of this software 13 * must display the following acknowledgement: 14 * This product includes software developed by the University of 15 * California, Lawrence Berkeley Laboratory. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions 19 * are met: 20 * 1. Redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer. 22 * 2. Redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution. 25 * 3. Neither the name of the University nor the names of its contributors 26 * may be used to endorse or promote products derived from this software 27 * without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 30 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 37 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 38 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 39 * SUCH DAMAGE. 40 * 41 * @(#)zs.c 8.1 (Berkeley) 7/19/93 42 */ 43 44 /*- 45 * Copyright (c) 1995 The NetBSD Foundation, Inc. (Atari modifications) 46 * All rights reserved. 47 * 48 * This code is derived from software contributed to The NetBSD Foundation 49 * by Leo Weppelman. 50 * 51 * Redistribution and use in source and binary forms, with or without 52 * modification, are permitted provided that the following conditions 53 * are met: 54 * 1. Redistributions of source code must retain the above copyright 55 * notice, this list of conditions and the following disclaimer. 56 * 2. Redistributions in binary form must reproduce the above copyright 57 * notice, this list of conditions and the following disclaimer in the 58 * documentation and/or other materials provided with the distribution. 59 * 3. Neither the name of The NetBSD Foundation nor the names of its 60 * contributors may be used to endorse or promote products derived 61 * from this software without specific prior written permission. 62 * 63 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 64 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 65 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 66 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 67 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 68 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 69 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 70 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 71 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 72 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 73 * POSSIBILITY OF SUCH DAMAGE. 74 */ 75 76 /* 77 * Zilog Z8530 (ZSCC) driver. 78 * 79 * Runs two tty ports (modem2 and serial2) on zs0. 80 * 81 * This driver knows far too much about chip to usage mappings. 82 */ 83 84 #include <sys/cdefs.h> 85 __KERNEL_RCSID(0, "zs.c,v 1.53.20.1 2008/01/09 01:45:32 matt Exp"); 86 87 #include <sys/param.h> 88 #include <sys/systm.h> 89 #include <sys/proc.h> 90 #include <sys/device.h> 91 #include <sys/conf.h> 92 #include <sys/file.h> 93 #include <sys/ioctl.h> 94 #include <sys/malloc.h> 95 #include <sys/tty.h> 96 #include <sys/time.h> 97 #include <sys/kernel.h> 98 #include <sys/syslog.h> 99 #include <sys/kauth.h> 100 101 #include <machine/cpu.h> 102 #include <machine/iomap.h> 103 #include <machine/scu.h> 104 #include <machine/mfp.h> 105 #include <atari/dev/ym2149reg.h> 106 107 #include <dev/ic/z8530reg.h> 108 #include <atari/dev/zsvar.h> 109 #include "zs.h" 110 #if NZS > 1 111 #error "This driver supports only 1 85C30!" 112 #endif 113 114 #if NZS > 0 115 116 #define PCLK (8053976) /* PCLK pin input clock rate */ 117 #define PCLK_HD (9600 * 1536) /* PCLK on Hades pin input clock rate */ 118 119 #define splzs spl5 120 121 /* 122 * Software state per found chip. 123 */ 124 struct zs_softc { 125 struct device zi_dev; /* base device */ 126 volatile struct zsdevice *zi_zs; /* chip registers */ 127 struct zs_chanstate zi_cs[2]; /* chan A and B software state */ 128 }; 129 130 static u_char cb_scheduled = 0; /* Already asked for callback? */ 131 /* 132 * Define the registers for a closed port 133 */ 134 static u_char zs_init_regs[16] = { 135 /* 0 */ 0, 136 /* 1 */ 0, 137 /* 2 */ 0x60, 138 /* 3 */ 0, 139 /* 4 */ 0, 140 /* 5 */ 0, 141 /* 6 */ 0, 142 /* 7 */ 0, 143 /* 8 */ 0, 144 /* 9 */ ZSWR9_MASTER_IE | ZSWR9_VECTOR_INCL_STAT, 145 /* 10 */ ZSWR10_NRZ, 146 /* 11 */ ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 147 /* 12 */ 0, 148 /* 13 */ 0, 149 /* 14 */ ZSWR14_BAUD_FROM_PCLK | ZSWR14_BAUD_ENA, 150 /* 15 */ 0 151 }; 152 153 /* 154 * Define the machine dependant clock frequencies 155 * If BRgen feeds sender/receiver we always use a 156 * divisor 16, therefor the division by 16 can as 157 * well be done here. 158 */ 159 static u_long zs_freqs_tt[] = { 160 /* 161 * Atari TT, RTxCB is generated by TT-MFP timer C, 162 * which is set to 307.2 kHz during initialisation 163 * and never changed afterwards. 164 */ 165 PCLK/16, /* BRgen, PCLK, divisor 16 */ 166 229500, /* BRgen, RTxCA, divisor 16 */ 167 3672000, /* RTxCA, from PCLK4 */ 168 0, /* TRxCA, external */ 169 170 PCLK/16, /* BRgen, PCLK, divisor 16 */ 171 19200, /* BRgen, RTxCB, divisor 16 */ 172 307200, /* RTxCB, from TT-MFP TCO */ 173 2457600 /* TRxCB, from BCLK */ 174 }; 175 176 static u_long zs_freqs_falcon[] = { 177 /* 178 * Atari Falcon, XXX no specs available, this might be wrong 179 */ 180 PCLK/16, /* BRgen, PCLK, divisor 16 */ 181 229500, /* BRgen, RTxCA, divisor 16 */ 182 3672000, /* RTxCA, ??? */ 183 0, /* TRxCA, external */ 184 185 PCLK/16, /* BRgen, PCLK, divisor 16 */ 186 229500, /* BRgen, RTxCB, divisor 16 */ 187 3672000, /* RTxCB, ??? */ 188 2457600 /* TRxCB, ??? */ 189 }; 190 191 static u_long zs_freqs_hades[] = { 192 /* 193 * XXX: Channel-A unchecked!!!!! 194 */ 195 PCLK_HD/16, /* BRgen, PCLK, divisor 16 */ 196 229500, /* BRgen, RTxCA, divisor 16 */ 197 3672000, /* RTxCA, from PCLK4 */ 198 0, /* TRxCA, external */ 199 200 PCLK_HD/16, /* BRgen, PCLK, divisor 16 */ 201 235550, /* BRgen, RTxCB, divisor 16 */ 202 3768800, /* RTxCB, 3.7688MHz */ 203 3768800 /* TRxCB, 3.7688MHz */ 204 }; 205 206 static u_long zs_freqs_generic[] = { 207 /* 208 * other machines, assume only PCLK is available 209 */ 210 PCLK/16, /* BRgen, PCLK, divisor 16 */ 211 0, /* BRgen, RTxCA, divisor 16 */ 212 0, /* RTxCA, unknown */ 213 0, /* TRxCA, unknown */ 214 215 PCLK/16, /* BRgen, PCLK, divisor 16 */ 216 0, /* BRgen, RTxCB, divisor 16 */ 217 0, /* RTxCB, unknown */ 218 0 /* TRxCB, unknown */ 219 }; 220 static u_long *zs_frequencies; 221 222 /* Definition of the driver for autoconfig. */ 223 static int zsmatch __P((struct device *, struct cfdata *, void *)); 224 static void zsattach __P((struct device *, struct device *, void *)); 225 226 CFATTACH_DECL(zs, sizeof(struct zs_softc), 227 zsmatch, zsattach, NULL, NULL); 228 229 extern struct cfdriver zs_cd; 230 231 /* {b,c}devsw[] function prototypes */ 232 dev_type_open(zsopen); 233 dev_type_close(zsclose); 234 dev_type_read(zsread); 235 dev_type_write(zswrite); 236 dev_type_ioctl(zsioctl); 237 dev_type_stop(zsstop); 238 dev_type_tty(zstty); 239 dev_type_poll(zspoll); 240 241 const struct cdevsw zs_cdevsw = { 242 zsopen, zsclose, zsread, zswrite, zsioctl, 243 zsstop, zstty, zspoll, nommap, ttykqfilter, D_TTY 244 }; 245 246 /* Interrupt handlers. */ 247 int zshard __P((long)); 248 static int zssoft __P((long)); 249 static int zsrint __P((struct zs_chanstate *, volatile struct zschan *)); 250 static int zsxint __P((struct zs_chanstate *, volatile struct zschan *)); 251 static int zssint __P((struct zs_chanstate *, volatile struct zschan *)); 252 253 static struct zs_chanstate *zslist; 254 255 /* Routines called from other code. */ 256 static void zsstart __P((struct tty *)); 257 258 /* Routines purely local to this driver. */ 259 static void zsoverrun __P((int, long *, const char *)); 260 static int zsparam __P((struct tty *, struct termios *)); 261 static int zsbaudrate __P((int, int, int *, int *, int *, int *)); 262 static int zs_modem __P((struct zs_chanstate *, int, int)); 263 static void zs_loadchannelregs __P((volatile struct zschan *, u_char *)); 264 static void zs_shutdown __P((struct zs_chanstate *)); 265 266 static int zsshortcuts; /* number of "shortcut" software interrupts */ 267 268 static int 269 zsmatch(pdp, cfp, auxp) 270 struct device *pdp; 271 struct cfdata *cfp; 272 void *auxp; 273 { 274 static int zs_matched = 0; 275 276 if(strcmp("zs", auxp) || zs_matched) 277 return(0); 278 zs_matched = 1; 279 return(1); 280 } 281 282 /* 283 * Attach a found zs. 284 */ 285 static void 286 zsattach(parent, dev, aux) 287 struct device *parent; 288 struct device *dev; 289 void *aux; 290 { 291 register struct zs_softc *zi; 292 register struct zs_chanstate *cs; 293 register volatile struct zsdevice *addr; 294 char tmp; 295 296 addr = (struct zsdevice *)AD_SCC; 297 zi = (struct zs_softc *)dev; 298 zi->zi_zs = addr; 299 cs = zi->zi_cs; 300 301 /* 302 * Get the command register into a known state. 303 */ 304 tmp = addr->zs_chan[ZS_CHAN_A].zc_csr; 305 tmp = addr->zs_chan[ZS_CHAN_A].zc_csr; 306 tmp = addr->zs_chan[ZS_CHAN_B].zc_csr; 307 tmp = addr->zs_chan[ZS_CHAN_B].zc_csr; 308 309 /* 310 * Do a hardware reset. 311 */ 312 ZS_WRITE(&addr->zs_chan[ZS_CHAN_A], 9, ZSWR9_HARD_RESET); 313 delay(50000); /*enough ? */ 314 ZS_WRITE(&addr->zs_chan[ZS_CHAN_A], 9, 0); 315 316 /* 317 * Initialize both channels 318 */ 319 zs_loadchannelregs(&addr->zs_chan[ZS_CHAN_A], zs_init_regs); 320 zs_loadchannelregs(&addr->zs_chan[ZS_CHAN_B], zs_init_regs); 321 322 if(machineid & ATARI_TT) { 323 /* 324 * ininitialise TT-MFP timer C: 307200Hz 325 * timer C and D share one control register: 326 * bits 0-2 control timer D 327 * bits 4-6 control timer C 328 */ 329 int cr = MFP2->mf_tcdcr & 7; 330 MFP2->mf_tcdcr = cr; /* stop timer C */ 331 MFP2->mf_tcdr = 1; /* counter 1 */ 332 cr |= T_Q004 << 4; /* divisor 4 */ 333 MFP2->mf_tcdcr = cr; /* start timer C */ 334 /* 335 * enable scc related interrupts 336 */ 337 SCU->vme_mask |= SCU_SCC; 338 339 zs_frequencies = zs_freqs_tt; 340 } else if (machineid & ATARI_FALCON) { 341 zs_frequencies = zs_freqs_falcon; 342 } else if (machineid & ATARI_HADES) { 343 zs_frequencies = zs_freqs_hades; 344 } else { 345 zs_frequencies = zs_freqs_generic; 346 } 347 348 /* link into interrupt list with order (A,B) (B=A+1) */ 349 cs[0].cs_next = &cs[1]; 350 cs[1].cs_next = zslist; 351 zslist = cs; 352 353 cs->cs_unit = 0; 354 cs->cs_zc = &addr->zs_chan[ZS_CHAN_A]; 355 cs++; 356 cs->cs_unit = 1; 357 cs->cs_zc = &addr->zs_chan[ZS_CHAN_B]; 358 359 printf(": serial2 on channel a and modem2 on channel b\n"); 360 } 361 362 /* 363 * Open a zs serial port. 364 */ 365 int 366 zsopen(dev, flags, mode, l) 367 dev_t dev; 368 int flags; 369 int mode; 370 struct lwp *l; 371 { 372 register struct tty *tp; 373 register struct zs_chanstate *cs; 374 struct zs_softc *zi; 375 int unit = ZS_UNIT(dev); 376 int zs = unit >> 1; 377 int error, s; 378 379 if(zs >= zs_cd.cd_ndevs || (zi = zs_cd.cd_devs[zs]) == NULL) 380 return (ENXIO); 381 cs = &zi->zi_cs[unit & 1]; 382 383 /* 384 * When port A (ser02) is selected on the TT, make sure 385 * the port is enabled. 386 */ 387 if((machineid & ATARI_TT) && !(unit & 1)) 388 ym2149_ser2(1); 389 390 if (cs->cs_rbuf == NULL) { 391 cs->cs_rbuf = malloc(ZLRB_RING_SIZE * sizeof(int), M_DEVBUF, 392 M_WAITOK); 393 } 394 395 tp = cs->cs_ttyp; 396 if(tp == NULL) { 397 cs->cs_ttyp = tp = ttymalloc(); 398 tty_attach(tp); 399 tp->t_dev = dev; 400 tp->t_oproc = zsstart; 401 tp->t_param = zsparam; 402 } 403 404 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 405 return (EBUSY); 406 407 s = spltty(); 408 409 /* 410 * Do the following iff this is a first open. 411 */ 412 if (!(tp->t_state & TS_ISOPEN) && tp->t_wopen == 0) { 413 if(tp->t_ispeed == 0) { 414 tp->t_iflag = TTYDEF_IFLAG; 415 tp->t_oflag = TTYDEF_OFLAG; 416 tp->t_cflag = TTYDEF_CFLAG; 417 tp->t_lflag = TTYDEF_LFLAG; 418 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 419 } 420 ttychars(tp); 421 ttsetwater(tp); 422 423 (void)zsparam(tp, &tp->t_termios); 424 425 /* 426 * Turn on DTR. We must always do this, even if carrier is not 427 * present, because otherwise we'd have to use TIOCSDTR 428 * immediately after setting CLOCAL, which applications do not 429 * expect. We always assert DTR while the device is open 430 * unless explicitly requested to deassert it. 431 */ 432 zs_modem(cs, ZSWR5_RTS|ZSWR5_DTR, DMSET); 433 /* May never get a status intr. if DCD already on. -gwr */ 434 if((cs->cs_rr0 = cs->cs_zc->zc_csr) & ZSRR0_DCD) 435 tp->t_state |= TS_CARR_ON; 436 if(cs->cs_softcar) 437 tp->t_state |= TS_CARR_ON; 438 } 439 440 splx(s); 441 442 error = ttyopen(tp, ZS_DIALOUT(dev), (flags & O_NONBLOCK)); 443 if (error) 444 goto bad; 445 446 error = tp->t_linesw->l_open(dev, tp); 447 if(error) 448 goto bad; 449 return (0); 450 451 bad: 452 if (!(tp->t_state & TS_ISOPEN) && tp->t_wopen == 0) { 453 /* 454 * We failed to open the device, and nobody else had it opened. 455 * Clean up the state as appropriate. 456 */ 457 zs_shutdown(cs); 458 } 459 return(error); 460 } 461 462 /* 463 * Close a zs serial port. 464 */ 465 int 466 zsclose(dev, flags, mode, l) 467 dev_t dev; 468 int flags; 469 int mode; 470 struct lwp *l; 471 { 472 register struct zs_chanstate *cs; 473 register struct tty *tp; 474 struct zs_softc *zi; 475 int unit = ZS_UNIT(dev); 476 477 zi = zs_cd.cd_devs[unit >> 1]; 478 cs = &zi->zi_cs[unit & 1]; 479 tp = cs->cs_ttyp; 480 481 tp->t_linesw->l_close(tp, flags); 482 ttyclose(tp); 483 484 if (!(tp->t_state & TS_ISOPEN) && tp->t_wopen == 0) { 485 /* 486 * Although we got a last close, the device may still be in 487 * use; e.g. if this was the dialout node, and there are still 488 * processes waiting for carrier on the non-dialout node. 489 */ 490 zs_shutdown(cs); 491 } 492 return (0); 493 } 494 495 /* 496 * Read/write zs serial port. 497 */ 498 int 499 zsread(dev, uio, flags) 500 dev_t dev; 501 struct uio *uio; 502 int flags; 503 { 504 register struct zs_chanstate *cs; 505 register struct zs_softc *zi; 506 register struct tty *tp; 507 int unit; 508 509 unit = ZS_UNIT(dev); 510 zi = zs_cd.cd_devs[unit >> 1]; 511 cs = &zi->zi_cs[unit & 1]; 512 tp = cs->cs_ttyp; 513 514 return(tp->t_linesw->l_read(tp, uio, flags)); 515 } 516 517 int 518 zswrite(dev, uio, flags) 519 dev_t dev; 520 struct uio *uio; 521 int flags; 522 { 523 register struct zs_chanstate *cs; 524 register struct zs_softc *zi; 525 register struct tty *tp; 526 int unit; 527 528 unit = ZS_UNIT(dev); 529 zi = zs_cd.cd_devs[unit >> 1]; 530 cs = &zi->zi_cs[unit & 1]; 531 tp = cs->cs_ttyp; 532 533 return(tp->t_linesw->l_write(tp, uio, flags)); 534 } 535 536 int 537 zspoll(dev, events, l) 538 dev_t dev; 539 int events; 540 struct lwp *l; 541 { 542 register struct zs_chanstate *cs; 543 register struct zs_softc *zi; 544 register struct tty *tp; 545 int unit; 546 547 unit = ZS_UNIT(dev); 548 zi = zs_cd.cd_devs[unit >> 1]; 549 cs = &zi->zi_cs[unit & 1]; 550 tp = cs->cs_ttyp; 551 552 return ((*tp->t_linesw->l_poll)(tp, events, l)); 553 } 554 555 struct tty * 556 zstty(dev) 557 dev_t dev; 558 { 559 register struct zs_chanstate *cs; 560 register struct zs_softc *zi; 561 int unit; 562 563 unit = ZS_UNIT(dev); 564 zi = zs_cd.cd_devs[unit >> 1]; 565 cs = &zi->zi_cs[unit & 1]; 566 return(cs->cs_ttyp); 567 } 568 569 /* 570 * ZS hardware interrupt. Scan all ZS channels. NB: we know here that 571 * channels are kept in (A,B) pairs. 572 * 573 * Do just a little, then get out; set a software interrupt if more 574 * work is needed. 575 * 576 * We deliberately ignore the vectoring Zilog gives us, and match up 577 * only the number of `reset interrupt under service' operations, not 578 * the order. 579 */ 580 581 int 582 zshard(sr) 583 long sr; 584 { 585 register struct zs_chanstate *a; 586 #define b (a + 1) 587 register volatile struct zschan *zc; 588 register int rr3, intflags = 0, v, i; 589 590 do { 591 intflags &= ~4; 592 for(a = zslist; a != NULL; a = b->cs_next) { 593 rr3 = ZS_READ(a->cs_zc, 3); 594 if(rr3 & (ZSRR3_IP_A_RX|ZSRR3_IP_A_TX|ZSRR3_IP_A_STAT)) { 595 intflags |= 4|2; 596 zc = a->cs_zc; 597 i = a->cs_rbput; 598 if(rr3 & ZSRR3_IP_A_RX && (v = zsrint(a, zc)) != 0) { 599 a->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 600 intflags |= 1; 601 } 602 if(rr3 & ZSRR3_IP_A_TX && (v = zsxint(a, zc)) != 0) { 603 a->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 604 intflags |= 1; 605 } 606 if(rr3 & ZSRR3_IP_A_STAT && (v = zssint(a, zc)) != 0) { 607 a->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 608 intflags |= 1; 609 } 610 a->cs_rbput = i; 611 } 612 if(rr3 & (ZSRR3_IP_B_RX|ZSRR3_IP_B_TX|ZSRR3_IP_B_STAT)) { 613 intflags |= 4|2; 614 zc = b->cs_zc; 615 i = b->cs_rbput; 616 if(rr3 & ZSRR3_IP_B_RX && (v = zsrint(b, zc)) != 0) { 617 b->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 618 intflags |= 1; 619 } 620 if(rr3 & ZSRR3_IP_B_TX && (v = zsxint(b, zc)) != 0) { 621 b->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 622 intflags |= 1; 623 } 624 if(rr3 & ZSRR3_IP_B_STAT && (v = zssint(b, zc)) != 0) { 625 b->cs_rbuf[i++ & ZLRB_RING_MASK] = v; 626 intflags |= 1; 627 } 628 b->cs_rbput = i; 629 } 630 } 631 } while(intflags & 4); 632 #undef b 633 634 if(intflags & 1) { 635 if(BASEPRI(sr)) { 636 spl1(); 637 zsshortcuts++; 638 return(zssoft(sr)); 639 } 640 else if(!cb_scheduled) { 641 cb_scheduled++; 642 add_sicallback((si_farg)zssoft, 0, 0); 643 } 644 } 645 return(intflags & 2); 646 } 647 648 static int 649 zsrint(cs, zc) 650 register struct zs_chanstate *cs; 651 register volatile struct zschan *zc; 652 { 653 register int c; 654 655 /* 656 * First read the status, because read of the received char 657 * destroy the status of this char. 658 */ 659 c = ZS_READ(zc, 1); 660 c |= (zc->zc_data << 8); 661 662 /* clear receive error & interrupt condition */ 663 zc->zc_csr = ZSWR0_RESET_ERRORS; 664 zc->zc_csr = ZSWR0_CLR_INTR; 665 666 return(ZRING_MAKE(ZRING_RINT, c)); 667 } 668 669 static int 670 zsxint(cs, zc) 671 register struct zs_chanstate *cs; 672 register volatile struct zschan *zc; 673 { 674 register int i = cs->cs_tbc; 675 676 if(i == 0) { 677 zc->zc_csr = ZSWR0_RESET_TXINT; 678 zc->zc_csr = ZSWR0_CLR_INTR; 679 return(ZRING_MAKE(ZRING_XINT, 0)); 680 } 681 cs->cs_tbc = i - 1; 682 zc->zc_data = *cs->cs_tba++; 683 zc->zc_csr = ZSWR0_CLR_INTR; 684 return (0); 685 } 686 687 static int 688 zssint(cs, zc) 689 register struct zs_chanstate *cs; 690 register volatile struct zschan *zc; 691 { 692 register int rr0; 693 694 rr0 = zc->zc_csr; 695 zc->zc_csr = ZSWR0_RESET_STATUS; 696 zc->zc_csr = ZSWR0_CLR_INTR; 697 /* 698 * The chip's hardware flow control is, as noted in zsreg.h, 699 * busted---if the DCD line goes low the chip shuts off the 700 * receiver (!). If we want hardware CTS flow control but do 701 * not have it, and carrier is now on, turn HFC on; if we have 702 * HFC now but carrier has gone low, turn it off. 703 */ 704 if(rr0 & ZSRR0_DCD) { 705 if(cs->cs_ttyp->t_cflag & CCTS_OFLOW && 706 (cs->cs_creg[3] & ZSWR3_HFC) == 0) { 707 cs->cs_creg[3] |= ZSWR3_HFC; 708 ZS_WRITE(zc, 3, cs->cs_creg[3]); 709 } 710 } 711 else { 712 if (cs->cs_creg[3] & ZSWR3_HFC) { 713 cs->cs_creg[3] &= ~ZSWR3_HFC; 714 ZS_WRITE(zc, 3, cs->cs_creg[3]); 715 } 716 } 717 return(ZRING_MAKE(ZRING_SINT, rr0)); 718 } 719 720 /* 721 * Print out a ring or fifo overrun error message. 722 */ 723 static void 724 zsoverrun(unit, ptime, what) 725 int unit; 726 long *ptime; 727 const char *what; 728 { 729 time_t cur_sec = time_second; 730 731 if(*ptime != cur_sec) { 732 *ptime = cur_sec; 733 log(LOG_WARNING, "zs%d%c: %s overrun\n", unit >> 1, 734 (unit & 1) + 'a', what); 735 } 736 } 737 738 /* 739 * ZS software interrupt. Scan all channels for deferred interrupts. 740 */ 741 int 742 zssoft(sr) 743 long sr; 744 { 745 register struct zs_chanstate *cs; 746 register volatile struct zschan *zc; 747 register struct linesw *line; 748 register struct tty *tp; 749 register int get, n, c, cc, unit, s; 750 int retval = 0; 751 752 cb_scheduled = 0; 753 s = spltty(); 754 for(cs = zslist; cs != NULL; cs = cs->cs_next) { 755 get = cs->cs_rbget; 756 again: 757 n = cs->cs_rbput; /* atomic */ 758 if(get == n) /* nothing more on this line */ 759 continue; 760 retval = 1; 761 unit = cs->cs_unit; /* set up to handle interrupts */ 762 zc = cs->cs_zc; 763 tp = cs->cs_ttyp; 764 line = tp->t_linesw; 765 /* 766 * Compute the number of interrupts in the receive ring. 767 * If the count is overlarge, we lost some events, and 768 * must advance to the first valid one. It may get 769 * overwritten if more data are arriving, but this is 770 * too expensive to check and gains nothing (we already 771 * lost out; all we can do at this point is trade one 772 * kind of loss for another). 773 */ 774 n -= get; 775 if(n > ZLRB_RING_SIZE) { 776 zsoverrun(unit, &cs->cs_rotime, "ring"); 777 get += n - ZLRB_RING_SIZE; 778 n = ZLRB_RING_SIZE; 779 } 780 while(--n >= 0) { 781 /* race to keep ahead of incoming interrupts */ 782 c = cs->cs_rbuf[get++ & ZLRB_RING_MASK]; 783 switch (ZRING_TYPE(c)) { 784 785 case ZRING_RINT: 786 c = ZRING_VALUE(c); 787 if(c & ZSRR1_DO) 788 zsoverrun(unit, &cs->cs_fotime, "fifo"); 789 cc = c >> 8; 790 if(c & ZSRR1_FE) 791 cc |= TTY_FE; 792 if(c & ZSRR1_PE) 793 cc |= TTY_PE; 794 line->l_rint(cc, tp); 795 break; 796 797 case ZRING_XINT: 798 /* 799 * Transmit done: change registers and resume, 800 * or clear BUSY. 801 */ 802 if(cs->cs_heldchange) { 803 int sps; 804 805 sps = splzs(); 806 c = zc->zc_csr; 807 if((c & ZSRR0_DCD) == 0) 808 cs->cs_preg[3] &= ~ZSWR3_HFC; 809 bcopy((void *)cs->cs_preg, 810 (void *)cs->cs_creg, 16); 811 zs_loadchannelregs(zc, cs->cs_creg); 812 splx(sps); 813 cs->cs_heldchange = 0; 814 if(cs->cs_heldtbc 815 && (tp->t_state & TS_TTSTOP) == 0) { 816 cs->cs_tbc = cs->cs_heldtbc - 1; 817 zc->zc_data = *cs->cs_tba++; 818 goto again; 819 } 820 } 821 tp->t_state &= ~TS_BUSY; 822 if(tp->t_state & TS_FLUSH) 823 tp->t_state &= ~TS_FLUSH; 824 else ndflush(&tp->t_outq,cs->cs_tba 825 - tp->t_outq.c_cf); 826 line->l_start(tp); 827 break; 828 829 case ZRING_SINT: 830 /* 831 * Status line change. HFC bit is run in 832 * hardware interrupt, to avoid locking 833 * at splzs here. 834 */ 835 c = ZRING_VALUE(c); 836 if((c ^ cs->cs_rr0) & ZSRR0_DCD) { 837 cc = (c & ZSRR0_DCD) != 0; 838 if(line->l_modem(tp, cc) == 0) 839 zs_modem(cs, ZSWR5_RTS|ZSWR5_DTR, 840 cc ? DMBIS : DMBIC); 841 } 842 cs->cs_rr0 = c; 843 break; 844 845 default: 846 log(LOG_ERR, "zs%d%c: bad ZRING_TYPE (%x)\n", 847 unit >> 1, (unit & 1) + 'a', c); 848 break; 849 } 850 } 851 cs->cs_rbget = get; 852 goto again; 853 } 854 splx(s); 855 return (retval); 856 } 857 858 int 859 zsioctl(dev, cmd, data, flag, l) 860 dev_t dev; 861 u_long cmd; 862 void * data; 863 int flag; 864 struct lwp *l; 865 { 866 int unit = ZS_UNIT(dev); 867 struct zs_softc *zi = zs_cd.cd_devs[unit >> 1]; 868 register struct tty *tp = zi->zi_cs[unit & 1].cs_ttyp; 869 register int error, s; 870 register struct zs_chanstate *cs = &zi->zi_cs[unit & 1]; 871 872 error = tp->t_linesw->l_ioctl(tp, cmd, data, flag, l); 873 if(error != EPASSTHROUGH) 874 return(error); 875 876 error = ttioctl(tp, cmd, data, flag, l); 877 if(error !=EPASSTHROUGH) 878 return (error); 879 880 switch (cmd) { 881 case TIOCSBRK: 882 s = splzs(); 883 cs->cs_preg[5] |= ZSWR5_BREAK; 884 cs->cs_creg[5] |= ZSWR5_BREAK; 885 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 886 splx(s); 887 break; 888 case TIOCCBRK: 889 s = splzs(); 890 cs->cs_preg[5] &= ~ZSWR5_BREAK; 891 cs->cs_creg[5] &= ~ZSWR5_BREAK; 892 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 893 splx(s); 894 break; 895 case TIOCGFLAGS: { 896 int bits = 0; 897 898 if(cs->cs_softcar) 899 bits |= TIOCFLAG_SOFTCAR; 900 if(cs->cs_creg[15] & ZSWR15_DCD_IE) 901 bits |= TIOCFLAG_CLOCAL; 902 if(cs->cs_creg[3] & ZSWR3_HFC) 903 bits |= TIOCFLAG_CRTSCTS; 904 *(int *)data = bits; 905 break; 906 } 907 case TIOCSFLAGS: { 908 int userbits = 0; 909 910 error = kauth_authorize_device_tty(l->l_cred, 911 KAUTH_DEVICE_TTY_PRIVSET, tp); 912 if(error != 0) 913 return (EPERM); 914 915 userbits = *(int *)data; 916 917 /* 918 * can have `local' or `softcar', and `rtscts' or `mdmbuf' 919 # defaulting to software flow control. 920 */ 921 if(userbits & TIOCFLAG_SOFTCAR && userbits & TIOCFLAG_CLOCAL) 922 return(EINVAL); 923 if(userbits & TIOCFLAG_MDMBUF) /* don't support this (yet?) */ 924 return(ENODEV); 925 926 s = splzs(); 927 if((userbits & TIOCFLAG_SOFTCAR)) { 928 cs->cs_softcar = 1; /* turn on softcar */ 929 cs->cs_preg[15] &= ~ZSWR15_DCD_IE; /* turn off dcd */ 930 cs->cs_creg[15] &= ~ZSWR15_DCD_IE; 931 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 932 } 933 else if(userbits & TIOCFLAG_CLOCAL) { 934 cs->cs_softcar = 0; /* turn off softcar */ 935 cs->cs_preg[15] |= ZSWR15_DCD_IE; /* turn on dcd */ 936 cs->cs_creg[15] |= ZSWR15_DCD_IE; 937 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 938 tp->t_termios.c_cflag |= CLOCAL; 939 } 940 if(userbits & TIOCFLAG_CRTSCTS) { 941 cs->cs_preg[15] |= ZSWR15_CTS_IE; 942 cs->cs_creg[15] |= ZSWR15_CTS_IE; 943 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 944 cs->cs_preg[3] |= ZSWR3_HFC; 945 cs->cs_creg[3] |= ZSWR3_HFC; 946 ZS_WRITE(cs->cs_zc, 3, cs->cs_creg[3]); 947 tp->t_termios.c_cflag |= CRTSCTS; 948 } 949 else { 950 /* no mdmbuf, so we must want software flow control */ 951 cs->cs_preg[15] &= ~ZSWR15_CTS_IE; 952 cs->cs_creg[15] &= ~ZSWR15_CTS_IE; 953 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]); 954 cs->cs_preg[3] &= ~ZSWR3_HFC; 955 cs->cs_creg[3] &= ~ZSWR3_HFC; 956 ZS_WRITE(cs->cs_zc, 3, cs->cs_creg[3]); 957 tp->t_termios.c_cflag &= ~CRTSCTS; 958 } 959 splx(s); 960 break; 961 } 962 case TIOCSDTR: 963 zs_modem(cs, ZSWR5_DTR, DMBIS); 964 break; 965 case TIOCCDTR: 966 zs_modem(cs, ZSWR5_DTR, DMBIC); 967 break; 968 case TIOCMGET: 969 zs_modem(cs, 0, DMGET); 970 break; 971 case TIOCMSET: 972 case TIOCMBIS: 973 case TIOCMBIC: 974 default: 975 return (EPASSTHROUGH); 976 } 977 return (0); 978 } 979 980 /* 981 * Start or restart transmission. 982 */ 983 static void 984 zsstart(tp) 985 register struct tty *tp; 986 { 987 register struct zs_chanstate *cs; 988 register int s, nch; 989 int unit = ZS_UNIT(tp->t_dev); 990 struct zs_softc *zi = zs_cd.cd_devs[unit >> 1]; 991 992 cs = &zi->zi_cs[unit & 1]; 993 s = spltty(); 994 995 /* 996 * If currently active or delaying, no need to do anything. 997 */ 998 if(tp->t_state & (TS_TIMEOUT | TS_BUSY | TS_TTSTOP)) 999 goto out; 1000 1001 /* 1002 * If there are sleepers, and output has drained below low 1003 * water mark, awaken. 1004 */ 1005 ttypull(tp); 1006 1007 nch = ndqb(&tp->t_outq, 0); /* XXX */ 1008 if(nch) { 1009 register char *p = tp->t_outq.c_cf; 1010 1011 /* mark busy, enable tx done interrupts, & send first byte */ 1012 tp->t_state |= TS_BUSY; 1013 (void) splzs(); 1014 cs->cs_preg[1] |= ZSWR1_TIE; 1015 cs->cs_creg[1] |= ZSWR1_TIE; 1016 ZS_WRITE(cs->cs_zc, 1, cs->cs_creg[1]); 1017 cs->cs_zc->zc_data = *p; 1018 cs->cs_tba = p + 1; 1019 cs->cs_tbc = nch - 1; 1020 } else { 1021 /* 1022 * Nothing to send, turn off transmit done interrupts. 1023 * This is useful if something is doing polled output. 1024 */ 1025 (void) splzs(); 1026 cs->cs_preg[1] &= ~ZSWR1_TIE; 1027 cs->cs_creg[1] &= ~ZSWR1_TIE; 1028 ZS_WRITE(cs->cs_zc, 1, cs->cs_creg[1]); 1029 } 1030 out: 1031 splx(s); 1032 } 1033 1034 /* 1035 * Stop output, e.g., for ^S or output flush. 1036 */ 1037 void 1038 zsstop(tp, flag) 1039 register struct tty *tp; 1040 int flag; 1041 { 1042 register struct zs_chanstate *cs; 1043 register int s, unit = ZS_UNIT(tp->t_dev); 1044 struct zs_softc *zi = zs_cd.cd_devs[unit >> 1]; 1045 1046 cs = &zi->zi_cs[unit & 1]; 1047 s = splzs(); 1048 if(tp->t_state & TS_BUSY) { 1049 /* 1050 * Device is transmitting; must stop it. 1051 */ 1052 cs->cs_tbc = 0; 1053 if ((tp->t_state & TS_TTSTOP) == 0) 1054 tp->t_state |= TS_FLUSH; 1055 } 1056 splx(s); 1057 } 1058 1059 static void 1060 zs_shutdown(cs) 1061 struct zs_chanstate *cs; 1062 { 1063 struct tty *tp = cs->cs_ttyp; 1064 int s; 1065 1066 s = splzs(); 1067 1068 /* 1069 * Hang up if necessary. Wait a bit, so the other side has time to 1070 * notice even if we immediately open the port again. 1071 */ 1072 if(tp->t_cflag & HUPCL) { 1073 zs_modem(cs, 0, DMSET); 1074 (void)tsleep((void *)cs, TTIPRI, ttclos, hz); 1075 } 1076 1077 /* Clear any break condition set with TIOCSBRK. */ 1078 if(cs->cs_creg[5] & ZSWR5_BREAK) { 1079 cs->cs_preg[5] &= ~ZSWR5_BREAK; 1080 cs->cs_creg[5] &= ~ZSWR5_BREAK; 1081 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 1082 } 1083 1084 /* 1085 * Drop all lines and cancel interrupts 1086 */ 1087 zs_loadchannelregs(cs->cs_zc, zs_init_regs); 1088 splx(s); 1089 } 1090 1091 /* 1092 * Set ZS tty parameters from termios. 1093 * 1094 * This routine makes use of the fact that only registers 1095 * 1, 3, 4, 5, 9, 10, 11, 12, 13, 14, and 15 are written. 1096 */ 1097 static int 1098 zsparam(tp, t) 1099 register struct tty *tp; 1100 register struct termios *t; 1101 { 1102 int unit = ZS_UNIT(tp->t_dev); 1103 struct zs_softc *zi = zs_cd.cd_devs[unit >> 1]; 1104 register struct zs_chanstate *cs = &zi->zi_cs[unit & 1]; 1105 int cdiv = 0, /* XXX gcc4 -Wuninitialized */ 1106 clkm = 0, /* XXX gcc4 -Wuninitialized */ 1107 brgm = 0, /* XXX gcc4 -Wuninitialized */ 1108 tcon = 0; /* XXX gcc4 -Wuninitialized */ 1109 register int tmp, tmp5, cflag, s; 1110 1111 tmp = t->c_ospeed; 1112 tmp5 = t->c_ispeed; 1113 if(tmp < 0 || (tmp5 && tmp5 != tmp)) 1114 return(EINVAL); 1115 if(tmp == 0) { 1116 /* stty 0 => drop DTR and RTS */ 1117 zs_modem(cs, 0, DMSET); 1118 return(0); 1119 } 1120 tmp = zsbaudrate(unit, tmp, &cdiv, &clkm, &brgm, &tcon); 1121 if (tmp < 0) 1122 return(EINVAL); 1123 tp->t_ispeed = tp->t_ospeed = tmp; 1124 1125 cflag = tp->t_cflag = t->c_cflag; 1126 if (cflag & CSTOPB) 1127 cdiv |= ZSWR4_TWOSB; 1128 else 1129 cdiv |= ZSWR4_ONESB; 1130 if (!(cflag & PARODD)) 1131 cdiv |= ZSWR4_EVENP; 1132 if (cflag & PARENB) 1133 cdiv |= ZSWR4_PARENB; 1134 1135 switch(cflag & CSIZE) { 1136 case CS5: 1137 tmp = ZSWR3_RX_5; 1138 tmp5 = ZSWR5_TX_5; 1139 break; 1140 case CS6: 1141 tmp = ZSWR3_RX_6; 1142 tmp5 = ZSWR5_TX_6; 1143 break; 1144 case CS7: 1145 tmp = ZSWR3_RX_7; 1146 tmp5 = ZSWR5_TX_7; 1147 break; 1148 case CS8: 1149 default: 1150 tmp = ZSWR3_RX_8; 1151 tmp5 = ZSWR5_TX_8; 1152 break; 1153 } 1154 tmp |= ZSWR3_RX_ENABLE; 1155 tmp5 |= ZSWR5_TX_ENABLE | ZSWR5_DTR | ZSWR5_RTS; 1156 1157 /* 1158 * Block interrupts so that state will not 1159 * be altered until we are done setting it up. 1160 */ 1161 s = splzs(); 1162 cs->cs_preg[4] = cdiv; 1163 cs->cs_preg[11] = clkm; 1164 cs->cs_preg[12] = tcon; 1165 cs->cs_preg[13] = tcon >> 8; 1166 cs->cs_preg[14] = brgm; 1167 cs->cs_preg[1] = ZSWR1_RIE | ZSWR1_TIE | ZSWR1_SIE; 1168 cs->cs_preg[9] = ZSWR9_MASTER_IE | ZSWR9_VECTOR_INCL_STAT; 1169 cs->cs_preg[10] = ZSWR10_NRZ; 1170 cs->cs_preg[15] = ZSWR15_BREAK_IE | ZSWR15_DCD_IE; 1171 1172 /* 1173 * Output hardware flow control on the chip is horrendous: if 1174 * carrier detect drops, the receiver is disabled. Hence we 1175 * can only do this when the carrier is on. 1176 */ 1177 if(cflag & CCTS_OFLOW && cs->cs_zc->zc_csr & ZSRR0_DCD) 1178 tmp |= ZSWR3_HFC; 1179 cs->cs_preg[3] = tmp; 1180 cs->cs_preg[5] = tmp5; 1181 1182 /* 1183 * If nothing is being transmitted, set up new current values, 1184 * else mark them as pending. 1185 */ 1186 if(cs->cs_heldchange == 0) { 1187 if (cs->cs_ttyp->t_state & TS_BUSY) { 1188 cs->cs_heldtbc = cs->cs_tbc; 1189 cs->cs_tbc = 0; 1190 cs->cs_heldchange = 1; 1191 } else { 1192 bcopy((void *)cs->cs_preg, (void *)cs->cs_creg, 16); 1193 zs_loadchannelregs(cs->cs_zc, cs->cs_creg); 1194 } 1195 } 1196 splx(s); 1197 return (0); 1198 } 1199 1200 /* 1201 * search for the best matching baudrate 1202 */ 1203 static int 1204 zsbaudrate(unit, wanted, divisor, clockmode, brgenmode, timeconst) 1205 int unit, wanted, *divisor, *clockmode, *brgenmode, *timeconst; 1206 { 1207 int bestdiff, bestbps, source; 1208 1209 bestdiff = bestbps = 0; 1210 unit = (unit & 1) << 2; 1211 for (source = 0; source < 4; ++source) { 1212 long freq = zs_frequencies[unit + source]; 1213 int diff, bps, div, clkm, brgm, tcon; 1214 1215 bps = div = clkm = brgm = tcon = 0; 1216 switch (source) { 1217 case 0: /* BRgen, PCLK */ 1218 brgm = ZSWR14_BAUD_ENA|ZSWR14_BAUD_FROM_PCLK; 1219 break; 1220 case 1: /* BRgen, RTxC */ 1221 brgm = ZSWR14_BAUD_ENA; 1222 break; 1223 case 2: /* RTxC */ 1224 clkm = ZSWR11_RXCLK_RTXC|ZSWR11_TXCLK_RTXC; 1225 break; 1226 case 3: /* TRxC */ 1227 clkm = ZSWR11_RXCLK_TRXC|ZSWR11_TXCLK_TRXC; 1228 break; 1229 } 1230 switch (source) { 1231 case 0: 1232 case 1: 1233 div = ZSWR4_CLK_X16; 1234 clkm = ZSWR11_RXCLK_BAUD|ZSWR11_TXCLK_BAUD; 1235 tcon = BPS_TO_TCONST(freq, wanted); 1236 if (tcon < 0) 1237 tcon = 0; 1238 bps = TCONST_TO_BPS(freq, tcon); 1239 break; 1240 case 2: 1241 case 3: 1242 { int b1 = freq / 16, d1 = abs(b1 - wanted); 1243 int b2 = freq / 32, d2 = abs(b2 - wanted); 1244 int b3 = freq / 64, d3 = abs(b3 - wanted); 1245 1246 if (d1 < d2 && d1 < d3) { 1247 div = ZSWR4_CLK_X16; 1248 bps = b1; 1249 } else if (d2 < d3 && d2 < d1) { 1250 div = ZSWR4_CLK_X32; 1251 bps = b2; 1252 } else { 1253 div = ZSWR4_CLK_X64; 1254 bps = b3; 1255 } 1256 brgm = tcon = 0; 1257 break; 1258 } 1259 } 1260 diff = abs(bps - wanted); 1261 if (!source || diff < bestdiff) { 1262 *divisor = div; 1263 *clockmode = clkm; 1264 *brgenmode = brgm; 1265 *timeconst = tcon; 1266 bestbps = bps; 1267 bestdiff = diff; 1268 if (diff == 0) 1269 break; 1270 } 1271 } 1272 /* Allow deviations upto 5% */ 1273 if (20 * bestdiff > wanted) 1274 return -1; 1275 return bestbps; 1276 } 1277 1278 /* 1279 * Raise or lower modem control (DTR/RTS) signals. If a character is 1280 * in transmission, the change is deferred. 1281 */ 1282 static int 1283 zs_modem(cs, bits, how) 1284 struct zs_chanstate *cs; 1285 int bits, how; 1286 { 1287 int s, mbits; 1288 1289 bits &= ZSWR5_DTR | ZSWR5_RTS; 1290 1291 s = splzs(); 1292 mbits = cs->cs_preg[5] & (ZSWR5_DTR | ZSWR5_RTS); 1293 1294 switch(how) { 1295 case DMSET: 1296 mbits = bits; 1297 break; 1298 case DMBIS: 1299 mbits |= bits; 1300 break; 1301 case DMBIC: 1302 mbits &= ~bits; 1303 break; 1304 case DMGET: 1305 splx(s); 1306 return(mbits); 1307 } 1308 1309 cs->cs_preg[5] = (cs->cs_preg[5] & ~(ZSWR5_DTR | ZSWR5_RTS)) | mbits; 1310 if(cs->cs_heldchange == 0) { 1311 if(cs->cs_ttyp->t_state & TS_BUSY) { 1312 cs->cs_heldtbc = cs->cs_tbc; 1313 cs->cs_tbc = 0; 1314 cs->cs_heldchange = 1; 1315 } 1316 else { 1317 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]); 1318 } 1319 } 1320 splx(s); 1321 return(0); 1322 } 1323 1324 /* 1325 * Write the given register set to the given zs channel in the proper order. 1326 * The channel must not be transmitting at the time. The receiver will 1327 * be disabled for the time it takes to write all the registers. 1328 */ 1329 static void 1330 zs_loadchannelregs(zc, reg) 1331 volatile struct zschan *zc; 1332 u_char *reg; 1333 { 1334 int i; 1335 1336 zc->zc_csr = ZSM_RESET_ERR; /* reset error condition */ 1337 i = zc->zc_data; /* drain fifo */ 1338 i = zc->zc_data; 1339 i = zc->zc_data; 1340 ZS_WRITE(zc, 4, reg[4]); 1341 ZS_WRITE(zc, 10, reg[10]); 1342 ZS_WRITE(zc, 3, reg[3] & ~ZSWR3_RX_ENABLE); 1343 ZS_WRITE(zc, 5, reg[5] & ~ZSWR5_TX_ENABLE); 1344 ZS_WRITE(zc, 1, reg[1]); 1345 ZS_WRITE(zc, 9, reg[9]); 1346 ZS_WRITE(zc, 11, reg[11]); 1347 ZS_WRITE(zc, 12, reg[12]); 1348 ZS_WRITE(zc, 13, reg[13]); 1349 ZS_WRITE(zc, 14, reg[14]); 1350 ZS_WRITE(zc, 15, reg[15]); 1351 ZS_WRITE(zc, 3, reg[3]); 1352 ZS_WRITE(zc, 5, reg[5]); 1353 } 1354 #endif /* NZS > 1 */ 1355
Indexes created Wed Oct 01 15:09:59 GMT 2025