zs.c revision 1.70 1 /* $NetBSD: zs.c,v 1.70 2010/04/09 16:30:15 tsutsui Exp $ */
2
3 /*
4 * Copyright (c) 1992, 1993
5 * The Regents of the University of California. All rights reserved.
6 *
7 * This software was developed by the Computer Systems Engineering group
8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
9 * contributed to Berkeley.
10 *
11 *
12 * All advertising materials mentioning features or use of this software
13 * must display the following acknowledgement:
14 * This product includes software developed by the University of
15 * California, Lawrence Berkeley Laboratory.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
19 * are met:
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 * 3. Neither the name of the University nor the names of its contributors
26 * may be used to endorse or promote products derived from this software
27 * without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
30 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
32 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
37 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
38 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39 * SUCH DAMAGE.
40 *
41 * @(#)zs.c 8.1 (Berkeley) 7/19/93
42 */
43
44 /*-
45 * Copyright (c) 1995 The NetBSD Foundation, Inc. (Atari modifications)
46 * All rights reserved.
47 *
48 * This code is derived from software contributed to The NetBSD Foundation
49 * by Leo Weppelman.
50 *
51 * Redistribution and use in source and binary forms, with or without
52 * modification, are permitted provided that the following conditions
53 * are met:
54 * 1. Redistributions of source code must retain the above copyright
55 * notice, this list of conditions and the following disclaimer.
56 * 2. Redistributions in binary form must reproduce the above copyright
57 * notice, this list of conditions and the following disclaimer in the
58 * documentation and/or other materials provided with the distribution.
59 *
60 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
61 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
62 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
63 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
64 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
65 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
66 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
67 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
68 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
69 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
70 * POSSIBILITY OF SUCH DAMAGE.
71 */
72
73 /*
74 * Zilog Z8530 (ZSCC) driver.
75 *
76 * Runs two tty ports (modem2 and serial2) on zs0.
77 *
78 * This driver knows far too much about chip to usage mappings.
79 */
80
81 #include <sys/cdefs.h>
82 __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.70 2010/04/09 16:30:15 tsutsui Exp $");
83
84 #include <sys/param.h>
85 #include <sys/systm.h>
86 #include <sys/proc.h>
87 #include <sys/device.h>
88 #include <sys/conf.h>
89 #include <sys/file.h>
90 #include <sys/ioctl.h>
91 #include <sys/malloc.h>
92 #include <sys/tty.h>
93 #include <sys/time.h>
94 #include <sys/kernel.h>
95 #include <sys/syslog.h>
96 #include <sys/kauth.h>
97
98 #include <machine/cpu.h>
99 #include <machine/iomap.h>
100 #include <machine/scu.h>
101 #include <machine/mfp.h>
102 #include <atari/dev/ym2149reg.h>
103
104 #include <dev/ic/z8530reg.h>
105 #include <atari/dev/zsvar.h>
106
107 #include "ioconf.h"
108
109 #include "zs.h"
110 #if NZS > 1
111 #error "This driver supports only 1 85C30!"
112 #endif
113
114 #if NZS > 0
115
116 #define PCLK (8053976) /* PCLK pin input clock rate */
117 #define PCLK_HD (9600 * 1536) /* PCLK on Hades pin input clock rate */
118
119 #define splzs spl5
120
121 /*
122 * Software state per found chip.
123 */
124 struct zs_softc {
125 device_t sc_dev; /* base device */
126 struct zsdevice *sc_zs; /* chip registers */
127 struct zs_chanstate sc_cs[2]; /* chan A and B software state */
128 };
129
130 static void *zs_softint_cookie; /* for callback */
131 /*
132 * Define the registers for a closed port
133 */
134 static uint8_t zs_init_regs[16] = {
135 /* 0 */ 0,
136 /* 1 */ 0,
137 /* 2 */ 0x60,
138 /* 3 */ 0,
139 /* 4 */ 0,
140 /* 5 */ 0,
141 /* 6 */ 0,
142 /* 7 */ 0,
143 /* 8 */ 0,
144 /* 9 */ ZSWR9_MASTER_IE | ZSWR9_VECTOR_INCL_STAT,
145 /* 10 */ ZSWR10_NRZ,
146 /* 11 */ ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD,
147 /* 12 */ 0,
148 /* 13 */ 0,
149 /* 14 */ ZSWR14_BAUD_FROM_PCLK | ZSWR14_BAUD_ENA,
150 /* 15 */ 0
151 };
152
153 /*
154 * Define the machine dependant clock frequencies
155 * If BRgen feeds sender/receiver we always use a
156 * divisor 16, therefor the division by 16 can as
157 * well be done here.
158 */
159 static u_long zs_freqs_tt[] = {
160 /*
161 * Atari TT, RTxCB is generated by TT-MFP timer C,
162 * which is set to 307.2 kHz during initialisation
163 * and never changed afterwards.
164 */
165 PCLK/16, /* BRgen, PCLK, divisor 16 */
166 229500, /* BRgen, RTxCA, divisor 16 */
167 3672000, /* RTxCA, from PCLK4 */
168 0, /* TRxCA, external */
169
170 PCLK/16, /* BRgen, PCLK, divisor 16 */
171 19200, /* BRgen, RTxCB, divisor 16 */
172 307200, /* RTxCB, from TT-MFP TCO */
173 2457600 /* TRxCB, from BCLK */
174 };
175
176 static u_long zs_freqs_falcon[] = {
177 /*
178 * Atari Falcon, XXX no specs available, this might be wrong
179 */
180 PCLK/16, /* BRgen, PCLK, divisor 16 */
181 229500, /* BRgen, RTxCA, divisor 16 */
182 3672000, /* RTxCA, ??? */
183 0, /* TRxCA, external */
184
185 PCLK/16, /* BRgen, PCLK, divisor 16 */
186 229500, /* BRgen, RTxCB, divisor 16 */
187 3672000, /* RTxCB, ??? */
188 2457600 /* TRxCB, ??? */
189 };
190
191 static u_long zs_freqs_hades[] = {
192 /*
193 * XXX: Channel-A unchecked!!!!!
194 */
195 PCLK_HD/16, /* BRgen, PCLK, divisor 16 */
196 229500, /* BRgen, RTxCA, divisor 16 */
197 3672000, /* RTxCA, from PCLK4 */
198 0, /* TRxCA, external */
199
200 PCLK_HD/16, /* BRgen, PCLK, divisor 16 */
201 235550, /* BRgen, RTxCB, divisor 16 */
202 3768800, /* RTxCB, 3.7688MHz */
203 3768800 /* TRxCB, 3.7688MHz */
204 };
205
206 static u_long zs_freqs_generic[] = {
207 /*
208 * other machines, assume only PCLK is available
209 */
210 PCLK/16, /* BRgen, PCLK, divisor 16 */
211 0, /* BRgen, RTxCA, divisor 16 */
212 0, /* RTxCA, unknown */
213 0, /* TRxCA, unknown */
214
215 PCLK/16, /* BRgen, PCLK, divisor 16 */
216 0, /* BRgen, RTxCB, divisor 16 */
217 0, /* RTxCB, unknown */
218 0 /* TRxCB, unknown */
219 };
220 static u_long *zs_frequencies;
221
222 /* Definition of the driver for autoconfig. */
223 static int zsmatch(device_t, cfdata_t, void *);
224 static void zsattach(device_t, device_t, void *);
225
226 CFATTACH_DECL_NEW(zs, sizeof(struct zs_softc),
227 zsmatch, zsattach, NULL, NULL);
228
229 /* {b,c}devsw[] function prototypes */
230 dev_type_open(zsopen);
231 dev_type_close(zsclose);
232 dev_type_read(zsread);
233 dev_type_write(zswrite);
234 dev_type_ioctl(zsioctl);
235 dev_type_stop(zsstop);
236 dev_type_tty(zstty);
237 dev_type_poll(zspoll);
238
239 const struct cdevsw zs_cdevsw = {
240 zsopen, zsclose, zsread, zswrite, zsioctl,
241 zsstop, zstty, zspoll, nommap, ttykqfilter, D_TTY
242 };
243
244 /* Interrupt handlers. */
245 int zshard(long);
246 static int zssoft(long);
247 static int zsrint(struct zs_chanstate *, struct zschan *);
248 static int zsxint(struct zs_chanstate *, struct zschan *);
249 static int zssint(struct zs_chanstate *, struct zschan *);
250
251 static struct zs_chanstate *zslist;
252
253 /* Routines called from other code. */
254 static void zsstart(struct tty *);
255
256 /* Routines purely local to this driver. */
257 static void zsoverrun(int, long *, const char *);
258 static int zsparam(struct tty *, struct termios *);
259 static int zsbaudrate(int, int, int *, int *, int *, int *);
260 static int zs_modem(struct zs_chanstate *, int, int);
261 static void zs_loadchannelregs(struct zschan *, uint8_t *);
262 static void zs_shutdown(struct zs_chanstate *);
263
264 static int
265 zsmatch(device_t parent, cfdata_t cf, void *aux)
266 {
267 static int zs_matched = 0;
268
269 if (strcmp("zs", aux) || zs_matched)
270 return 0;
271 zs_matched = 1;
272 return 1;
273 }
274
275 /*
276 * Attach a found zs.
277 */
278 static void
279 zsattach(device_t parent, device_t self, void *aux)
280 {
281 struct zs_softc *sc;
282 struct zs_chanstate *cs;
283 struct zsdevice *addr;
284 uint8_t tmp;
285
286 addr = (struct zsdevice *)AD_SCC;
287 sc = device_private(self);
288 sc->sc_dev = self;
289 sc->sc_zs = addr;
290 cs = sc->sc_cs;
291
292 /*
293 * Get the command register into a known state.
294 */
295 tmp = addr->zs_chan[ZS_CHAN_A].zc_csr;
296 tmp = addr->zs_chan[ZS_CHAN_A].zc_csr;
297 tmp = addr->zs_chan[ZS_CHAN_B].zc_csr;
298 tmp = addr->zs_chan[ZS_CHAN_B].zc_csr;
299
300 /*
301 * Do a hardware reset.
302 */
303 ZS_WRITE(&addr->zs_chan[ZS_CHAN_A], 9, ZSWR9_HARD_RESET);
304 delay(50000); /*enough ? */
305 ZS_WRITE(&addr->zs_chan[ZS_CHAN_A], 9, 0);
306
307 /*
308 * Initialize both channels
309 */
310 zs_loadchannelregs(&addr->zs_chan[ZS_CHAN_A], zs_init_regs);
311 zs_loadchannelregs(&addr->zs_chan[ZS_CHAN_B], zs_init_regs);
312
313 if (machineid & ATARI_TT) {
314 /*
315 * ininitialise TT-MFP timer C: 307200Hz
316 * timer C and D share one control register:
317 * bits 0-2 control timer D
318 * bits 4-6 control timer C
319 */
320 int cr = MFP2->mf_tcdcr & 7;
321 MFP2->mf_tcdcr = cr; /* stop timer C */
322 MFP2->mf_tcdr = 1; /* counter 1 */
323 cr |= T_Q004 << 4; /* divisor 4 */
324 MFP2->mf_tcdcr = cr; /* start timer C */
325 /*
326 * enable scc related interrupts
327 */
328 SCU->vme_mask |= SCU_SCC;
329
330 zs_frequencies = zs_freqs_tt;
331 } else if (machineid & ATARI_FALCON) {
332 zs_frequencies = zs_freqs_falcon;
333 } else if (machineid & ATARI_HADES) {
334 zs_frequencies = zs_freqs_hades;
335 } else {
336 zs_frequencies = zs_freqs_generic;
337 }
338
339 /* link into interrupt list with order (A,B) (B=A+1) */
340 cs[0].cs_next = &cs[1];
341 cs[1].cs_next = zslist;
342 zslist = cs;
343
344 cs->cs_unit = 0;
345 cs->cs_zc = &addr->zs_chan[ZS_CHAN_A];
346 cs++;
347 cs->cs_unit = 1;
348 cs->cs_zc = &addr->zs_chan[ZS_CHAN_B];
349
350 zs_softint_cookie = softint_establish(SOFTINT_SERIAL,
351 (void (*)(void *))zssoft, 0);
352
353 printf(": serial2 on channel a and modem2 on channel b\n");
354 }
355
356 /*
357 * Open a zs serial port.
358 */
359 int
360 zsopen(dev_t dev, int flags, int mode, struct lwp *l)
361 {
362 struct tty *tp;
363 struct zs_chanstate *cs;
364 struct zs_softc *sc;
365 int unit = ZS_UNIT(dev);
366 int zs = unit >> 1;
367 int error, s;
368
369 sc = device_lookup_private(&zs_cd, zs);
370 if (sc == NULL)
371 return ENXIO;
372 cs = &sc->sc_cs[unit & 1];
373
374 /*
375 * When port A (ser02) is selected on the TT, make sure
376 * the port is enabled.
377 */
378 if ((machineid & ATARI_TT) && !(unit & 1))
379 ym2149_ser2(1);
380
381 if (cs->cs_rbuf == NULL) {
382 cs->cs_rbuf = malloc(ZLRB_RING_SIZE * sizeof(int), M_DEVBUF,
383 M_WAITOK);
384 }
385
386 tp = cs->cs_ttyp;
387 if (tp == NULL) {
388 cs->cs_ttyp = tp = ttymalloc();
389 tty_attach(tp);
390 tp->t_dev = dev;
391 tp->t_oproc = zsstart;
392 tp->t_param = zsparam;
393 }
394
395 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp))
396 return EBUSY;
397
398 s = spltty();
399
400 /*
401 * Do the following iff this is a first open.
402 */
403 if ((tp->t_state & TS_ISOPEN) == 0 && tp->t_wopen == 0) {
404 if (tp->t_ispeed == 0) {
405 tp->t_iflag = TTYDEF_IFLAG;
406 tp->t_oflag = TTYDEF_OFLAG;
407 tp->t_cflag = TTYDEF_CFLAG;
408 tp->t_lflag = TTYDEF_LFLAG;
409 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED;
410 }
411 ttychars(tp);
412 ttsetwater(tp);
413
414 (void)zsparam(tp, &tp->t_termios);
415
416 /*
417 * Turn on DTR. We must always do this, even if carrier is not
418 * present, because otherwise we'd have to use TIOCSDTR
419 * immediately after setting CLOCAL, which applications do not
420 * expect. We always assert DTR while the device is open
421 * unless explicitly requested to deassert it.
422 */
423 zs_modem(cs, ZSWR5_RTS|ZSWR5_DTR, DMSET);
424 /* May never get a status intr. if DCD already on. -gwr */
425 if (((cs->cs_rr0 = cs->cs_zc->zc_csr) & ZSRR0_DCD) != 0)
426 tp->t_state |= TS_CARR_ON;
427 if (cs->cs_softcar)
428 tp->t_state |= TS_CARR_ON;
429 }
430
431 splx(s);
432
433 error = ttyopen(tp, ZS_DIALOUT(dev), (flags & O_NONBLOCK));
434 if (error)
435 goto bad;
436
437 error = tp->t_linesw->l_open(dev, tp);
438 if (error)
439 goto bad;
440 return 0;
441
442 bad:
443 if ((tp->t_state & TS_ISOPEN) == 0 && tp->t_wopen == 0) {
444 /*
445 * We failed to open the device, and nobody else had it opened.
446 * Clean up the state as appropriate.
447 */
448 zs_shutdown(cs);
449 }
450 return error;
451 }
452
453 /*
454 * Close a zs serial port.
455 */
456 int
457 zsclose(dev_t dev, int flags, int mode, struct lwp *l)
458 {
459 struct zs_chanstate *cs;
460 struct tty *tp;
461 struct zs_softc *sc;
462 int unit = ZS_UNIT(dev);
463
464 sc = device_lookup_private(&zs_cd, unit >> 1);
465 cs = &sc->sc_cs[unit & 1];
466 tp = cs->cs_ttyp;
467
468 tp->t_linesw->l_close(tp, flags);
469 ttyclose(tp);
470
471 if ((tp->t_state & TS_ISOPEN) == 0 && tp->t_wopen == 0) {
472 /*
473 * Although we got a last close, the device may still be in
474 * use; e.g. if this was the dialout node, and there are still
475 * processes waiting for carrier on the non-dialout node.
476 */
477 zs_shutdown(cs);
478 }
479 return 0;
480 }
481
482 /*
483 * Read/write zs serial port.
484 */
485 int
486 zsread(dev_t dev, struct uio *uio, int flags)
487 {
488 struct zs_chanstate *cs;
489 struct zs_softc *sc;
490 struct tty *tp;
491 int unit;
492
493 unit = ZS_UNIT(dev);
494 sc = device_lookup_private(&zs_cd, unit >> 1);
495 cs = &sc->sc_cs[unit & 1];
496 tp = cs->cs_ttyp;
497
498 return (*tp->t_linesw->l_read)(tp, uio, flags);
499 }
500
501 int
502 zswrite(dev_t dev, struct uio *uio, int flags)
503 {
504 struct zs_chanstate *cs;
505 struct zs_softc *sc;
506 struct tty *tp;
507 int unit;
508
509 unit = ZS_UNIT(dev);
510 sc = device_lookup_private(&zs_cd, unit >> 1);
511 cs = &sc->sc_cs[unit & 1];
512 tp = cs->cs_ttyp;
513
514 return (*tp->t_linesw->l_write)(tp, uio, flags);
515 }
516
517 int
518 zspoll(dev_t dev, int events, struct lwp *l)
519 {
520 struct zs_chanstate *cs;
521 struct zs_softc *sc;
522 struct tty *tp;
523 int unit;
524
525 unit = ZS_UNIT(dev);
526 sc = device_lookup_private(&zs_cd, unit >> 1);
527 cs = &sc->sc_cs[unit & 1];
528 tp = cs->cs_ttyp;
529
530 return (*tp->t_linesw->l_poll)(tp, events, l);
531 }
532
533 struct tty *
534 zstty(dev_t dev)
535 {
536 struct zs_chanstate *cs;
537 struct zs_softc *sc;
538 int unit;
539
540 unit = ZS_UNIT(dev);
541 sc = device_lookup_private(&zs_cd, unit >> 1);
542 cs = &sc->sc_cs[unit & 1];
543 return cs->cs_ttyp;
544 }
545
546 /*
547 * ZS hardware interrupt. Scan all ZS channels. NB: we know here that
548 * channels are kept in (A,B) pairs.
549 *
550 * Do just a little, then get out; set a software interrupt if more
551 * work is needed.
552 *
553 * We deliberately ignore the vectoring Zilog gives us, and match up
554 * only the number of `reset interrupt under service' operations, not
555 * the order.
556 */
557
558 int
559 zshard(long sr)
560 {
561 struct zs_chanstate *a;
562 #define b (a + 1)
563 struct zschan *zc;
564 int rr3, intflags = 0, v, i;
565
566 do {
567 intflags &= ~4;
568 for (a = zslist; a != NULL; a = b->cs_next) {
569 rr3 = ZS_READ(a->cs_zc, 3);
570 if (rr3 & (ZSRR3_IP_A_RX | ZSRR3_IP_A_TX |
571 ZSRR3_IP_A_STAT)) {
572 intflags |= 4 | 2;
573 zc = a->cs_zc;
574 i = a->cs_rbput;
575 if ((rr3 & ZSRR3_IP_A_RX) != 0 &&
576 (v = zsrint(a, zc)) != 0) {
577 a->cs_rbuf[i++ & ZLRB_RING_MASK] = v;
578 intflags |= 1;
579 }
580 if ((rr3 & ZSRR3_IP_A_TX) != 0 &&
581 (v = zsxint(a, zc)) != 0) {
582 a->cs_rbuf[i++ & ZLRB_RING_MASK] = v;
583 intflags |= 1;
584 }
585 if ((rr3 & ZSRR3_IP_A_STAT) != 0 &&
586 (v = zssint(a, zc)) != 0) {
587 a->cs_rbuf[i++ & ZLRB_RING_MASK] = v;
588 intflags |= 1;
589 }
590 a->cs_rbput = i;
591 }
592 if (rr3 & (ZSRR3_IP_B_RX | ZSRR3_IP_B_TX |
593 ZSRR3_IP_B_STAT)) {
594 intflags |= 4 | 2;
595 zc = b->cs_zc;
596 i = b->cs_rbput;
597 if ((rr3 & ZSRR3_IP_B_RX) != 0 &&
598 (v = zsrint(b, zc)) != 0) {
599 b->cs_rbuf[i++ & ZLRB_RING_MASK] = v;
600 intflags |= 1;
601 }
602 if ((rr3 & ZSRR3_IP_B_TX) != 0 &&
603 (v = zsxint(b, zc)) != 0) {
604 b->cs_rbuf[i++ & ZLRB_RING_MASK] = v;
605 intflags |= 1;
606 }
607 if ((rr3 & ZSRR3_IP_B_STAT) != 0 &&
608 (v = zssint(b, zc)) != 0) {
609 b->cs_rbuf[i++ & ZLRB_RING_MASK] = v;
610 intflags |= 1;
611 }
612 b->cs_rbput = i;
613 }
614 }
615 } while (intflags & 4);
616 #undef b
617
618 if (intflags & 1)
619 softint_schedule(zs_softint_cookie);
620
621 return intflags & 2;
622 }
623
624 static int
625 zsrint(struct zs_chanstate *cs, struct zschan *zc)
626 {
627 int c;
628
629 /*
630 * First read the status, because read of the received char
631 * destroy the status of this char.
632 */
633 c = ZS_READ(zc, 1);
634 c |= (zc->zc_data << 8);
635
636 /* clear receive error & interrupt condition */
637 zc->zc_csr = ZSWR0_RESET_ERRORS;
638 zc->zc_csr = ZSWR0_CLR_INTR;
639
640 return ZRING_MAKE(ZRING_RINT, c);
641 }
642
643 static int
644 zsxint(struct zs_chanstate *cs, struct zschan *zc)
645 {
646 int i = cs->cs_tbc;
647
648 if (i == 0) {
649 zc->zc_csr = ZSWR0_RESET_TXINT;
650 zc->zc_csr = ZSWR0_CLR_INTR;
651 return ZRING_MAKE(ZRING_XINT, 0);
652 }
653 cs->cs_tbc = i - 1;
654 zc->zc_data = *cs->cs_tba++;
655 zc->zc_csr = ZSWR0_CLR_INTR;
656 return 0;
657 }
658
659 static int
660 zssint(struct zs_chanstate *cs, struct zschan *zc)
661 {
662 int rr0;
663
664 rr0 = zc->zc_csr;
665 zc->zc_csr = ZSWR0_RESET_STATUS;
666 zc->zc_csr = ZSWR0_CLR_INTR;
667 /*
668 * The chip's hardware flow control is, as noted in zsreg.h,
669 * busted---if the DCD line goes low the chip shuts off the
670 * receiver (!). If we want hardware CTS flow control but do
671 * not have it, and carrier is now on, turn HFC on; if we have
672 * HFC now but carrier has gone low, turn it off.
673 */
674 if (rr0 & ZSRR0_DCD) {
675 if (cs->cs_ttyp->t_cflag & CCTS_OFLOW &&
676 (cs->cs_creg[3] & ZSWR3_HFC) == 0) {
677 cs->cs_creg[3] |= ZSWR3_HFC;
678 ZS_WRITE(zc, 3, cs->cs_creg[3]);
679 }
680 } else {
681 if (cs->cs_creg[3] & ZSWR3_HFC) {
682 cs->cs_creg[3] &= ~ZSWR3_HFC;
683 ZS_WRITE(zc, 3, cs->cs_creg[3]);
684 }
685 }
686 return ZRING_MAKE(ZRING_SINT, rr0);
687 }
688
689 /*
690 * Print out a ring or fifo overrun error message.
691 */
692 static void
693 zsoverrun(int unit, long *ptime, const char *what)
694 {
695 time_t cur_sec = time_second;
696
697 if (*ptime != cur_sec) {
698 *ptime = cur_sec;
699 log(LOG_WARNING, "zs%d%c: %s overrun\n", unit >> 1,
700 (unit & 1) + 'a', what);
701 }
702 }
703
704 /*
705 * ZS software interrupt. Scan all channels for deferred interrupts.
706 */
707 int
708 zssoft(long sr)
709 {
710 struct zs_chanstate *cs;
711 struct zschan *zc;
712 struct linesw *line;
713 struct tty *tp;
714 int get, n, c, cc, unit, s;
715 int retval = 0;
716
717 s = spltty();
718 for (cs = zslist; cs != NULL; cs = cs->cs_next) {
719 get = cs->cs_rbget;
720 again:
721 n = cs->cs_rbput; /* atomic */
722 if (get == n) /* nothing more on this line */
723 continue;
724 retval = 1;
725 unit = cs->cs_unit; /* set up to handle interrupts */
726 zc = cs->cs_zc;
727 tp = cs->cs_ttyp;
728 line = tp->t_linesw;
729 /*
730 * Compute the number of interrupts in the receive ring.
731 * If the count is overlarge, we lost some events, and
732 * must advance to the first valid one. It may get
733 * overwritten if more data are arriving, but this is
734 * too expensive to check and gains nothing (we already
735 * lost out; all we can do at this point is trade one
736 * kind of loss for another).
737 */
738 n -= get;
739 if (n > ZLRB_RING_SIZE) {
740 zsoverrun(unit, &cs->cs_rotime, "ring");
741 get += n - ZLRB_RING_SIZE;
742 n = ZLRB_RING_SIZE;
743 }
744 while (--n >= 0) {
745 /* race to keep ahead of incoming interrupts */
746 c = cs->cs_rbuf[get++ & ZLRB_RING_MASK];
747 switch (ZRING_TYPE(c)) {
748
749 case ZRING_RINT:
750 c = ZRING_VALUE(c);
751 if ((c & ZSRR1_DO) != 0)
752 zsoverrun(unit, &cs->cs_fotime, "fifo");
753 cc = c >> 8;
754 if ((c & ZSRR1_FE) != 0)
755 cc |= TTY_FE;
756 if ((c & ZSRR1_PE) != 0)
757 cc |= TTY_PE;
758 line->l_rint(cc, tp);
759 break;
760
761 case ZRING_XINT:
762 /*
763 * Transmit done: change registers and resume,
764 * or clear BUSY.
765 */
766 if (cs->cs_heldchange) {
767 int sps;
768
769 sps = splzs();
770 c = zc->zc_csr;
771 if ((c & ZSRR0_DCD) == 0)
772 cs->cs_preg[3] &= ~ZSWR3_HFC;
773 memcpy((void *)cs->cs_creg,
774 (void *)cs->cs_preg, 16);
775 zs_loadchannelregs(zc, cs->cs_creg);
776 splx(sps);
777 cs->cs_heldchange = 0;
778 if (cs->cs_heldtbc &&
779 (tp->t_state & TS_TTSTOP) == 0) {
780 cs->cs_tbc = cs->cs_heldtbc - 1;
781 zc->zc_data = *cs->cs_tba++;
782 goto again;
783 }
784 }
785 tp->t_state &= ~TS_BUSY;
786 if ((tp->t_state & TS_FLUSH) != 0)
787 tp->t_state &= ~TS_FLUSH;
788 else
789 ndflush(&tp->t_outq,
790 cs->cs_tba - tp->t_outq.c_cf);
791 line->l_start(tp);
792 break;
793
794 case ZRING_SINT:
795 /*
796 * Status line change. HFC bit is run in
797 * hardware interrupt, to avoid locking
798 * at splzs here.
799 */
800 c = ZRING_VALUE(c);
801 if (((c ^ cs->cs_rr0) & ZSRR0_DCD) != 0) {
802 cc = (c & ZSRR0_DCD) != 0;
803 if (line->l_modem(tp, cc) == 0)
804 zs_modem(cs,
805 ZSWR5_RTS | ZSWR5_DTR,
806 cc ? DMBIS : DMBIC);
807 }
808 cs->cs_rr0 = c;
809 break;
810
811 default:
812 log(LOG_ERR, "zs%d%c: bad ZRING_TYPE (%x)\n",
813 unit >> 1, (unit & 1) + 'a', c);
814 break;
815 }
816 }
817 cs->cs_rbget = get;
818 goto again;
819 }
820 splx(s);
821 return retval;
822 }
823
824 int
825 zsioctl(dev_t dev, u_long cmd, void * data, int flag, struct lwp *l)
826 {
827 int unit = ZS_UNIT(dev);
828 struct zs_softc *sc = device_lookup_private(&zs_cd, unit >> 1);
829 struct tty *tp = sc->sc_cs[unit & 1].cs_ttyp;
830 int error, s;
831 struct zs_chanstate *cs = &sc->sc_cs[unit & 1];
832
833 error = tp->t_linesw->l_ioctl(tp, cmd, data, flag, l);
834 if (error != EPASSTHROUGH)
835 return error;
836
837 error = ttioctl(tp, cmd, data, flag, l);
838 if (error !=EPASSTHROUGH)
839 return error;
840
841 switch (cmd) {
842 case TIOCSBRK:
843 s = splzs();
844 cs->cs_preg[5] |= ZSWR5_BREAK;
845 cs->cs_creg[5] |= ZSWR5_BREAK;
846 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]);
847 splx(s);
848 break;
849 case TIOCCBRK:
850 s = splzs();
851 cs->cs_preg[5] &= ~ZSWR5_BREAK;
852 cs->cs_creg[5] &= ~ZSWR5_BREAK;
853 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]);
854 splx(s);
855 break;
856 case TIOCGFLAGS: {
857 int bits = 0;
858
859 if (cs->cs_softcar)
860 bits |= TIOCFLAG_SOFTCAR;
861 if ((cs->cs_creg[15] & ZSWR15_DCD_IE) != 0)
862 bits |= TIOCFLAG_CLOCAL;
863 if ((cs->cs_creg[3] & ZSWR3_HFC) != 0)
864 bits |= TIOCFLAG_CRTSCTS;
865 *(int *)data = bits;
866 break;
867 }
868 case TIOCSFLAGS: {
869 int userbits = 0;
870
871 error = kauth_authorize_device_tty(l->l_cred,
872 KAUTH_DEVICE_TTY_PRIVSET, tp);
873 if (error != 0)
874 return EPERM;
875
876 userbits = *(int *)data;
877
878 /*
879 * can have `local' or `softcar', and `rtscts' or `mdmbuf'
880 # defaulting to software flow control.
881 */
882 if ((userbits & TIOCFLAG_SOFTCAR) != 0 &&
883 (userbits & TIOCFLAG_CLOCAL) != 0)
884 return EINVAL;
885 if ((userbits & TIOCFLAG_MDMBUF) != 0)
886 /* don't support this (yet?) */
887 return ENODEV;
888
889 s = splzs();
890 if ((userbits & TIOCFLAG_SOFTCAR) != 0) {
891 cs->cs_softcar = 1; /* turn on softcar */
892 cs->cs_preg[15] &= ~ZSWR15_DCD_IE; /* turn off dcd */
893 cs->cs_creg[15] &= ~ZSWR15_DCD_IE;
894 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]);
895 } else if ((userbits & TIOCFLAG_CLOCAL) != 0) {
896 cs->cs_softcar = 0; /* turn off softcar */
897 cs->cs_preg[15] |= ZSWR15_DCD_IE; /* turn on dcd */
898 cs->cs_creg[15] |= ZSWR15_DCD_IE;
899 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]);
900 tp->t_termios.c_cflag |= CLOCAL;
901 }
902 if ((userbits & TIOCFLAG_CRTSCTS) != 0) {
903 cs->cs_preg[15] |= ZSWR15_CTS_IE;
904 cs->cs_creg[15] |= ZSWR15_CTS_IE;
905 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]);
906 cs->cs_preg[3] |= ZSWR3_HFC;
907 cs->cs_creg[3] |= ZSWR3_HFC;
908 ZS_WRITE(cs->cs_zc, 3, cs->cs_creg[3]);
909 tp->t_termios.c_cflag |= CRTSCTS;
910 } else {
911 /* no mdmbuf, so we must want software flow control */
912 cs->cs_preg[15] &= ~ZSWR15_CTS_IE;
913 cs->cs_creg[15] &= ~ZSWR15_CTS_IE;
914 ZS_WRITE(cs->cs_zc, 15, cs->cs_creg[15]);
915 cs->cs_preg[3] &= ~ZSWR3_HFC;
916 cs->cs_creg[3] &= ~ZSWR3_HFC;
917 ZS_WRITE(cs->cs_zc, 3, cs->cs_creg[3]);
918 tp->t_termios.c_cflag &= ~CRTSCTS;
919 }
920 splx(s);
921 break;
922 }
923 case TIOCSDTR:
924 zs_modem(cs, ZSWR5_DTR, DMBIS);
925 break;
926 case TIOCCDTR:
927 zs_modem(cs, ZSWR5_DTR, DMBIC);
928 break;
929 case TIOCMGET:
930 zs_modem(cs, 0, DMGET);
931 break;
932 case TIOCMSET:
933 case TIOCMBIS:
934 case TIOCMBIC:
935 default:
936 return EPASSTHROUGH;
937 }
938 return 0;
939 }
940
941 /*
942 * Start or restart transmission.
943 */
944 static void
945 zsstart(struct tty *tp)
946 {
947 struct zs_chanstate *cs;
948 int s, nch;
949 int unit = ZS_UNIT(tp->t_dev);
950 struct zs_softc *sc = device_lookup_private(&zs_cd, unit >> 1);
951
952 cs = &sc->sc_cs[unit & 1];
953 s = spltty();
954
955 /*
956 * If currently active or delaying, no need to do anything.
957 */
958 if ((tp->t_state & (TS_TIMEOUT | TS_BUSY | TS_TTSTOP)) != 0)
959 goto out;
960
961 /*
962 * If there are sleepers, and output has drained below low
963 * water mark, awaken.
964 */
965 ttypull(tp);
966
967 nch = ndqb(&tp->t_outq, 0); /* XXX */
968 if (nch) {
969 char *p = tp->t_outq.c_cf;
970
971 /* mark busy, enable tx done interrupts, & send first byte */
972 tp->t_state |= TS_BUSY;
973 (void)splzs();
974 cs->cs_preg[1] |= ZSWR1_TIE;
975 cs->cs_creg[1] |= ZSWR1_TIE;
976 ZS_WRITE(cs->cs_zc, 1, cs->cs_creg[1]);
977 cs->cs_zc->zc_data = *p;
978 cs->cs_tba = p + 1;
979 cs->cs_tbc = nch - 1;
980 } else {
981 /*
982 * Nothing to send, turn off transmit done interrupts.
983 * This is useful if something is doing polled output.
984 */
985 (void)splzs();
986 cs->cs_preg[1] &= ~ZSWR1_TIE;
987 cs->cs_creg[1] &= ~ZSWR1_TIE;
988 ZS_WRITE(cs->cs_zc, 1, cs->cs_creg[1]);
989 }
990 out:
991 splx(s);
992 }
993
994 /*
995 * Stop output, e.g., for ^S or output flush.
996 */
997 void
998 zsstop(struct tty *tp, int flag)
999 {
1000 struct zs_chanstate *cs;
1001 int s, unit = ZS_UNIT(tp->t_dev);
1002 struct zs_softc *sc = device_lookup_private(&zs_cd, unit >> 1);
1003
1004 cs = &sc->sc_cs[unit & 1];
1005 s = splzs();
1006 if ((tp->t_state & TS_BUSY) != 0) {
1007 /*
1008 * Device is transmitting; must stop it.
1009 */
1010 cs->cs_tbc = 0;
1011 if ((tp->t_state & TS_TTSTOP) == 0)
1012 tp->t_state |= TS_FLUSH;
1013 }
1014 splx(s);
1015 }
1016
1017 static void
1018 zs_shutdown(struct zs_chanstate *cs)
1019 {
1020 struct tty *tp = cs->cs_ttyp;
1021 int s;
1022
1023 s = splzs();
1024
1025 /*
1026 * Hang up if necessary. Wait a bit, so the other side has time to
1027 * notice even if we immediately open the port again.
1028 */
1029 if ((tp->t_cflag & HUPCL) != 0) {
1030 zs_modem(cs, 0, DMSET);
1031 (void)tsleep((void *)cs, TTIPRI, ttclos, hz);
1032 }
1033
1034 /* Clear any break condition set with TIOCSBRK. */
1035 if ((cs->cs_creg[5] & ZSWR5_BREAK) != 0) {
1036 cs->cs_preg[5] &= ~ZSWR5_BREAK;
1037 cs->cs_creg[5] &= ~ZSWR5_BREAK;
1038 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]);
1039 }
1040
1041 /*
1042 * Drop all lines and cancel interrupts
1043 */
1044 zs_loadchannelregs(cs->cs_zc, zs_init_regs);
1045 splx(s);
1046 }
1047
1048 /*
1049 * Set ZS tty parameters from termios.
1050 *
1051 * This routine makes use of the fact that only registers
1052 * 1, 3, 4, 5, 9, 10, 11, 12, 13, 14, and 15 are written.
1053 */
1054 static int
1055 zsparam(struct tty *tp, struct termios *t)
1056 {
1057 int unit = ZS_UNIT(tp->t_dev);
1058 struct zs_softc *sc = device_lookup_private(&zs_cd, unit >> 1);
1059 struct zs_chanstate *cs = &sc->sc_cs[unit & 1];
1060 int cdiv = 0; /* XXX gcc4 -Wuninitialized */
1061 int clkm = 0; /* XXX gcc4 -Wuninitialized */
1062 int brgm = 0; /* XXX gcc4 -Wuninitialized */
1063 int tcon = 0; /* XXX gcc4 -Wuninitialized */
1064 int tmp, tmp5, cflag, s;
1065
1066 tmp = t->c_ospeed;
1067 tmp5 = t->c_ispeed;
1068 if (tmp < 0 || (tmp5 && tmp5 != tmp))
1069 return EINVAL;
1070 if (tmp == 0) {
1071 /* stty 0 => drop DTR and RTS */
1072 zs_modem(cs, 0, DMSET);
1073 return 0;
1074 }
1075 tmp = zsbaudrate(unit, tmp, &cdiv, &clkm, &brgm, &tcon);
1076 if (tmp < 0)
1077 return EINVAL;
1078 tp->t_ispeed = tp->t_ospeed = tmp;
1079
1080 cflag = tp->t_cflag = t->c_cflag;
1081 if ((cflag & CSTOPB) != 0)
1082 cdiv |= ZSWR4_TWOSB;
1083 else
1084 cdiv |= ZSWR4_ONESB;
1085 if ((cflag & PARODD) == 0)
1086 cdiv |= ZSWR4_EVENP;
1087 if ((cflag & PARENB) != 0)
1088 cdiv |= ZSWR4_PARENB;
1089
1090 switch (cflag & CSIZE) {
1091 case CS5:
1092 tmp = ZSWR3_RX_5;
1093 tmp5 = ZSWR5_TX_5;
1094 break;
1095 case CS6:
1096 tmp = ZSWR3_RX_6;
1097 tmp5 = ZSWR5_TX_6;
1098 break;
1099 case CS7:
1100 tmp = ZSWR3_RX_7;
1101 tmp5 = ZSWR5_TX_7;
1102 break;
1103 case CS8:
1104 default:
1105 tmp = ZSWR3_RX_8;
1106 tmp5 = ZSWR5_TX_8;
1107 break;
1108 }
1109 tmp |= ZSWR3_RX_ENABLE;
1110 tmp5 |= ZSWR5_TX_ENABLE | ZSWR5_DTR | ZSWR5_RTS;
1111
1112 /*
1113 * Block interrupts so that state will not
1114 * be altered until we are done setting it up.
1115 */
1116 s = splzs();
1117 cs->cs_preg[4] = cdiv;
1118 cs->cs_preg[11] = clkm;
1119 cs->cs_preg[12] = tcon;
1120 cs->cs_preg[13] = tcon >> 8;
1121 cs->cs_preg[14] = brgm;
1122 cs->cs_preg[1] = ZSWR1_RIE | ZSWR1_TIE | ZSWR1_SIE;
1123 cs->cs_preg[9] = ZSWR9_MASTER_IE | ZSWR9_VECTOR_INCL_STAT;
1124 cs->cs_preg[10] = ZSWR10_NRZ;
1125 cs->cs_preg[15] = ZSWR15_BREAK_IE | ZSWR15_DCD_IE;
1126
1127 /*
1128 * Output hardware flow control on the chip is horrendous: if
1129 * carrier detect drops, the receiver is disabled. Hence we
1130 * can only do this when the carrier is on.
1131 */
1132 if ((cflag & CCTS_OFLOW) != 0 &&
1133 (cs->cs_zc->zc_csr & ZSRR0_DCD) != 0)
1134 tmp |= ZSWR3_HFC;
1135 cs->cs_preg[3] = tmp;
1136 cs->cs_preg[5] = tmp5;
1137
1138 /*
1139 * If nothing is being transmitted, set up new current values,
1140 * else mark them as pending.
1141 */
1142 if (cs->cs_heldchange == 0) {
1143 if ((cs->cs_ttyp->t_state & TS_BUSY) != 0) {
1144 cs->cs_heldtbc = cs->cs_tbc;
1145 cs->cs_tbc = 0;
1146 cs->cs_heldchange = 1;
1147 } else {
1148 memcpy((void *)cs->cs_creg, (void *)cs->cs_preg, 16);
1149 zs_loadchannelregs(cs->cs_zc, cs->cs_creg);
1150 }
1151 }
1152 splx(s);
1153 return 0;
1154 }
1155
1156 /*
1157 * search for the best matching baudrate
1158 */
1159 static int
1160 zsbaudrate(int unit, int wanted, int *divisor, int *clockmode, int *brgenmode,
1161 int *timeconst)
1162 {
1163 int bestdiff, bestbps, source;
1164
1165 bestdiff = bestbps = 0;
1166 unit = (unit & 1) << 2;
1167 for (source = 0; source < 4; ++source) {
1168 long freq = zs_frequencies[unit + source];
1169 int diff, bps, div, clkm, brgm, tcon;
1170
1171 bps = div = clkm = brgm = tcon = 0;
1172 switch (source) {
1173 case 0: /* BRgen, PCLK */
1174 brgm = ZSWR14_BAUD_ENA|ZSWR14_BAUD_FROM_PCLK;
1175 break;
1176 case 1: /* BRgen, RTxC */
1177 brgm = ZSWR14_BAUD_ENA;
1178 break;
1179 case 2: /* RTxC */
1180 clkm = ZSWR11_RXCLK_RTXC|ZSWR11_TXCLK_RTXC;
1181 break;
1182 case 3: /* TRxC */
1183 clkm = ZSWR11_RXCLK_TRXC|ZSWR11_TXCLK_TRXC;
1184 break;
1185 }
1186 switch (source) {
1187 case 0:
1188 case 1:
1189 div = ZSWR4_CLK_X16;
1190 clkm = ZSWR11_RXCLK_BAUD|ZSWR11_TXCLK_BAUD;
1191 tcon = BPS_TO_TCONST(freq, wanted);
1192 if (tcon < 0)
1193 tcon = 0;
1194 bps = TCONST_TO_BPS(freq, tcon);
1195 break;
1196 case 2:
1197 case 3:
1198 {
1199 int b1 = freq / 16, d1 = abs(b1 - wanted);
1200 int b2 = freq / 32, d2 = abs(b2 - wanted);
1201 int b3 = freq / 64, d3 = abs(b3 - wanted);
1202
1203 if (d1 < d2 && d1 < d3) {
1204 div = ZSWR4_CLK_X16;
1205 bps = b1;
1206 } else if (d2 < d3 && d2 < d1) {
1207 div = ZSWR4_CLK_X32;
1208 bps = b2;
1209 } else {
1210 div = ZSWR4_CLK_X64;
1211 bps = b3;
1212 }
1213 brgm = tcon = 0;
1214 break;
1215 }
1216 }
1217 diff = abs(bps - wanted);
1218 if (!source || diff < bestdiff) {
1219 *divisor = div;
1220 *clockmode = clkm;
1221 *brgenmode = brgm;
1222 *timeconst = tcon;
1223 bestbps = bps;
1224 bestdiff = diff;
1225 if (diff == 0)
1226 break;
1227 }
1228 }
1229 /* Allow deviations upto 5% */
1230 if (20 * bestdiff > wanted)
1231 return -1;
1232 return bestbps;
1233 }
1234
1235 /*
1236 * Raise or lower modem control (DTR/RTS) signals. If a character is
1237 * in transmission, the change is deferred.
1238 */
1239 static int
1240 zs_modem(struct zs_chanstate *cs, int bits, int how)
1241 {
1242 int s, mbits;
1243
1244 bits &= ZSWR5_DTR | ZSWR5_RTS;
1245
1246 s = splzs();
1247 mbits = cs->cs_preg[5] & (ZSWR5_DTR | ZSWR5_RTS);
1248
1249 switch (how) {
1250 case DMSET:
1251 mbits = bits;
1252 break;
1253 case DMBIS:
1254 mbits |= bits;
1255 break;
1256 case DMBIC:
1257 mbits &= ~bits;
1258 break;
1259 case DMGET:
1260 splx(s);
1261 return mbits;
1262 }
1263
1264 cs->cs_preg[5] = (cs->cs_preg[5] & ~(ZSWR5_DTR | ZSWR5_RTS)) | mbits;
1265 if (cs->cs_heldchange == 0) {
1266 if ((cs->cs_ttyp->t_state & TS_BUSY) != 0) {
1267 cs->cs_heldtbc = cs->cs_tbc;
1268 cs->cs_tbc = 0;
1269 cs->cs_heldchange = 1;
1270 } else {
1271 ZS_WRITE(cs->cs_zc, 5, cs->cs_creg[5]);
1272 }
1273 }
1274 splx(s);
1275 return 0;
1276 }
1277
1278 /*
1279 * Write the given register set to the given zs channel in the proper order.
1280 * The channel must not be transmitting at the time. The receiver will
1281 * be disabled for the time it takes to write all the registers.
1282 */
1283 static void
1284 zs_loadchannelregs(struct zschan *zc, uint8_t *reg)
1285 {
1286 int i;
1287
1288 zc->zc_csr = ZSM_RESET_ERR; /* reset error condition */
1289 i = zc->zc_data; /* drain fifo */
1290 i = zc->zc_data;
1291 i = zc->zc_data;
1292 ZS_WRITE(zc, 4, reg[4]);
1293 ZS_WRITE(zc, 10, reg[10]);
1294 ZS_WRITE(zc, 3, reg[3] & ~ZSWR3_RX_ENABLE);
1295 ZS_WRITE(zc, 5, reg[5] & ~ZSWR5_TX_ENABLE);
1296 ZS_WRITE(zc, 1, reg[1]);
1297 ZS_WRITE(zc, 9, reg[9]);
1298 ZS_WRITE(zc, 11, reg[11]);
1299 ZS_WRITE(zc, 12, reg[12]);
1300 ZS_WRITE(zc, 13, reg[13]);
1301 ZS_WRITE(zc, 14, reg[14]);
1302 ZS_WRITE(zc, 15, reg[15]);
1303 ZS_WRITE(zc, 3, reg[3]);
1304 ZS_WRITE(zc, 5, reg[5]);
1305 }
1306 #endif /* NZS > 1 */
1307