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zsvar.h revision 1.5 
      1 /*	$NetBSD: zsvar.h,v 1.5 1996/01/24 19:26:40 gwr Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1995 Leo Weppelman (Atari modifications)
      5  * Copyright (c) 1992, 1993
      6  *	The Regents of the University of California.  All rights reserved.
      7  *
      8  * This software was developed by the Computer Systems Engineering group
      9  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
     10  * contributed to Berkeley.
     11  *
     12  * All advertising materials mentioning features or use of this software
     13  * must display the following acknowledgement:
     14  *	This product includes software developed by the University of
     15  *	California, Lawrence Berkeley Laboratory.
     16  *
     17  * Redistribution and use in source and binary forms, with or without
     18  * modification, are permitted provided that the following conditions
     19  * are met:
     20  * 1. Redistributions of source code must retain the above copyright
     21  *    notice, this list of conditions and the following disclaimer.
     22  * 2. Redistributions in binary form must reproduce the above copyright
     23  *    notice, this list of conditions and the following disclaimer in the
     24  *    documentation and/or other materials provided with the distribution.
     25  * 3. All advertising materials mentioning features or use of this software
     26  *    must display the following acknowledgement:
     27  *	This product includes software developed by the University of
     28  *	California, Berkeley and its contributors.
     29  * 4. Neither the name of the University nor the names of its contributors
     30  *    may be used to endorse or promote products derived from this software
     31  *    without specific prior written permission.
     32  *
     33  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     34  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     35  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     36  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     37  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     38  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     39  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     40  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     41  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     42  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     43  * SUCH DAMAGE.
     44  *
     45  *	@(#)zsvar.h	8.1 (Berkeley) 6/11/93
     46  */
     47 
     48 /*
     49  * Register layout is machine-dependent...
     50  */
     51 
     52 struct zschan {
     53 	u_char		zc_xxx0;
     54 	volatile u_char	zc_csr;		/* ctrl,status, and indirect access */
     55 	u_char		zc_xxx1;
     56 	volatile u_char	zc_data;	/* data */
     57 };
     58 
     59 struct zsdevice {
     60 	struct	zschan zs_chan[2];
     61 };
     62 
     63 /*
     64  * Software state, per zs channel.
     65  *
     66  * The zs chip has insufficient buffering, so we provide a software
     67  * buffer using a two-level interrupt scheme.  The hardware (high priority)
     68  * interrupt simply grabs the `cause' of the interrupt and stuffs it into
     69  * a ring buffer.  It then schedules a software interrupt; the latter
     70  * empties the ring as fast as it can, hoping to avoid overflow.
     71  *
     72  * Interrupts can happen because of:
     73  *	- received data;
     74  *	- transmit pseudo-DMA done; and
     75  *	- status change.
     76  * These are all stored together in the (single) ring.  The size of the
     77  * ring is a power of two, to make % operations fast.  Since we need two
     78  * bits to distinguish the interrupt type, and up to 16 for the received
     79  * data plus RR1 status, we use 32 bits per ring entry.
     80  *
     81  * When the value is a character + RR1 status, the character is in the
     82  * upper 8 bits of the RR1 status.
     83  */
     84 #define ZLRB_RING_SIZE		4096		/* ZS line ring buffer size */
     85 #define	ZLRB_RING_MASK		4095		/* mask for same */
     86 
     87 /* 0 is reserved (means "no interrupt") */
     88 #define	ZRING_RINT		1		/* receive data interrupt */
     89 #define	ZRING_XINT		2		/* transmit done interrupt */
     90 #define	ZRING_SINT		3		/* status change interrupt */
     91 
     92 #define	ZRING_TYPE(x)		((x) & 3)
     93 #define	ZRING_VALUE(x)		((x) >> 8)
     94 #define	ZRING_MAKE(t, v)	((t) | (v) << 8)
     95 
     96 struct zs_chanstate {
     97 	struct	zs_chanstate	*cs_next;	/* linked list for zshard() */
     98 	volatile struct zschan	*cs_zc;		/* points to hardware regs */
     99 	int			cs_unit;	/* unit number */
    100 	struct	tty		*cs_ttyp;	/* ### */
    101 
    102 	/*
    103 	 * We must keep a copy of the write registers as they are
    104 	 * mostly write-only and we sometimes need to set and clear
    105 	 * individual bits (e.g., in WR3).  Not all of these are
    106 	 * needed but 16 bytes is cheap and this makes the addressing
    107 	 * simpler.  Unfortunately, we can only write to some registers
    108 	 * when the chip is not actually transmitting, so whenever
    109 	 * we are expecting a `transmit done' interrupt the preg array
    110 	 * is allowed to `get ahead' of the current values.  In a
    111 	 * few places we must change the current value of a register,
    112 	 * rather than (or in addition to) the pending value; for these
    113 	 * cs_creg[] contains the current value.
    114 	 */
    115 	u_char	cs_creg[16];		/* current values */
    116 	u_char	cs_preg[16];		/* pending values */
    117 	u_char	cs_heldchange;		/* change pending (creg != preg) */
    118 	u_char	cs_rr0;			/* last rr0 processed */
    119 
    120 	/* pure software data, per channel */
    121 	char	cs_softcar;		/* software carrier */
    122 	char	cs_xxx;			/* (spare) */
    123 
    124 	/*
    125 	 * The transmit byte count and address are used for pseudo-DMA
    126 	 * output in the hardware interrupt code.  PDMA can be suspended
    127 	 * to get pending changes done; heldtbc is used for this.  It can
    128 	 * also be stopped for ^S; this sets TS_TTSTOP in tp->t_state.
    129 	 */
    130 	int	cs_tbc;			/* transmit byte count */
    131 	caddr_t	cs_tba;			/* transmit buffer address */
    132 	int	cs_heldtbc;		/* held tbc while xmission stopped */
    133 
    134 	/*
    135 	 * Printing an overrun error message often takes long enough to
    136 	 * cause another overrun, so we only print one per second.
    137 	 */
    138 	long	cs_rotime;		/* time of last ring overrun */
    139 	long	cs_fotime;		/* time of last fifo overrun */
    140 
    141 	/*
    142 	 * The ring buffer.
    143 	 */
    144 	u_int		cs_rbget;	/* ring buffer `get' index	*/
    145 	volatile u_int	cs_rbput;	/* ring buffer `put' index	*/
    146 	int		*cs_rbuf;	/* type, value pairs	*/
    147 };
    148 
    149 #define	ZS_CHAN_A	0
    150 #define	ZS_CHAN_B	1
    151 
    152 /*
    153  * Macros to read and write individual registers (except 0) in a channel.
    154  */
    155 #define	ZS_READ(c, r)		((c)->zc_csr = (r), (c)->zc_csr)
    156 #define	ZS_WRITE(c, r, v)	((c)->zc_csr = (r), (c)->zc_csr = (v))
    157 
    158 /*
    159  * Split minor into unit & flag nibble.
    160  */
    161 #define	ZS_UNIT(dev)		((minor(dev) >> 4) & 0xf)
    162 #define	ZS_FLAGS(dev)		(minor(dev) & 0xf)
    163