bus_defs.h revision 1.1.54.1
1 /* $NetBSD: bus_defs.h,v 1.1.54.1 2020/04/13 08:03:39 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1996 Carnegie-Mellon University. 35 * All rights reserved. 36 * 37 * Author: Chris G. Demetriou 38 * 39 * Permission to use, copy, modify and distribute this software and 40 * its documentation is hereby granted, provided that both the copyright 41 * notice and this permission notice appear in all copies of the 42 * software, derivative works or modified versions, and any portions 43 * thereof, and that both notices appear in supporting documentation. 44 * 45 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 46 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 47 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 48 * 49 * Carnegie Mellon requests users of this software to return to 50 * 51 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 52 * School of Computer Science 53 * Carnegie Mellon University 54 * Pittsburgh PA 15213-3890 55 * 56 * any improvements or extensions that they make and grant Carnegie the 57 * rights to redistribute these changes. 58 */ 59 60 #ifndef _ATARI_BUS_DEFS_H_ 61 #define _ATARI_BUS_DEFS_H_ 62 63 /* 64 * Memory addresses (in bus space) 65 */ 66 typedef u_long bus_addr_t; 67 typedef u_long bus_size_t; 68 69 #define PRIxBUSADDR "lx" 70 #define PRIxBUSSIZE "lx" 71 #define PRIuBUSSIZE "lu" 72 73 /* 74 * I/O addresses (in bus space) 75 */ 76 typedef u_long bus_io_addr_t; 77 typedef u_long bus_io_size_t; 78 79 #define __BUS_SPACE_HAS_STREAM_METHODS 80 81 /* 82 * Access methods for bus resources and address space. 83 */ 84 typedef struct atari_bus_space *bus_space_tag_t; 85 typedef u_long bus_space_handle_t; 86 87 #define PRIxBSH "lx" 88 89 #define BUS_SPACE_MAP_CACHEABLE 0x01 90 #define BUS_SPACE_MAP_LINEAR 0x02 91 #define BUS_SPACE_MAP_PREFETCHABLE 0x04 92 93 /* 94 * Structure containing functions and other feature-data that might differ 95 * between the various bus spaces on the atari. Currently 'known' bus 96 * spaces are: ISA, PCI, VME and 'mainbus'. 97 */ 98 struct atari_bus_space { 99 u_long base; 100 101 /* XXX Next 2 lines can be turned into an opaque cookie */ 102 int stride; 103 int wo_1, wo_2, wo_4, wo_8; 104 105 /* Autoconf detection stuff */ 106 int (*abs_p_1)(bus_space_tag_t, bus_space_handle_t, 107 bus_size_t); 108 int (*abs_p_2)(bus_space_tag_t, bus_space_handle_t, 109 bus_size_t); 110 int (*abs_p_4)(bus_space_tag_t, bus_space_handle_t, 111 bus_size_t); 112 int (*abs_p_8)(bus_space_tag_t, bus_space_handle_t, 113 bus_size_t); 114 115 /* read (single) */ 116 uint8_t (*abs_r_1)(bus_space_tag_t, bus_space_handle_t, 117 bus_size_t); 118 uint16_t (*abs_r_2)(bus_space_tag_t, bus_space_handle_t, 119 bus_size_t); 120 uint32_t (*abs_r_4)(bus_space_tag_t, bus_space_handle_t, 121 bus_size_t); 122 uint64_t (*abs_r_8)(bus_space_tag_t, bus_space_handle_t, 123 bus_size_t); 124 125 /* read (single) stream */ 126 uint8_t (*abs_rs_1)(bus_space_tag_t, bus_space_handle_t, 127 bus_size_t); 128 uint16_t (*abs_rs_2)(bus_space_tag_t, bus_space_handle_t, 129 bus_size_t); 130 uint32_t (*abs_rs_4)(bus_space_tag_t, bus_space_handle_t, 131 bus_size_t); 132 uint64_t (*abs_rs_8)(bus_space_tag_t, bus_space_handle_t, 133 bus_size_t); 134 135 /* read multiple */ 136 void (*abs_rm_1)(bus_space_tag_t, bus_space_handle_t, 137 bus_size_t, uint8_t *, bus_size_t); 138 void (*abs_rm_2)(bus_space_tag_t, bus_space_handle_t, 139 bus_size_t, uint16_t *, bus_size_t); 140 void (*abs_rm_4)(bus_space_tag_t, bus_space_handle_t, 141 bus_size_t, uint32_t *, bus_size_t); 142 void (*abs_rm_8)(bus_space_tag_t, bus_space_handle_t, 143 bus_size_t, uint64_t *, bus_size_t); 144 145 /* read multiple stream */ 146 void (*abs_rms_1)(bus_space_tag_t, bus_space_handle_t, 147 bus_size_t, uint8_t *, bus_size_t); 148 void (*abs_rms_2)(bus_space_tag_t, bus_space_handle_t, 149 bus_size_t, uint16_t *, bus_size_t); 150 void (*abs_rms_4)(bus_space_tag_t, bus_space_handle_t, 151 bus_size_t, uint32_t *, bus_size_t); 152 void (*abs_rms_8)(bus_space_tag_t, bus_space_handle_t, 153 bus_size_t, uint64_t *, bus_size_t); 154 155 /* read region */ 156 void (*abs_rr_1)(bus_space_tag_t, bus_space_handle_t, 157 bus_size_t, uint8_t *, bus_size_t); 158 void (*abs_rr_2)(bus_space_tag_t, bus_space_handle_t, 159 bus_size_t, uint16_t *, bus_size_t); 160 void (*abs_rr_4)(bus_space_tag_t, bus_space_handle_t, 161 bus_size_t, uint32_t *, bus_size_t); 162 void (*abs_rr_8)(bus_space_tag_t, bus_space_handle_t, 163 bus_size_t, uint64_t *, bus_size_t); 164 165 /* read region stream */ 166 void (*abs_rrs_1)(bus_space_tag_t, bus_space_handle_t, 167 bus_size_t, uint8_t *, bus_size_t); 168 void (*abs_rrs_2)(bus_space_tag_t, bus_space_handle_t, 169 bus_size_t, uint16_t *, bus_size_t); 170 void (*abs_rrs_4)(bus_space_tag_t, bus_space_handle_t, 171 bus_size_t, uint32_t *, bus_size_t); 172 void (*abs_rrs_8)(bus_space_tag_t, bus_space_handle_t, 173 bus_size_t, uint64_t *, bus_size_t); 174 175 /* write (single) */ 176 void (*abs_w_1)(bus_space_tag_t, bus_space_handle_t, 177 bus_size_t, uint8_t); 178 void (*abs_w_2)(bus_space_tag_t, bus_space_handle_t, 179 bus_size_t, uint16_t); 180 void (*abs_w_4)(bus_space_tag_t, bus_space_handle_t, 181 bus_size_t, uint32_t); 182 void (*abs_w_8)(bus_space_tag_t, bus_space_handle_t, 183 bus_size_t, uint64_t); 184 185 /* write (single) stream */ 186 void (*abs_ws_1)(bus_space_tag_t, bus_space_handle_t, 187 bus_size_t, uint8_t); 188 void (*abs_ws_2)(bus_space_tag_t, bus_space_handle_t, 189 bus_size_t, uint16_t); 190 void (*abs_ws_4)(bus_space_tag_t, bus_space_handle_t, 191 bus_size_t, uint32_t); 192 void (*abs_ws_8)(bus_space_tag_t, bus_space_handle_t, 193 bus_size_t, uint64_t); 194 195 /* write multiple */ 196 void (*abs_wm_1)(bus_space_tag_t, bus_space_handle_t, 197 bus_size_t, const uint8_t *, bus_size_t); 198 void (*abs_wm_2)(bus_space_tag_t, bus_space_handle_t, 199 bus_size_t, const uint16_t *, bus_size_t); 200 void (*abs_wm_4)(bus_space_tag_t, bus_space_handle_t, 201 bus_size_t, const uint32_t *, bus_size_t); 202 void (*abs_wm_8)(bus_space_tag_t, bus_space_handle_t, 203 bus_size_t, const uint64_t *, bus_size_t); 204 205 /* write multiple stream */ 206 void (*abs_wms_1)(bus_space_tag_t, bus_space_handle_t, 207 bus_size_t, const uint8_t *, bus_size_t); 208 void (*abs_wms_2)(bus_space_tag_t, bus_space_handle_t, 209 bus_size_t, const uint16_t *, bus_size_t); 210 void (*abs_wms_4)(bus_space_tag_t, bus_space_handle_t, 211 bus_size_t, const uint32_t *, bus_size_t); 212 void (*abs_wms_8)(bus_space_tag_t, bus_space_handle_t, 213 bus_size_t, const uint64_t *, bus_size_t); 214 215 /* write region */ 216 void (*abs_wr_1)(bus_space_tag_t, bus_space_handle_t, 217 bus_size_t, const uint8_t *, bus_size_t); 218 void (*abs_wr_2)(bus_space_tag_t, bus_space_handle_t, 219 bus_size_t, const uint16_t *, bus_size_t); 220 void (*abs_wr_4)(bus_space_tag_t, bus_space_handle_t, 221 bus_size_t, const uint32_t *, bus_size_t); 222 void (*abs_wr_8)(bus_space_tag_t, bus_space_handle_t, 223 bus_size_t, const uint64_t *, bus_size_t); 224 225 /* write region stream */ 226 void (*abs_wrs_1)(bus_space_tag_t, bus_space_handle_t, 227 bus_size_t, const uint8_t *, bus_size_t); 228 void (*abs_wrs_2)(bus_space_tag_t, bus_space_handle_t, 229 bus_size_t, const uint16_t *, bus_size_t); 230 void (*abs_wrs_4)(bus_space_tag_t, bus_space_handle_t, 231 bus_size_t, const uint32_t *, bus_size_t); 232 void (*abs_wrs_8)(bus_space_tag_t, bus_space_handle_t, 233 bus_size_t, const uint64_t *, bus_size_t); 234 235 /* set multiple */ 236 void (*abs_sm_1)(bus_space_tag_t, bus_space_handle_t, 237 bus_size_t, uint8_t, bus_size_t); 238 void (*abs_sm_2)(bus_space_tag_t, bus_space_handle_t, 239 bus_size_t, uint16_t, bus_size_t); 240 void (*abs_sm_4)(bus_space_tag_t, bus_space_handle_t, 241 bus_size_t, uint32_t, bus_size_t); 242 void (*abs_sm_8)(bus_space_tag_t, bus_space_handle_t, 243 bus_size_t, uint64_t, bus_size_t); 244 245 /* set region */ 246 void (*abs_sr_1)(bus_space_tag_t, bus_space_handle_t, 247 bus_size_t, uint8_t, bus_size_t); 248 void (*abs_sr_2)(bus_space_tag_t, bus_space_handle_t, 249 bus_size_t, uint16_t, bus_size_t); 250 void (*abs_sr_4)(bus_space_tag_t, bus_space_handle_t, 251 bus_size_t, uint32_t, bus_size_t); 252 void (*abs_sr_8)(bus_space_tag_t, bus_space_handle_t, 253 bus_size_t, uint64_t, bus_size_t); 254 255 #if 0 /* See comment on __abs_copy below */ 256 /* copy */ 257 void (*abs_c_1)(bus_space_tag_t, bus_space_handle_t, 258 bus_size_t, bus_space_handle_t, bus_size_t, 259 bus_size_t); 260 void (*abs_c_2)(bus_space_tag_t, bus_space_handle_t, 261 bus_size_t, bus_space_handle_t, bus_size_t, 262 bus_size_t); 263 void (*abs_c_4)(bus_space_tag_t, bus_space_handle_t, 264 bus_size_t, bus_space_handle_t, bus_size_t, 265 bus_size_t); 266 void (*abs_c_8)(bus_space_tag_t, bus_space_handle_t, 267 bus_size_t, bus_space_handle_t, bus_size_t, 268 bus_size_t); 269 #endif 270 }; 271 272 #define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t) 273 274 #define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */ 275 #define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */ 276 277 /* 278 * Flags used in various bus DMA methods. 279 */ 280 #define BUS_DMA_WAITOK 0x000 /* safe to sleep (pseudo-flag) */ 281 #define BUS_DMA_NOWAIT 0x001 /* not safe to sleep */ 282 #define BUS_DMA_ALLOCNOW 0x002 /* perform resource allocation now */ 283 #define BUS_DMA_COHERENT 0x004 /* hint: map memory DMA coherent */ 284 #define BUS_DMA_STREAMING 0x008 /* hint: sequential, unidirectional */ 285 #define BUS_DMA_BUS1 0x010 /* placeholders for bus functions... */ 286 #define BUS_DMA_BUS2 0x020 287 #define BUS_DMA_BUS3 0x040 288 #define BUS_DMA_BUS4 0x080 289 #define BUS_DMA_READ 0x100 /* mapping is device -> memory only */ 290 #define BUS_DMA_WRITE 0x200 /* mapping is memory -> device only */ 291 #define BUS_DMA_NOCACHE 0x400 /* hint: map non-cached memory */ 292 293 /* Forwards needed by prototypes below. */ 294 struct mbuf; 295 struct uio; 296 297 /* 298 * Operations performed by bus_dmamap_sync(). 299 */ 300 #define BUS_DMASYNC_PREREAD 0x01 /* pre-read synchronization */ 301 #define BUS_DMASYNC_POSTREAD 0x02 /* post-read synchronization */ 302 #define BUS_DMASYNC_PREWRITE 0x04 /* pre-write synchronization */ 303 #define BUS_DMASYNC_POSTWRITE 0x08 /* post-write synchronization */ 304 305 typedef struct atari_bus_dma_tag *bus_dma_tag_t; 306 typedef struct atari_bus_dmamap *bus_dmamap_t; 307 308 #define BUS_DMA_TAG_VALID(t) ((t) != (bus_dma_tag_t)0) 309 310 /* 311 * bus_dma_segment_t 312 * 313 * Describes a single contiguous DMA transaction. Values 314 * are suitable for programming into DMA registers. 315 */ 316 struct atari_bus_dma_segment { 317 bus_addr_t ds_addr; /* DMA address */ 318 bus_size_t ds_len; /* length of transfer */ 319 }; 320 typedef struct atari_bus_dma_segment bus_dma_segment_t; 321 322 /* 323 * bus_dma_tag_t 324 * 325 * A machine-dependent opaque type describing the implementation of 326 * DMA for a given bus. 327 */ 328 struct atari_bus_dma_tag { 329 /* 330 * The `bounce threshold' is checked while we are loading 331 * the DMA map. If the physical address of the segment 332 * exceeds the threshold, an error will be returned. The 333 * caller can then take whatever action is necessary to 334 * bounce the transfer. If this value is 0, it will be 335 * ignored. 336 */ 337 bus_addr_t _bounce_thresh; 338 339 /* 340 * The next value can be used to compensate for a constant 341 * displacement between the address space view of the CPU 342 * and the devices on the bus. 343 */ 344 int32_t _displacement; 345 346 /* 347 * DMA mapping methods. 348 */ 349 int (*_dmamap_create)(bus_dma_tag_t, bus_size_t, int, 350 bus_size_t, bus_size_t, int, bus_dmamap_t *); 351 void (*_dmamap_destroy)(bus_dma_tag_t, bus_dmamap_t); 352 int (*_dmamap_load)(bus_dma_tag_t, bus_dmamap_t, void *, 353 bus_size_t, struct proc *, int); 354 int (*_dmamap_load_mbuf)(bus_dma_tag_t, bus_dmamap_t, 355 struct mbuf *, int); 356 int (*_dmamap_load_uio)(bus_dma_tag_t, bus_dmamap_t, 357 struct uio *, int); 358 int (*_dmamap_load_raw)(bus_dma_tag_t, bus_dmamap_t, 359 bus_dma_segment_t *, int, bus_size_t, int); 360 void (*_dmamap_unload)(bus_dma_tag_t, bus_dmamap_t); 361 void (*_dmamap_sync)(bus_dma_tag_t, bus_dmamap_t, 362 bus_addr_t, bus_size_t, int); 363 }; 364 365 /* 366 * bus_dmamap_t 367 * 368 * Describes a DMA mapping. 369 */ 370 struct atari_bus_dmamap { 371 /* 372 * PRIVATE MEMBERS: not for use my machine-independent code. 373 */ 374 bus_size_t _dm_size; /* largest DMA transfer mappable */ 375 int _dm_segcnt; /* number of segs this map can map */ 376 bus_size_t _dm_maxmaxsegsz; /* fixed largest possible segment */ 377 bus_size_t _dm_boundary; /* don't cross this */ 378 bus_addr_t _dm_bounce_thresh; /* bounce threshold; see tag */ 379 int _dm_flags; /* misc. flags */ 380 381 void *_dm_cookie; /* cookie for bus-specific funcs */ 382 383 /* 384 * PUBLIC MEMBERS: these are used by machine-independent code. 385 */ 386 bus_size_t dm_maxsegsz; /* largest possible segment */ 387 bus_size_t dm_mapsize; /* size of the mapping */ 388 int dm_nsegs; /* # valid segments in mapping */ 389 bus_dma_segment_t dm_segs[1]; /* segments; variable length */ 390 }; 391 392 #endif /* _ATARI_BUS_DEFS_H_ */ 393
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