cpu.h revision 1.1
1 /* $NetBSD: cpu.h,v 1.1 1995/03/26 07:12:07 leo Exp $ */ 2 3 /* 4 * Copyright (c) 1988 University of Utah. 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * the Systems Programming Group of the University of Utah Computer 10 * Science Department. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the University of 23 * California, Berkeley and its contributors. 24 * 4. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * from: Utah $Hdr: cpu.h 1.16 91/03/25$ 41 * 42 * @(#)cpu.h 7.7 (Berkeley) 6/27/91 43 */ 44 45 #ifndef _MACHINE_CPU_H_ 46 #define _MACHINE_CPU_H_ 47 48 /* 49 * Exported definitions unique to atari/68k cpu support. 50 */ 51 52 /* 53 * definitions of cpu-dependent requirements 54 * referenced in generic code 55 */ 56 #define COPY_SIGCODE /* copy sigcode above user stack in exec */ 57 58 #define cpu_exec(p) /* nothing */ 59 #define cpu_swapin(p) /* nothing */ 60 #define cpu_wait(p) /* nothing */ 61 #define cpu_setstack(p, ap) (p)->p_md.md_regs[SP] = ap 62 #define cpu_set_init_frame(p, fp) (p)->p_md.md_regs = fp 63 64 /* 65 * Arguments to hardclock and gatherstats encapsulate the previous 66 * machine state in an opaque clockframe. On the hp300, we use 67 * what the hardware pushes on an interrupt (frame format 0). 68 */ 69 struct clockframe { 70 u_short sr; /* sr at time of interrupt */ 71 u_long pc; /* pc at time of interrupt */ 72 u_short vo; /* vector offset (4-word frame) */ 73 }; 74 75 #define CLKF_USERMODE(framep) (((framep)->sr & PSL_S) == 0) 76 #define CLKF_BASEPRI(framep) (((framep)->sr & PSL_IPL) == 0) 77 #define CLKF_PC(framep) ((framep)->pc) 78 #if 0 79 /* We would like to do it this way... */ 80 #define CLKF_INTR(framep) (((framep)->sr & PSL_M) == 0) 81 #else 82 /* but until we start using PSL_M, we have to do this instead */ 83 #define CLKF_INTR(framep) (0) /* XXX */ 84 #endif 85 86 87 /* 88 * Preempt the current process if in interrupt from user mode, 89 * or after the current trap/syscall if in system mode. 90 */ 91 #define need_resched() {want_resched = 1; setsoftast();} 92 93 /* 94 * Give a profiling tick to the current process from the softclock 95 * interrupt. On hp300, request an ast to send us through trap(), 96 * marking the proc as needing a profiling tick. 97 */ 98 #define profile_tick(p, framep) ((p)->p_flag |= P_OWEUPC, setsoftast()) 99 #define need_proftick(p) ((p)->p_flag |= P_OWEUPC, setsoftast()) 100 101 /* 102 * Notify the current process (p) that it has a signal pending, 103 * process as soon as possible. 104 */ 105 #define signotify(p) setsoftast() 106 107 #define setsoftast() (astpending = 1) 108 109 extern int astpending; /* need trap before returning to user mode */ 110 extern int want_resched; /* resched() was called */ 111 112 /* 113 * simulated software interrupt register 114 */ 115 extern unsigned char ssir; 116 117 #define SIR_NET 0x1 118 #define SIR_CLOCK 0x2 119 120 #define siroff(x) ssir &= ~(x) 121 #define setsoftnet() ssir |= SIR_NET 122 #define setsoftclock() ssir |= SIR_CLOCK 123 124 125 /* 126 * The rest of this should probably be moved to ../atari/ataricpu.h, 127 * although some of it could probably be put into generic 68k headers. 128 */ 129 #define BASEPRI(sr) ((sr & PSL_IPL) == 0) 130 131 /* 132 * Values for machineid. 133 */ 134 #define ATARI_68020 (1L<<2) 135 #define ATARI_68030 (1L<<3) 136 #define ATARI_68040 (1L<<4) 137 #define ATARI_68881 (1L<<8) 138 #define ATARI_68882 (1L<<9) 139 #define ATARI_FPU40 (1L<<10) 140 141 142 /* 143 * Values for mmutype (assigned for quick testing) 144 */ 145 #define MMU_68030 -1 /* 68030 on-chip subset of 68851 */ 146 #define MMU_68851 1 /* Motorola 68851 */ 147 #define MMU_68040 -2 /* 68040 on-chip subsubset */ 148 149 /* values for cpuspeed (not really related to clock speed due to caches) */ 150 #define MHZ_8 1 151 #define MHZ_16 2 152 #define MHZ_25 3 153 #define MHZ_33 4 154 #define MHZ_50 6 155 156 #ifdef KERNEL 157 extern int machineid, mmutype, cpu040; 158 #endif 159 160 /* 161 * 68851 and 68030 MMU 162 */ 163 #define PMMU_LVLMASK 0x0007 164 #define PMMU_INV 0x0400 165 #define PMMU_WP 0x0800 166 #define PMMU_ALV 0x1000 167 #define PMMU_SO 0x2000 168 #define PMMU_LV 0x4000 169 #define PMMU_BE 0x8000 170 #define PMMU_FAULT (PMMU_WP|PMMU_INV) 171 172 /* 680X0 function codes */ 173 #define FC_USERD 1 /* user data space */ 174 #define FC_USERP 2 /* user program space */ 175 #define FC_SUPERD 5 /* supervisor data space */ 176 #define FC_SUPERP 6 /* supervisor program space */ 177 #define FC_CPU 7 /* CPU space */ 178 179 /* fields in the 68020 cache control register */ 180 #define IC_ENABLE 0x0001 /* enable instruction cache */ 181 #define IC_FREEZE 0x0002 /* freeze instruction cache */ 182 #define IC_CE 0x0004 /* clear instruction cache entry */ 183 #define IC_CLR 0x0008 /* clear entire instruction cache */ 184 185 /* additional fields in the 68030 cache control register */ 186 #define IC_BE 0x0010 /* instruction burst enable */ 187 #define DC_ENABLE 0x0100 /* data cache enable */ 188 #define DC_FREEZE 0x0200 /* data cache freeze */ 189 #define DC_CE 0x0400 /* clear data cache entry */ 190 #define DC_CLR 0x0800 /* clear entire data cache */ 191 #define DC_BE 0x1000 /* data burst enable */ 192 #define DC_WA 0x2000 /* write allocate */ 193 194 /* fields in the 68040 cache control register */ 195 #define IC40_ENABLE 0x00008000 /* enable instruction cache */ 196 #define DC40_ENABLE 0x80000000 /* enable data cache */ 197 198 #define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 199 #define CACHE_OFF (DC_CLR|IC_CLR) 200 #define CACHE_CLR (CACHE_ON) 201 #define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 202 #define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE) 203 204 /* 68040 cache control */ 205 #define CACHE40_ON (IC40_ENABLE|DC40_ENABLE) 206 #define CACHE40_OFF 0x00000000 207 208 /* 209 * CTL_MACHDEP definitions. 210 */ 211 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 212 #define CPU_MAXID 2 /* number of valid machdep ids */ 213 214 #define CTL_MACHDEP_NAMES { \ 215 { 0, 0 }, \ 216 { "console_device", CTLTYPE_STRUCT }, \ 217 } 218 219 #endif /* !_MACHINE_CPU_H_ */ 220
Indexes created Tue Sep 23 07:09:52 GMT 2025