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cpu.h revision 1.11 
      1 /*	$NetBSD: cpu.h,v 1.11 1996/04/18 08:52:17 leo Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1988 University of Utah.
      5  * Copyright (c) 1982, 1990 The Regents of the University of California.
      6  * All rights reserved.
      7  *
      8  * This code is derived from software contributed to Berkeley by
      9  * the Systems Programming Group of the University of Utah Computer
     10  * Science Department.
     11  *
     12  * Redistribution and use in source and binary forms, with or without
     13  * modification, are permitted provided that the following conditions
     14  * are met:
     15  * 1. Redistributions of source code must retain the above copyright
     16  *    notice, this list of conditions and the following disclaimer.
     17  * 2. Redistributions in binary form must reproduce the above copyright
     18  *    notice, this list of conditions and the following disclaimer in the
     19  *    documentation and/or other materials provided with the distribution.
     20  * 3. All advertising materials mentioning features or use of this software
     21  *    must display the following acknowledgement:
     22  *	This product includes software developed by the University of
     23  *	California, Berkeley and its contributors.
     24  * 4. Neither the name of the University nor the names of its contributors
     25  *    may be used to endorse or promote products derived from this software
     26  *    without specific prior written permission.
     27  *
     28  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     29  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     30  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     31  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     32  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     33  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     34  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     35  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     36  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     37  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     38  * SUCH DAMAGE.
     39  *
     40  * from: Utah $Hdr: cpu.h 1.16 91/03/25$
     41  *
     42  *	@(#)cpu.h	7.7 (Berkeley) 6/27/91
     43  */
     44 
     45 #ifndef _MACHINE_CPU_H_
     46 #define _MACHINE_CPU_H_
     47 
     48 /*
     49  * Exported definitions unique to atari/68k cpu support.
     50  */
     51 
     52 /*
     53  * definitions of cpu-dependent requirements
     54  * referenced in generic code
     55  */
     56 #define	cpu_swapin(p)			/* nothing */
     57 #define	cpu_wait(p)			/* nothing */
     58 #define cpu_swapout(p)			/* nothing */
     59 
     60 /*
     61  * Arguments to hardclock and gatherstats encapsulate the previous
     62  * machine state in an opaque clockframe.  On the hp300, we use
     63  * what the hardware pushes on an interrupt (frame format 0).
     64  */
     65 struct clockframe {
     66 	u_short	sr;		/* sr at time of interrupt */
     67 	u_long	pc;		/* pc at time of interrupt */
     68 	u_short	vo;		/* vector offset (4-word frame) */
     69 };
     70 
     71 #define	CLKF_USERMODE(framep)	(((framep)->sr & PSL_S) == 0)
     72 #define	CLKF_BASEPRI(framep)	(((framep)->sr & PSL_IPL) == 0)
     73 #define	CLKF_PC(framep)		((framep)->pc)
     74 #if 0
     75 /* We would like to do it this way... */
     76 #define	CLKF_INTR(framep)	(((framep)->sr & PSL_M) == 0)
     77 #else
     78 /* but until we start using PSL_M, we have to do this instead */
     79 #define	CLKF_INTR(framep)	(0)	/* XXX */
     80 #endif
     81 
     82 
     83 /*
     84  * Preempt the current process if in interrupt from user mode,
     85  * or after the current trap/syscall if in system mode.
     86  */
     87 #define	need_resched()	{want_resched = 1; setsoftast();}
     88 
     89 /*
     90  * Give a profiling tick to the current process from the softclock
     91  * interrupt.  On hp300, request an ast to send us through trap(),
     92  * marking the proc as needing a profiling tick.
     93  */
     94 #define	profile_tick(p, framep)	((p)->p_flag |= P_OWEUPC, setsoftast())
     95 #define	need_proftick(p)	((p)->p_flag |= P_OWEUPC, setsoftast())
     96 
     97 /*
     98  * Notify the current process (p) that it has a signal pending,
     99  * process as soon as possible.
    100  */
    101 #define	signotify(p)	setsoftast()
    102 
    103 #define setsoftast()	(astpending = 1)
    104 
    105 extern int	astpending;	/* need trap before returning to user mode */
    106 extern int	want_resched;	/* resched() was called */
    107 
    108 /* include support for software interrupts */
    109 #include <machine/mtpr.h>
    110 
    111 /*
    112  * The rest of this should probably be moved to ../atari/ataricpu.h,
    113  * although some of it could probably be put into generic 68k headers.
    114  */
    115 #define	BASEPRI(sr)	((sr & PSL_IPL) == 0)
    116 
    117 /*
    118  * Values for machineid.
    119  */
    120 #define	ATARI_68000	1		/* 68000 CPU			*/
    121 #define	ATARI_68010	(1<<1)		/* 68010 CPU			*/
    122 #define ATARI_68020	(1L<<2)		/* 68020 CPU			*/
    123 #define ATARI_68030	(1L<<3)		/* 68030 CPU			*/
    124 #define ATARI_68040	(1L<<4)		/* 68040 CPU			*/
    125 #define	ATARI_TT	(1L<<11)
    126 #define	ATARI_FALCON	(1L<<12)
    127 
    128 #define	ATARI_CLKBROKEN	(1L<<16)
    129 
    130 #define	ATARI_ANYCPU	(ATARI_68000|ATARI_68010|ATARI_68020|ATARI_68030 \
    131 			|ATARI_68040)
    132 
    133 /*
    134  * Values for mmutype (assigned for quick testing)
    135  */
    136 #define	MMU_68030	-1	/* 68030 on-chip subset of 68851	*/
    137 #define	MMU_68851	 1	/* Motorola 68851			*/
    138 #define MMU_68040	-2	/* 68040 on-chip subsubset		*/
    139 
    140 #ifdef _KERNEL
    141 extern int machineid, mmutype, cpu040, fputype;
    142 #endif
    143 
    144 /*
    145  * 68851 and 68030 MMU
    146  */
    147 #define	PMMU_LVLMASK	0x0007
    148 #define	PMMU_INV	0x0400
    149 #define	PMMU_WP		0x0800
    150 #define	PMMU_ALV	0x1000
    151 #define	PMMU_SO		0x2000
    152 #define	PMMU_LV		0x4000
    153 #define	PMMU_BE		0x8000
    154 #define	PMMU_FAULT	(PMMU_WP|PMMU_INV)
    155 
    156 /* 680X0 function codes */
    157 #define	FC_USERD	1	/* user data space */
    158 #define	FC_USERP	2	/* user program space */
    159 #define	FC_SUPERD	5	/* supervisor data space */
    160 #define	FC_SUPERP	6	/* supervisor program space */
    161 #define	FC_CPU		7	/* CPU space */
    162 
    163 /* fields in the 68020 cache control register */
    164 #define	IC_ENABLE	0x0001	/* enable instruction cache */
    165 #define	IC_FREEZE	0x0002	/* freeze instruction cache */
    166 #define	IC_CE		0x0004	/* clear instruction cache entry */
    167 #define	IC_CLR		0x0008	/* clear entire instruction cache */
    168 
    169 /* additional fields in the 68030 cache control register */
    170 #define	IC_BE		0x0010	/* instruction burst enable */
    171 #define	DC_ENABLE	0x0100	/* data cache enable */
    172 #define	DC_FREEZE	0x0200	/* data cache freeze */
    173 #define	DC_CE		0x0400	/* clear data cache entry */
    174 #define	DC_CLR		0x0800	/* clear entire data cache */
    175 #define	DC_BE		0x1000	/* data burst enable */
    176 #define	DC_WA		0x2000	/* write allocate */
    177 
    178 /* fields in the 68040 cache control register */
    179 #define	IC40_ENABLE	0x00008000	/* enable instruction cache */
    180 #define DC40_ENABLE	0x80000000	/* enable data cache */
    181 
    182 #define	CACHE_ON	(DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
    183 #define	CACHE_OFF	(DC_CLR|IC_CLR)
    184 #define	CACHE_CLR	(CACHE_ON)
    185 #define	IC_CLEAR	(DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
    186 #define	DC_CLEAR	(DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE)
    187 
    188 /* 68040 cache control */
    189 #define	CACHE40_ON	(IC40_ENABLE|DC40_ENABLE)
    190 #define	CACHE40_OFF	0x00000000
    191 
    192 /*
    193  * CTL_MACHDEP definitions.
    194  */
    195 #define CPU_CONSDEV	1	/* dev_t: console terminal device */
    196 #define CPU_MAXID	2	/* number of valid machdep ids */
    197 
    198 #define CTL_MACHDEP_NAMES { \
    199 	{ 0, 0 }, \
    200 	{ "console_device", CTLTYPE_STRUCT }, \
    201 }
    202 
    203 #ifdef _KERNEL
    204 /*
    205  * Prototypes from atari_init.c
    206  */
    207 int	cpu_dump __P((int (*)(dev_t, daddr_t, caddr_t, size_t), daddr_t *));
    208 int	cpu_dumpsize __P((void));
    209 
    210 /*
    211  * Prototypes from autoconf.c
    212  */
    213 void	configure __P((void));
    214 void	config_console __P((void));
    215 
    216 /*
    217  * Prototypes from clock.c
    218  */
    219 long	clkread __P((void));
    220 
    221 /*
    222  * Prototypes from disksubr.c
    223  */
    224 struct buf;
    225 struct disklabel;
    226 int	bounds_check_with_label __P((struct buf *, struct disklabel *, int));
    227 
    228 /*
    229  * Prototypes from fpu.c
    230  */
    231 char	*fpu_describe __P((int));
    232 int	fpu_probe __P((void));
    233 
    234 
    235 /*
    236  * Prototypes from grfabs.c
    237  */
    238 int	grfabs_probe __P((void));
    239 
    240 
    241 /*
    242  * Prototypes from vm_machdep.c
    243  */
    244 int		badbaddr __P((caddr_t));
    245 void		consinit __P((void));
    246 void		cpu_set_kpc __P((struct proc *, void (*)(struct proc *)));
    247 void		dumpconf __P((void));
    248 vm_offset_t	kvtop __P((caddr_t));
    249 void		physaccess __P((caddr_t, caddr_t, int, int));
    250 void		physunaccess __P((caddr_t, int));
    251 void		setredzone __P((u_int *, caddr_t));
    252 
    253 /*
    254  * Prototypes from locore.s
    255  */
    256 struct fpframe;
    257 struct user;
    258 struct pcb;
    259 
    260 void	clearseg __P((vm_offset_t));
    261 void	doboot __P((void));
    262 u_long	getdfc __P((void));
    263 u_long	getsfc __P((void));
    264 void	loadustp __P((int));
    265 void	m68881_save __P((struct fpframe *));
    266 void	m68881_restore __P((struct fpframe *));
    267 void	physcopyseg __P((vm_offset_t, vm_offset_t));
    268 u_int	probeva __P((u_int, u_int));
    269 void	proc_trampoline __P((void));
    270 void	savectx __P((struct pcb *));
    271 void	switch_exit __P((struct proc *));
    272 void	DCIS __P((void));
    273 void	DCIU __P((void));
    274 void	ICIA __P((void));
    275 void	ICPA __P((void));
    276 void	PCIA __P((void));
    277 void	TBIA __P((void));
    278 void	TBIS __P((vm_offset_t));
    279 void	TBIAS __P((void));
    280 void	TBIAU __P((void));
    281 
    282 /*
    283  * Prototypes from machdep.c:
    284  */
    285 typedef void (*si_farg)(void *, void *);	/* XXX */
    286 void	add_sicallback __P((si_farg, void *, void *));
    287 void	rem_sicallback __P((si_farg));
    288 struct frame;
    289 void	regdump __P((struct frame *, int));
    290 void	boot __P((int));
    291 void	cpu_startup __P((void));
    292 void	dumpsys __P((void));
    293 vm_offset_t reserve_dumppages __P((vm_offset_t));
    294 void	softint __P((void));
    295 
    296 
    297 /*
    298  * Prototypes from nvram.c:
    299  */
    300 struct uio;
    301 int	nvram_uio __P((struct uio *));
    302 
    303 /*
    304  * Prototypes from sys_machdep.c:
    305  */
    306 int	cachectl __P((int, caddr_t, int));
    307 int	dma_cachectl __P((caddr_t, int));
    308 
    309 /*
    310  * Prototypes from swapgeneric.c:
    311  */
    312 void	setconf __P((void));
    313 
    314 /*
    315  * Prototypes from trap.c:
    316  */
    317 #ifdef _MACHINE_FRAME_H_ /* XXX: We don't want to include this everywhere */
    318 void  child_return __P((struct proc *, struct frame));
    319 #endif
    320 
    321 #endif /* _KERNEL */
    322 #endif /* !_MACHINE_CPU_H_ */
    323