mfp.h revision 1.1
1 /* $NetBSD: mfp.h,v 1.1 1995/03/26 07:12:08 leo Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Leo Weppelman. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Leo Weppelman. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #ifndef _MACHINE_MFP_H 34 #define _MACHINE_MFP_H 35 /* 36 * Atari TT hardware: MFP1/MFP2 37 * Motorola 68901 Multi-Function Peripheral 38 */ 39 40 #define MFP ((struct mfp *)AD_MFP) 41 #define MFP2 ((struct mfp *)AD_MFP2) 42 43 struct mfp { 44 volatile u_char mfb[48]; /* use only the odd bytes */ 45 }; 46 47 #define mf_gpip mfb[ 1] /* general purpose I/O interrupt port */ 48 #define mf_aer mfb[ 3] /* active edge register */ 49 #define mf_ddr mfb[ 5] /* data direction register */ 50 #define mf_iera mfb[ 7] /* interrupt enable register A */ 51 #define mf_ierb mfb[ 9] /* interrupt enable register B */ 52 #define mf_ipra mfb[11] /* interrupt pending register A */ 53 #define mf_iprb mfb[13] /* interrupt pending register B */ 54 #define mf_isra mfb[15] /* interrupt in-service register A */ 55 #define mf_isrb mfb[17] /* interrupt in-service register B */ 56 #define mf_imra mfb[19] /* interrupt mask register A */ 57 #define mf_imrb mfb[21] /* interrupt mask register B */ 58 #define mf_vr mfb[23] /* vector register */ 59 #define mf_tacr mfb[25] /* timer control register A */ 60 #define mf_tbcr mfb[27] /* timer control register B */ 61 #define mf_tcdcr mfb[29] /* timer control register C+D */ 62 #define mf_tadr mfb[31] /* timer data register A */ 63 #define mf_tbdr mfb[33] /* timer data register B */ 64 #define mf_tcdr mfb[35] /* timer data register C */ 65 #define mf_tddr mfb[37] /* timer data register D */ 66 #define mf_scr mfb[39] /* synchronous character register */ 67 #define mf_ucr mfb[41] /* USART control register */ 68 #define mf_rsr mfb[43] /* receiver status register */ 69 #define mf_tsr mfb[45] /* transmitter status register */ 70 #define mf_udr mfb[47] /* USART data register */ 71 72 /* names of IO port bits: */ 73 #define IO_PBSY 0x01 /* Parallel Busy */ 74 #define IO_SDCD 0x02 /* Serial Data Carrier Detect */ 75 #define IO_SCTS 0x04 /* Serial Clear To Send */ 76 /* 0x08 *//* reserved */ 77 #define IO_AINT 0x10 /* ACIA interrupt (KB or MIDI) */ 78 #define IO_DINT 0x20 /* DMA interrupt (FDC or HDC) */ 79 #define IO_SRI 0x40 /* Serial Ring Indicator */ 80 #define IO_MONO 0x80 /* Monochrome Monitor Detect */ 81 82 /* names of interrupts in register A: MFP1 */ 83 #define IA_MONO 0x80 /* IO_MONO */ 84 #define IA_SRI 0x40 /* IO_SRI */ 85 #define IA_TIMA 0x20 /* Timer A */ 86 #define IA_RRDY 0x10 /* Serial Receiver Ready(=Full) */ 87 #define IA_RERR 0x08 /* Serial Receiver Error */ 88 #define IA_TRDY 0x04 /* Serial Transmitter Ready(=Empty) */ 89 #define IA_TERR 0x02 /* Serial Transmitter Error */ 90 #define IA_TIMB 0x01 /* Timer B */ 91 92 /* names of interrupts in register A: MFP2 */ 93 #define IA_SCSI 0x80 /* SCSI-controller */ 94 #define IA_RTC 0x40 /* Real Time Clock */ 95 #define IA_TIMA2 0x20 /* Timer A */ 96 /* 0x10 *//* reserved */ 97 /* 0x08 *//* reserved */ 98 /* 0x04 *//* reserved */ 99 /* 0x02 *//* reserved */ 100 #define IA_TIMB2 0x01 /* Timer B */ 101 102 /* names of interrupts in register B: MFP1*/ 103 #define IB_DINT 0x80 /* IO_DINT: from DMA devices */ 104 #define IB_AINT 0x40 /* IO_AINT: from kbd or midi */ 105 #define IB_TIMC 0x20 /* Timer C */ 106 #define IB_TIMD 0x10 /* Timer D */ 107 /* 0x08 *//* reserved */ 108 #define IB_SCTS 0x04 /* IO_SCTS */ 109 #define IB_SDCD 0x02 /* IO_SDCD */ 110 #define IB_PBSY 0x01 /* IO_PBSY */ 111 112 /* names of interrupts in register B: MFP2*/ 113 #define IB_SCDM 0x80 /* SCSI-dma */ 114 #define IB_DCHG 0x40 /* Diskette change */ 115 /* 0x20 *//* reserved */ 116 /* 0x10 *//* reserved */ 117 #define IB_RISB 0x80 /* Serial Ring indicator SCC port B */ 118 #define IB_DMSC 0x40 /* SCC-dma */ 119 #define IB_J602_3 0x02 /* Pin 3 J602 */ 120 #define IB_J602_1 0x01 /* Pin 1 J602 */ 121 122 /* bits in VR: */ 123 #define V_S 0x08 /* software end-of-interrupt mode */ 124 #define V_V 0xF0 /* four high bits of vector */ 125 126 /* bits in TCR: */ 127 /* 0x07 *//* divider */ 128 #define T_STOP 0x00 /* don't count */ 129 #define T_Q004 0x01 /* divide by 4 */ 130 #define T_Q010 0x02 /* divide by 10 */ 131 #define T_Q016 0x03 /* divide by 16 */ 132 #define T_Q050 0x04 /* divide by 50 */ 133 #define T_Q064 0x05 /* divide by 64 */ 134 #define T_Q100 0x06 /* divide by 100 */ 135 #define T_Q200 0x07 /* divide by 200 */ 136 #define T_EXTI 0x08 /* use extern impulse */ 137 #define T_LOWO 0x10 /* force output low */ 138 139 /* bits in UCR: */ 140 /* 0x01 *//* not used */ 141 #define U_EVEN 0x02 /* even parity */ 142 #define U_PAR 0x04 /* use parity */ 143 /* 0x18 *//* sync/async and stop bits */ 144 #define U_SYNC 0x00 /* synchrone */ 145 #define U_ST1 0x08 /* async, 1 stop bit */ 146 #define U_ST1_5 0x10 /* async, 1.5 stop bit */ 147 #define U_ST2 0x18 /* async, 2 stop bits */ 148 /* 0x60 *//* number of data bits */ 149 #define U_D8 0x00 /* 8 data bits */ 150 #define U_D7 0x20 /* 7 data bits */ 151 #define U_D6 0x40 /* 6 data bits */ 152 #define U_D5 0x60 /* 5 data bits */ 153 #define U_Q16 0x80 /* divide clock by 16 */ 154 155 /* bits in RSR: */ 156 #define RS_ENA 0x01 /* Receiver Enable */ 157 #define RS_STRIP 0x02 /* Synchronous Strip Enable */ 158 #define RS_CIP 0x04 /* Character in Progress */ 159 #define RS_BREAK 0x08 /* Break Detected */ 160 #define RS_FE 0x10 /* Frame Error */ 161 #define RS_PE 0x20 /* Parity Error */ 162 #define RS_OE 0x40 /* Overrun Error */ 163 #define RS_FULL 0x80 /* Buffer Full */ 164 165 /* bits in TSR: */ 166 #define TS_ENA 0x01 /* Transmitter Enable */ 167 /* 0x06 *//* state of dead transmitter output */ 168 #define TS_TRI 0x00 /* Quiet Output Tristate */ 169 #define TS_LOW 0x02 /* Quiet Output Low */ 170 #define TS_HIGH 0x04 /* Quiet Output High */ 171 #define TS_BACK 0x06 /* Loop Back Mode */ 172 #define TS_BREAK 0x08 /* Break Detected */ 173 #define TS_EOT 0x10 /* End of Transmission */ 174 #define TS_TURN 0x20 /* Auto Turnaround */ 175 #define TS_UE 0x40 /* Underrun Error */ 176 #define TS_EMPTY 0x80 /* Buffer Empty */ 177 #endif /* _MACHINE_MFP_H */ 178
Indexes created Tue Sep 23 07:09:52 GMT 2025