pte.h revision 1.3.40.1
1 /* $NetBSD: pte.h,v 1.3.40.1 2001/06/21 19:20:32 nathanw Exp $ */ 2 3 /* 4 * Copyright (c) 1988 University of Utah. 5 * Copyright (c) 1982, 1986, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * the Systems Programming Group of the University of Utah Computer 10 * Science Department. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the University of 23 * California, Berkeley and its contributors. 24 * 4. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * from: Utah $Hdr: pte.h 1.11 89/09/03$ 41 * 42 * @(#)pte.h 7.3 (Berkeley) 5/8/91 43 */ 44 45 #ifndef _MACHINE_PTE_H_ 46 #define _MACHINE_PTE_H_ 47 48 /* 49 * ATARI hardware segment/page table entries 50 */ 51 52 struct pte { 53 u_int pte; 54 }; 55 56 typedef u_int pt_entry_t; 57 58 struct ste { 59 u_int ste; 60 }; 61 62 typedef u_int st_entry_t; 63 64 #define PT_ENTRY_NULL ((pt_entry_t *) 0) 65 #define ST_ENTRY_NULL ((st_entry_t *) 0) 66 67 #define SG_V 0x00000002 /* segment is valid */ 68 #define SG_NV 0x00000000 69 #define SG_PROT 0x00000004 /* access protection mask */ 70 #define SG_RO 0x00000004 71 #define SG_RW 0x00000000 72 #define SG_U 0x00000008 /* modified bit (68040) */ 73 #define SG_FRAME 0xffffe000 74 #define SG_IMASK 0xff000000 75 #define SG_ISHIFT 24 76 #define SG_PMASK 0x00ffe000 77 #define SG_PSHIFT 13 78 79 /* 68040 additions */ 80 #define SG4_MASK1 0xfe000000 /* pointer table 1 index mask */ 81 #define SG4_SHIFT1 25 82 #define SG4_MASK2 0x01fc0000 /* pointer table 2 index mask */ 83 #define SG4_SHIFT2 18 84 #define SG4_MASK3 0x0003e000 /* page table index mask */ 85 #define SG4_SHIFT3 13 86 #define SG4_ADDR1 0xfffffe00 /* pointer table address mask */ 87 #define SG4_ADDR2 0xffffff80 /* page table address mask */ 88 #define SG4_LEV1SIZE 128 /* entries in pointer table 1 */ 89 #define SG4_LEV2SIZE 128 /* entries in pointer table 2 */ 90 #define SG4_LEV3SIZE 32 /* entries in page table */ 91 92 #define PG_V 0x00000001 93 #define PG_NV 0x00000000 94 #define PG_PROT 0x00000004 95 #define PG_U 0x00000008 96 #define PG_M 0x00000010 97 /* 98 * XXX The Milan uses the U0 pin to switch the pci-bridge between little & big 99 * endian mode. That's why I moved the 'wired' flag to U1 leo 10Apr/2001. 100 */ 101 #if 0 102 #define PG_W 0x00000100 103 #else 104 #define PG_W 0x00000200 105 #endif 106 #define PG_RO 0x00000004 107 #define PG_RW 0x00000000 108 #define PG_FRAME 0xffffe000 109 #define PG_CI 0x00000040 110 #define PG_SHIFT 13 111 #define PG_PFNUM(x) (((x) & PG_FRAME) >> PG_SHIFT) 112 113 /* 68040 additions */ 114 #define PG_CMASK 0x00000060 /* cache mode mask */ 115 #define PG_CWT 0x00000000 /* writethrough caching */ 116 #define PG_CCB 0x00000020 /* copyback caching */ 117 #define PG_CIS 0x00000040 /* cache inhibited serialized */ 118 #define PG_CIN 0x00000060 /* cache inhibited nonserialized */ 119 #define PG_SO 0x00000080 /* supervisor only */ 120 121 #define ATARI_STSIZE (MAXUL2SIZE*SG4_LEV2SIZE*sizeof(st_entry_t)) 122 123 /* 124 * ATARI_MAX_COREUPT maximum number of incore user page tables 125 * ATARI_USER_PTSIZE the number of bytes for user pagetables 126 * ATARI_PTBASE the VA start of the map from which upt's are allocated 127 * ATARI_PTSIZE the size of the map from which upt's are allocated 128 * ATARI_KPTSIZE size of kernel page table 129 * ATARI_MAX_KPTSIZE the most number of bytes for kpt pages 130 * ATARI_MAX_PTSIZE the number of bytes to map everything 131 */ 132 #define ATARI_MAX_COREUPT 1024 133 #define ATARI_UPTSIZE roundup(VM_MAXUSER_ADDRESS / NPTEPG, NBPG) 134 #define ATARI_UPTBASE 0x10000000 135 #define ATARI_UPTMAXSIZE \ 136 roundup((ATARI_MAX_COREUPT * ATARI_UPTSIZE), NBPG) 137 #define ATARI_MAX_KPTSIZE \ 138 (ATARI_MAX_COREUPT * ATARI_UPTSIZE / NPTEPG) 139 #define ATARI_KPTSIZE \ 140 roundup((VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS) / NPTEPG, NBPG) 141 #define ATARI_MAX_PTSIZE roundup(0xffffffff / NPTEPG, NBPG) 142 143 /* 144 * Kernel virtual address to page table entry and to physical address. 145 */ 146 #define kvtopte(va) \ 147 (&Sysmap[((unsigned)(va) - VM_MIN_KERNEL_ADDRESS) >> PGSHIFT]) 148 #define ptetokv(pt) \ 149 ((((u_int *)(pt) - Sysmap) << PGSHIFT) + VM_MIN_KERNEL_ADDRESS) 150 #define kvtophys(va) \ 151 ((kvtopte(va)->pg_pfnum << PGSHIFT) | ((int)(va) & PGOFSET)) 152 153 154 #endif /* !_MACHINE_PTE_H_ */ 155
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