isa_milan.c revision 1.4.10.3 1 1.4.10.3 nathanw /* $NetBSD: isa_milan.c,v 1.4.10.3 2002/10/18 02:35:58 nathanw Exp $ */
2 1.4.10.2 nathanw
3 1.4.10.2 nathanw /*-
4 1.4.10.2 nathanw * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 1.4.10.2 nathanw * All rights reserved.
6 1.4.10.2 nathanw *
7 1.4.10.2 nathanw * This code is derived from software contributed to The NetBSD Foundation
8 1.4.10.2 nathanw * by Leo Weppelman.
9 1.4.10.2 nathanw *
10 1.4.10.2 nathanw * Redistribution and use in source and binary forms, with or without
11 1.4.10.2 nathanw * modification, are permitted provided that the following conditions
12 1.4.10.2 nathanw * are met:
13 1.4.10.2 nathanw * 1. Redistributions of source code must retain the above copyright
14 1.4.10.2 nathanw * notice, this list of conditions and the following disclaimer.
15 1.4.10.2 nathanw * 2. Redistributions in binary form must reproduce the above copyright
16 1.4.10.2 nathanw * notice, this list of conditions and the following disclaimer in the
17 1.4.10.2 nathanw * documentation and/or other materials provided with the distribution.
18 1.4.10.2 nathanw * 3. All advertising materials mentioning features or use of this software
19 1.4.10.2 nathanw * must display the following acknowledgement:
20 1.4.10.2 nathanw * This product includes software developed by the NetBSD
21 1.4.10.2 nathanw * Foundation, Inc. and its contributors.
22 1.4.10.2 nathanw * 4. Neither the name of The NetBSD Foundation nor the names of its
23 1.4.10.2 nathanw * contributors may be used to endorse or promote products derived
24 1.4.10.2 nathanw * from this software without specific prior written permission.
25 1.4.10.2 nathanw *
26 1.4.10.2 nathanw * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 1.4.10.2 nathanw * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 1.4.10.2 nathanw * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 1.4.10.2 nathanw * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 1.4.10.2 nathanw * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 1.4.10.2 nathanw * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 1.4.10.2 nathanw * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 1.4.10.2 nathanw * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 1.4.10.2 nathanw * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 1.4.10.2 nathanw * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 1.4.10.2 nathanw * POSSIBILITY OF SUCH DAMAGE.
37 1.4.10.2 nathanw */
38 1.4.10.2 nathanw
39 1.4.10.2 nathanw #include <sys/types.h>
40 1.4.10.2 nathanw #include <sys/param.h>
41 1.4.10.2 nathanw #include <sys/systm.h>
42 1.4.10.2 nathanw #include <sys/device.h>
43 1.4.10.2 nathanw
44 1.4.10.2 nathanw #include <dev/isa/isavar.h>
45 1.4.10.2 nathanw #include <dev/isa/isareg.h>
46 1.4.10.2 nathanw
47 1.4.10.2 nathanw #include <machine/iomap.h>
48 1.4.10.2 nathanw
49 1.4.10.2 nathanw void isa_bus_init(void);
50 1.4.10.2 nathanw
51 1.4.10.2 nathanw static void new_imask(void);
52 1.4.10.2 nathanw static void isa_callback(int);
53 1.4.10.2 nathanw
54 1.4.10.2 nathanw /*
55 1.4.10.2 nathanw * Bitmask of currently enabled isa interrupts. Used by new_imask().
56 1.4.10.2 nathanw */
57 1.4.10.2 nathanw static u_int16_t imask_enable = 0xffff;
58 1.4.10.2 nathanw
59 1.4.10.2 nathanw #define IRQ_SLAVE 2 /* Slave at level 2 */
60 1.4.10.2 nathanw #define MILAN_MAX_ISA_INTS 16 /* Max. number of vectors */
61 1.4.10.2 nathanw #define ICU_OFFSET 0 /* Interrupt vector base */
62 1.4.10.2 nathanw
63 1.4.10.2 nathanw #define WICU(icu, val) *(volatile u_int8_t*)(icu) = val
64 1.4.10.2 nathanw
65 1.4.10.2 nathanw static isa_intr_info_t milan_isa_iinfo[MILAN_MAX_ISA_INTS];
66 1.4.10.2 nathanw
67 1.4.10.2 nathanw void
68 1.4.10.2 nathanw isa_bus_init()
69 1.4.10.2 nathanw {
70 1.4.10.2 nathanw volatile u_int8_t *icu;
71 1.4.10.2 nathanw
72 1.4.10.2 nathanw /*
73 1.4.10.2 nathanw * Initialize both the icu's:
74 1.4.10.2 nathanw * - enter Special Mask Mode
75 1.4.10.2 nathanw * - Block all interrupts
76 1.4.10.2 nathanw */
77 1.4.10.2 nathanw icu = (u_int8_t*)(AD_8259_MASTER);
78 1.4.10.2 nathanw
79 1.4.10.2 nathanw icu[0] = 0x11; /* reset; program device, four bytes */
80 1.4.10.2 nathanw icu[1] = ICU_OFFSET; /* starting at this vector index */
81 1.4.10.2 nathanw icu[1] = (1 << IRQ_SLAVE); /* slave on line 2 */
82 1.4.10.2 nathanw icu[1] = 1; /* 8086 mode */
83 1.4.10.2 nathanw icu[1] = 0xff; /* leave interrupts masked */
84 1.4.10.2 nathanw icu[0] = 0x68; /* special mask mode */
85 1.4.10.2 nathanw icu[0] = 0x0a; /* Read IRR by default. */
86 1.4.10.2 nathanw
87 1.4.10.2 nathanw icu = (u_int8_t*)(AD_8259_SLAVE);
88 1.4.10.2 nathanw
89 1.4.10.2 nathanw icu[0] = 0x11; /* reset; program device, four bytes */
90 1.4.10.2 nathanw icu[1] = ICU_OFFSET + 8; /* starting at this vector index */
91 1.4.10.2 nathanw icu[1] = IRQ_SLAVE; /* slave on line 2 */
92 1.4.10.2 nathanw icu[1] = 1; /* 8086 mode */
93 1.4.10.2 nathanw icu[1] = 0xff; /* leave interrupts masked */
94 1.4.10.2 nathanw icu[0] = 0x68; /* special mask mode */
95 1.4.10.2 nathanw icu[0] = 0x0a; /* Read IRR by default. */
96 1.4.10.2 nathanw }
97 1.4.10.2 nathanw
98 1.4.10.2 nathanw /*
99 1.4.10.2 nathanw * Determine and activate new interrupt mask by scanning the milan_isa_iinfo
100 1.4.10.2 nathanw * array for enabled interrupts.
101 1.4.10.2 nathanw */
102 1.4.10.2 nathanw static void
103 1.4.10.2 nathanw new_imask()
104 1.4.10.2 nathanw {
105 1.4.10.2 nathanw int irq;
106 1.4.10.2 nathanw u_int16_t nmask = 0;
107 1.4.10.2 nathanw
108 1.4.10.2 nathanw for (irq = 0; irq < MILAN_MAX_ISA_INTS; irq++) {
109 1.4.10.2 nathanw if (milan_isa_iinfo[irq].ifunc != NULL)
110 1.4.10.2 nathanw nmask |= 1 << irq;
111 1.4.10.2 nathanw if (nmask >= 0x100)
112 1.4.10.2 nathanw nmask |= 1 << IRQ_SLAVE;
113 1.4.10.2 nathanw }
114 1.4.10.2 nathanw imask_enable = ~nmask;
115 1.4.10.2 nathanw WICU(AD_8259_MASTER+1, imask_enable & 0xff);
116 1.4.10.2 nathanw WICU(AD_8259_SLAVE+1 , (imask_enable >> 8) & 0xff);
117 1.4.10.2 nathanw }
118 1.4.10.2 nathanw
119 1.4.10.2 nathanw static void
120 1.4.10.2 nathanw isa_callback(vector)
121 1.4.10.2 nathanw int vector;
122 1.4.10.2 nathanw {
123 1.4.10.2 nathanw isa_intr_info_t *iinfo_p;
124 1.4.10.2 nathanw int s;
125 1.4.10.2 nathanw
126 1.4.10.2 nathanw iinfo_p = &milan_isa_iinfo[vector];
127 1.4.10.2 nathanw
128 1.4.10.2 nathanw s = splx(iinfo_p->ipl);
129 1.4.10.2 nathanw (void) (iinfo_p->ifunc)(iinfo_p->iarg);
130 1.4.10.2 nathanw if (vector > 7)
131 1.4.10.2 nathanw WICU(AD_8259_SLAVE, 0x60 | (vector & 7));
132 1.4.10.2 nathanw else WICU(AD_8259_MASTER, 0x60 | (vector & 7));
133 1.4.10.2 nathanw splx(s);
134 1.4.10.2 nathanw }
135 1.4.10.2 nathanw
136 1.4.10.2 nathanw void milan_isa_intr(int, int);
137 1.4.10.2 nathanw void
138 1.4.10.2 nathanw milan_isa_intr(vector, sr)
139 1.4.10.2 nathanw int vector, sr;
140 1.4.10.2 nathanw {
141 1.4.10.2 nathanw isa_intr_info_t *iinfo_p;
142 1.4.10.2 nathanw int s;
143 1.4.10.2 nathanw
144 1.4.10.2 nathanw if (vector >= MILAN_MAX_ISA_INTS) {
145 1.4.10.2 nathanw printf("milan_isa_intr: Bogus vector %d\n", vector);
146 1.4.10.2 nathanw return;
147 1.4.10.2 nathanw }
148 1.4.10.2 nathanw
149 1.4.10.2 nathanw /* Ack cascade 0x60 == Specific EOI */
150 1.4.10.2 nathanw if (vector > 7)
151 1.4.10.2 nathanw WICU(AD_8259_MASTER, 0x60|IRQ_SLAVE);
152 1.4.10.2 nathanw
153 1.4.10.2 nathanw iinfo_p = &milan_isa_iinfo[vector];
154 1.4.10.2 nathanw if (iinfo_p->ifunc == NULL) {
155 1.4.10.2 nathanw printf("milan_isa_intr: Stray interrupt: %d (mask:%04x)\n",
156 1.4.10.2 nathanw vector, imask_enable);
157 1.4.10.2 nathanw return;
158 1.4.10.2 nathanw }
159 1.4.10.2 nathanw if ((sr & PSL_IPL) >= (iinfo_p->ipl & PSL_IPL)) {
160 1.4.10.2 nathanw /*
161 1.4.10.2 nathanw * We're running at a too high priority now.
162 1.4.10.2 nathanw */
163 1.4.10.2 nathanw add_sicallback((si_farg)isa_callback, (void*)vector, 0);
164 1.4.10.2 nathanw }
165 1.4.10.2 nathanw else {
166 1.4.10.2 nathanw s = splx(iinfo_p->ipl);
167 1.4.10.2 nathanw (void) (iinfo_p->ifunc)(iinfo_p->iarg);
168 1.4.10.2 nathanw if (vector > 7)
169 1.4.10.2 nathanw WICU(AD_8259_SLAVE, 0x60 | (vector & 7));
170 1.4.10.2 nathanw else WICU(AD_8259_MASTER, 0x60 | (vector & 7));
171 1.4.10.2 nathanw splx(s);
172 1.4.10.2 nathanw }
173 1.4.10.2 nathanw }
174 1.4.10.2 nathanw
175 1.4.10.2 nathanw /*
176 1.4.10.2 nathanw * Try to allocate a free interrupt... On the Milan, we have available:
177 1.4.10.2 nathanw * 5, 9, 10, 11, 13. Or in a bitmask: 0x1720.
178 1.4.10.2 nathanw */
179 1.4.10.2 nathanw #define MILAN_AVAIL_ISA_INTS 0x1720
180 1.4.10.2 nathanw
181 1.4.10.2 nathanw int
182 1.4.10.2 nathanw isa_intr_alloc(ic, mask, type, irq)
183 1.4.10.2 nathanw isa_chipset_tag_t ic;
184 1.4.10.2 nathanw int mask;
185 1.4.10.2 nathanw int type;
186 1.4.10.2 nathanw int *irq;
187 1.4.10.2 nathanw {
188 1.4.10.2 nathanw int i;
189 1.4.10.2 nathanw
190 1.4.10.2 nathanw /*
191 1.4.10.2 nathanw * Say no to impossible questions...
192 1.4.10.2 nathanw */
193 1.4.10.2 nathanw if (!(mask &= MILAN_AVAIL_ISA_INTS))
194 1.4.10.2 nathanw return 1;
195 1.4.10.2 nathanw
196 1.4.10.2 nathanw for (i = 0; i < MILAN_MAX_ISA_INTS; i++) {
197 1.4.10.2 nathanw if (mask & (1<<i)) {
198 1.4.10.2 nathanw if (milan_isa_iinfo[i].ifunc == NULL) {
199 1.4.10.2 nathanw *irq = i;
200 1.4.10.2 nathanw return 0;
201 1.4.10.2 nathanw }
202 1.4.10.2 nathanw }
203 1.4.10.2 nathanw }
204 1.4.10.2 nathanw return (1);
205 1.4.10.2 nathanw }
206 1.4.10.2 nathanw
207 1.4.10.2 nathanw void *
208 1.4.10.2 nathanw isa_intr_establish(ic, irq, type, level, ih_fun, ih_arg)
209 1.4.10.2 nathanw isa_chipset_tag_t ic;
210 1.4.10.2 nathanw int irq, type, level;
211 1.4.10.2 nathanw int (*ih_fun) __P((void *));
212 1.4.10.2 nathanw void *ih_arg;
213 1.4.10.2 nathanw {
214 1.4.10.2 nathanw isa_intr_info_t *iinfo_p;
215 1.4.10.2 nathanw
216 1.4.10.2 nathanw iinfo_p = &milan_isa_iinfo[irq];
217 1.4.10.2 nathanw
218 1.4.10.2 nathanw if (iinfo_p->ifunc != NULL) {
219 1.4.10.2 nathanw printf("isa_intr_establish: interrupt %d was already "
220 1.4.10.2 nathanw "established\n", irq);
221 1.4.10.2 nathanw return NULL;
222 1.4.10.2 nathanw }
223 1.4.10.2 nathanw
224 1.4.10.2 nathanw iinfo_p->slot = 0; /* Unused on Milan */
225 1.4.10.2 nathanw iinfo_p->ihand = NULL; /* Unused on Milan */
226 1.4.10.2 nathanw iinfo_p->ipl = level;
227 1.4.10.2 nathanw iinfo_p->ifunc = ih_fun;
228 1.4.10.2 nathanw iinfo_p->iarg = ih_arg;
229 1.4.10.2 nathanw
230 1.4.10.2 nathanw new_imask();
231 1.4.10.2 nathanw return(iinfo_p);
232 1.4.10.2 nathanw }
233 1.4.10.2 nathanw
234 1.4.10.2 nathanw void
235 1.4.10.2 nathanw isa_intr_disestablish(ic, handler)
236 1.4.10.2 nathanw isa_chipset_tag_t ic;
237 1.4.10.2 nathanw void *handler;
238 1.4.10.2 nathanw {
239 1.4.10.2 nathanw isa_intr_info_t *iinfo_p = (isa_intr_info_t *)handler;
240 1.4.10.2 nathanw
241 1.4.10.2 nathanw if (iinfo_p->ifunc == NULL)
242 1.4.10.3 nathanw panic("isa_intr_disestablish: interrupt was not established");
243 1.4.10.2 nathanw
244 1.4.10.2 nathanw iinfo_p->ifunc = NULL;
245 1.4.10.2 nathanw new_imask();
246 1.4.10.2 nathanw }
247