isa_milan.c revision 1.4
1 /* $NetBSD: isa_milan.c,v 1.4 2001/05/29 05:58:18 leo Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Leo Weppelman. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/types.h> 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/device.h> 43 44 #include <dev/isa/isavar.h> 45 #include <dev/isa/isareg.h> 46 47 #include <machine/iomap.h> 48 49 void isa_bus_init(void); 50 #if 0 51 static void init_icu(void); 52 #endif 53 static void set_icus(void); 54 static void calc_imask(void); 55 static void isa_callback(int); 56 57 /* 58 * Bitmask of currently enabled isa interrupts. Used by set_icus(). 59 */ 60 static u_int16_t imask_enable = 0xffff; 61 62 #define IRQ_SLAVE 2 63 64 /* 65 * Interrupt routing table 66 */ 67 #define MILAN_MAX_ISA_INTS 16 68 69 static isa_intr_info_t milan_isa_iinfo[MILAN_MAX_ISA_INTS]; 70 71 void 72 isa_bus_init() 73 { 74 #if 0 75 init_icu(); 76 #endif 77 set_icus(); 78 } 79 80 #if 0 81 /* 82 * XXX: For some reason, this does not work at all... (Leo). 83 */ 84 static void 85 init_icu() 86 { 87 #define ICU_OFFSET 0 88 89 u_int8_t *icu; 90 91 icu = (u_int8_t*)(AD_8259_MASTER); 92 93 icu[0] = 0x11; /* reset; program device, four bytes */ 94 icu[1] = ICU_OFFSET; /* starting at this vector index */ 95 icu[1] = (1 << IRQ_SLAVE); /* slave on line 2 */ 96 icu[1] = 1; /* 8086 mode */ 97 icu[1] = 0xff; /* leave interrupts masked */ 98 99 icu = (u_int8_t*)(AD_8259_SLAVE); 100 101 icu[0] = 0x11; /* reset; program device, four bytes */ 102 icu[1] = ICU_OFFSET + 8; /* starting at this vector index */ 103 icu[1] = IRQ_SLAVE; /* slave on line 2 */ 104 icu[1] = 1; /* 8086 mode */ 105 icu[1] = 0xff; /* leave interrupts masked */ 106 } 107 #endif 108 109 static void 110 set_icus() 111 { 112 u_int8_t *icu; 113 114 icu = (u_int8_t*)AD_8259_MASTER; 115 icu[1] = imask_enable & 0xff; 116 icu = (u_int8_t*)AD_8259_SLAVE; 117 icu[1] = (imask_enable >> 8) & 0xff; 118 } 119 120 static void 121 calc_imask() 122 { 123 int irq; 124 u_int16_t nmask = 0; 125 126 for (irq = 0; irq < MILAN_MAX_ISA_INTS; irq++) { 127 if (milan_isa_iinfo[irq].ifunc != NULL) 128 nmask |= 1 << irq; 129 if (nmask >= 0x100) 130 nmask |= 1 << IRQ_SLAVE; 131 } 132 imask_enable = ~nmask; 133 set_icus(); 134 } 135 136 static void 137 isa_callback(vector) 138 int vector; 139 { 140 isa_intr_info_t *iinfo_p; 141 int s; 142 143 iinfo_p = &milan_isa_iinfo[vector]; 144 145 s = splx(iinfo_p->ipl); 146 (void) (iinfo_p->ifunc)(iinfo_p->iarg); 147 splx(s); 148 } 149 150 void milan_isa_intr(int, int); 151 void 152 milan_isa_intr(vector, sr) 153 int vector, sr; 154 { 155 isa_intr_info_t *iinfo_p; 156 int s; 157 158 if (vector >= MILAN_MAX_ISA_INTS) { 159 printf("milan_isa_intr: Bogus vector %d\n", vector); 160 return; 161 } 162 163 /* Acknowledge interrupt XXX 0x20 == EOI */ 164 if (vector > 7) 165 *((u_char *)AD_8259_SLAVE) = 0x20; 166 *((u_char *)AD_8259_MASTER) = 0x20; 167 168 iinfo_p = &milan_isa_iinfo[vector]; 169 if (iinfo_p->ifunc == NULL) { 170 printf("milan_isa_intr: Stray interrupt: %d (mask:%04x)\n", 171 vector, imask_enable); 172 return; 173 } 174 if ((sr & PSL_IPL) >= (iinfo_p->ipl & PSL_IPL)) { 175 /* 176 * We're running at a too high priority now. 177 */ 178 add_sicallback((si_farg)isa_callback, (void*)vector, 0); 179 } 180 else { 181 s = splx(iinfo_p->ipl); 182 (void) (iinfo_p->ifunc)(iinfo_p->iarg); 183 splx(s); 184 } 185 } 186 187 188 /* 189 * Try to allocate a free interrupt... On the Milan, we have available: 190 * 5, 9, 10, 11, 13. Or in a bitmask: 0x1720. 191 */ 192 #define MILAN_AVAIL_ISA_INTS 0x1720 193 194 int 195 isa_intr_alloc(ic, mask, type, irq) 196 isa_chipset_tag_t ic; 197 int mask; 198 int type; 199 int *irq; 200 { 201 int i; 202 203 /* 204 * The Hades only supports edge triggered interrupts! 205 * XXX: Find out about the Milan.... 206 */ 207 if (type != IST_EDGE) 208 return 1; 209 210 /* 211 * Say no to impossible questions... 212 */ 213 if (!(mask &= MILAN_AVAIL_ISA_INTS)) 214 return 1; 215 216 for (i = 0; i < MILAN_MAX_ISA_INTS; i++) { 217 if (mask & (1<<i)) { 218 if (milan_isa_iinfo[i].ifunc == NULL) { 219 *irq = i; 220 return 0; 221 } 222 } 223 } 224 return (1); 225 } 226 227 void * 228 isa_intr_establish(ic, irq, type, level, ih_fun, ih_arg) 229 isa_chipset_tag_t ic; 230 int irq, type, level; 231 int (*ih_fun) __P((void *)); 232 void *ih_arg; 233 { 234 isa_intr_info_t *iinfo_p; 235 236 /* 237 * The Hades only supports edge triggered interrupts! 238 * XXX: Find out oubout the Milan... 239 */ 240 if (type != IST_EDGE) 241 return NULL; 242 243 iinfo_p = &milan_isa_iinfo[irq]; 244 245 if (iinfo_p->ifunc != NULL) { 246 printf("isa_intr_establish: interrupt %d was already " 247 "established\n", irq); 248 return NULL; 249 } 250 251 iinfo_p->slot = 0; /* Unused on Milan */ 252 iinfo_p->ihand = NULL; /* Unused on Milan */ 253 iinfo_p->ipl = level; 254 iinfo_p->ifunc = ih_fun; 255 iinfo_p->iarg = ih_arg; 256 257 calc_imask(); 258 return(iinfo_p); 259 } 260 261 void 262 isa_intr_disestablish(ic, handler) 263 isa_chipset_tag_t ic; 264 void *handler; 265 { 266 isa_intr_info_t *iinfo_p = (isa_intr_info_t *)handler; 267 268 if (iinfo_p->ifunc == NULL) 269 panic("isa_intr_disestablish: interrupt was not established\n"); 270 271 iinfo_p->ifunc = NULL; 272 calc_imask(); 273 } 274
Indexes created Fri Oct 03 02:09:57 GMT 2025