isa_milan.c revision 1.5
1 /* $NetBSD: isa_milan.c,v 1.5 2002/02/23 20:44:45 leo Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Leo Weppelman. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/types.h> 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/device.h> 43 44 #include <dev/isa/isavar.h> 45 #include <dev/isa/isareg.h> 46 47 #include <machine/iomap.h> 48 49 void isa_bus_init(void); 50 51 static void new_imask(void); 52 static void isa_callback(int); 53 54 /* 55 * Bitmask of currently enabled isa interrupts. Used by new_imask(). 56 */ 57 static u_int16_t imask_enable = 0xffff; 58 59 #define IRQ_SLAVE 2 /* Slave at level 2 */ 60 #define MILAN_MAX_ISA_INTS 16 /* Max. number of vectors */ 61 #define ICU_OFFSET 0 /* Interrupt vector base */ 62 63 #define WICU(icu, val) *(volatile u_int8_t*)(icu) = val 64 65 static isa_intr_info_t milan_isa_iinfo[MILAN_MAX_ISA_INTS]; 66 67 void 68 isa_bus_init() 69 { 70 volatile u_int8_t *icu; 71 72 /* 73 * Initialize both the icu's: 74 * - enter Special Mask Mode 75 * - Block all interrupts 76 */ 77 icu = (u_int8_t*)(AD_8259_MASTER); 78 79 icu[0] = 0x11; /* reset; program device, four bytes */ 80 icu[1] = ICU_OFFSET; /* starting at this vector index */ 81 icu[1] = (1 << IRQ_SLAVE); /* slave on line 2 */ 82 icu[1] = 1; /* 8086 mode */ 83 icu[1] = 0xff; /* leave interrupts masked */ 84 icu[0] = 0x68; /* special mask mode */ 85 icu[0] = 0x0a; /* Read IRR by default. */ 86 87 icu = (u_int8_t*)(AD_8259_SLAVE); 88 89 icu[0] = 0x11; /* reset; program device, four bytes */ 90 icu[1] = ICU_OFFSET + 8; /* starting at this vector index */ 91 icu[1] = IRQ_SLAVE; /* slave on line 2 */ 92 icu[1] = 1; /* 8086 mode */ 93 icu[1] = 0xff; /* leave interrupts masked */ 94 icu[0] = 0x68; /* special mask mode */ 95 icu[0] = 0x0a; /* Read IRR by default. */ 96 } 97 98 /* 99 * Determine and activate new interrupt mask by scanning the milan_isa_iinfo 100 * array for enabled interrupts. 101 */ 102 static void 103 new_imask() 104 { 105 int irq; 106 u_int16_t nmask = 0; 107 108 for (irq = 0; irq < MILAN_MAX_ISA_INTS; irq++) { 109 if (milan_isa_iinfo[irq].ifunc != NULL) 110 nmask |= 1 << irq; 111 if (nmask >= 0x100) 112 nmask |= 1 << IRQ_SLAVE; 113 } 114 imask_enable = ~nmask; 115 WICU(AD_8259_MASTER+1, imask_enable & 0xff); 116 WICU(AD_8259_SLAVE+1 , (imask_enable >> 8) & 0xff); 117 } 118 119 static void 120 isa_callback(vector) 121 int vector; 122 { 123 isa_intr_info_t *iinfo_p; 124 int s; 125 126 iinfo_p = &milan_isa_iinfo[vector]; 127 128 s = splx(iinfo_p->ipl); 129 (void) (iinfo_p->ifunc)(iinfo_p->iarg); 130 if (vector > 7) 131 WICU(AD_8259_SLAVE, 0x60 | (vector & 7)); 132 else WICU(AD_8259_MASTER, 0x60 | (vector & 7)); 133 splx(s); 134 } 135 136 void milan_isa_intr(int, int); 137 void 138 milan_isa_intr(vector, sr) 139 int vector, sr; 140 { 141 isa_intr_info_t *iinfo_p; 142 int s; 143 144 if (vector >= MILAN_MAX_ISA_INTS) { 145 printf("milan_isa_intr: Bogus vector %d\n", vector); 146 return; 147 } 148 149 /* Ack cascade 0x60 == Specific EOI */ 150 if (vector > 7) 151 WICU(AD_8259_MASTER, 0x60|IRQ_SLAVE); 152 153 iinfo_p = &milan_isa_iinfo[vector]; 154 if (iinfo_p->ifunc == NULL) { 155 printf("milan_isa_intr: Stray interrupt: %d (mask:%04x)\n", 156 vector, imask_enable); 157 return; 158 } 159 if ((sr & PSL_IPL) >= (iinfo_p->ipl & PSL_IPL)) { 160 /* 161 * We're running at a too high priority now. 162 */ 163 add_sicallback((si_farg)isa_callback, (void*)vector, 0); 164 } 165 else { 166 s = splx(iinfo_p->ipl); 167 (void) (iinfo_p->ifunc)(iinfo_p->iarg); 168 if (vector > 7) 169 WICU(AD_8259_SLAVE, 0x60 | (vector & 7)); 170 else WICU(AD_8259_MASTER, 0x60 | (vector & 7)); 171 splx(s); 172 } 173 } 174 175 /* 176 * Try to allocate a free interrupt... On the Milan, we have available: 177 * 5, 9, 10, 11, 13. Or in a bitmask: 0x1720. 178 */ 179 #define MILAN_AVAIL_ISA_INTS 0x1720 180 181 int 182 isa_intr_alloc(ic, mask, type, irq) 183 isa_chipset_tag_t ic; 184 int mask; 185 int type; 186 int *irq; 187 { 188 int i; 189 190 /* 191 * Say no to impossible questions... 192 */ 193 if (!(mask &= MILAN_AVAIL_ISA_INTS)) 194 return 1; 195 196 for (i = 0; i < MILAN_MAX_ISA_INTS; i++) { 197 if (mask & (1<<i)) { 198 if (milan_isa_iinfo[i].ifunc == NULL) { 199 *irq = i; 200 return 0; 201 } 202 } 203 } 204 return (1); 205 } 206 207 void * 208 isa_intr_establish(ic, irq, type, level, ih_fun, ih_arg) 209 isa_chipset_tag_t ic; 210 int irq, type, level; 211 int (*ih_fun) __P((void *)); 212 void *ih_arg; 213 { 214 isa_intr_info_t *iinfo_p; 215 216 iinfo_p = &milan_isa_iinfo[irq]; 217 218 if (iinfo_p->ifunc != NULL) { 219 printf("isa_intr_establish: interrupt %d was already " 220 "established\n", irq); 221 return NULL; 222 } 223 224 iinfo_p->slot = 0; /* Unused on Milan */ 225 iinfo_p->ihand = NULL; /* Unused on Milan */ 226 iinfo_p->ipl = level; 227 iinfo_p->ifunc = ih_fun; 228 iinfo_p->iarg = ih_arg; 229 230 new_imask(); 231 return(iinfo_p); 232 } 233 234 void 235 isa_intr_disestablish(ic, handler) 236 isa_chipset_tag_t ic; 237 void *handler; 238 { 239 isa_intr_info_t *iinfo_p = (isa_intr_info_t *)handler; 240 241 if (iinfo_p->ifunc == NULL) 242 panic("isa_intr_disestablish: interrupt was not established\n"); 243 244 iinfo_p->ifunc = NULL; 245 new_imask(); 246 } 247
Indexes created Fri Oct 03 02:09:57 GMT 2025