isa_milan.c revision 1.6.6.3
1 /* $NetBSD: isa_milan.c,v 1.6.6.3 2004/09/21 13:14:11 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Leo Weppelman. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: isa_milan.c,v 1.6.6.3 2004/09/21 13:14:11 skrll Exp $"); 41 42 #include <sys/types.h> 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/device.h> 46 47 #include <dev/isa/isavar.h> 48 #include <dev/isa/isareg.h> 49 50 #include <machine/iomap.h> 51 52 void isa_bus_init(void); 53 54 static void new_imask(void); 55 static void isa_callback(int); 56 57 /* 58 * Bitmask of currently enabled isa interrupts. Used by new_imask(). 59 */ 60 static u_int16_t imask_enable = 0xffff; 61 62 #define IRQ_SLAVE 2 /* Slave at level 2 */ 63 #define MILAN_MAX_ISA_INTS 16 /* Max. number of vectors */ 64 #define ICU_OFFSET 0 /* Interrupt vector base */ 65 66 #define WICU(icu, val) *(volatile u_int8_t*)(icu) = val 67 68 static isa_intr_info_t milan_isa_iinfo[MILAN_MAX_ISA_INTS]; 69 70 void 71 isa_bus_init() 72 { 73 volatile u_int8_t *icu; 74 75 /* 76 * Initialize both the icu's: 77 * - enter Special Mask Mode 78 * - Block all interrupts 79 */ 80 icu = (u_int8_t*)(AD_8259_MASTER); 81 82 icu[0] = 0x11; /* reset; program device, four bytes */ 83 icu[1] = ICU_OFFSET; /* starting at this vector index */ 84 icu[1] = (1 << IRQ_SLAVE); /* slave on line 2 */ 85 icu[1] = 1; /* 8086 mode */ 86 icu[1] = 0xff; /* leave interrupts masked */ 87 icu[0] = 0x68; /* special mask mode */ 88 icu[0] = 0x0a; /* Read IRR by default. */ 89 90 icu = (u_int8_t*)(AD_8259_SLAVE); 91 92 icu[0] = 0x11; /* reset; program device, four bytes */ 93 icu[1] = ICU_OFFSET + 8; /* starting at this vector index */ 94 icu[1] = IRQ_SLAVE; /* slave on line 2 */ 95 icu[1] = 1; /* 8086 mode */ 96 icu[1] = 0xff; /* leave interrupts masked */ 97 icu[0] = 0x68; /* special mask mode */ 98 icu[0] = 0x0a; /* Read IRR by default. */ 99 } 100 101 /* 102 * Determine and activate new interrupt mask by scanning the milan_isa_iinfo 103 * array for enabled interrupts. 104 */ 105 static void 106 new_imask() 107 { 108 int irq; 109 u_int16_t nmask = 0; 110 111 for (irq = 0; irq < MILAN_MAX_ISA_INTS; irq++) { 112 if (milan_isa_iinfo[irq].ifunc != NULL) 113 nmask |= 1 << irq; 114 if (nmask >= 0x100) 115 nmask |= 1 << IRQ_SLAVE; 116 } 117 imask_enable = ~nmask; 118 WICU(AD_8259_MASTER+1, imask_enable & 0xff); 119 WICU(AD_8259_SLAVE+1 , (imask_enable >> 8) & 0xff); 120 } 121 122 static void 123 isa_callback(vector) 124 int vector; 125 { 126 isa_intr_info_t *iinfo_p; 127 int s; 128 129 iinfo_p = &milan_isa_iinfo[vector]; 130 131 s = splx(iinfo_p->ipl); 132 (void) (iinfo_p->ifunc)(iinfo_p->iarg); 133 if (vector > 7) 134 WICU(AD_8259_SLAVE, 0x60 | (vector & 7)); 135 else WICU(AD_8259_MASTER, 0x60 | (vector & 7)); 136 splx(s); 137 } 138 139 void milan_isa_intr(int, int); 140 void 141 milan_isa_intr(vector, sr) 142 int vector, sr; 143 { 144 isa_intr_info_t *iinfo_p; 145 int s; 146 147 if (vector >= MILAN_MAX_ISA_INTS) { 148 printf("milan_isa_intr: Bogus vector %d\n", vector); 149 return; 150 } 151 152 /* Ack cascade 0x60 == Specific EOI */ 153 if (vector > 7) 154 WICU(AD_8259_MASTER, 0x60|IRQ_SLAVE); 155 156 iinfo_p = &milan_isa_iinfo[vector]; 157 if (iinfo_p->ifunc == NULL) { 158 printf("milan_isa_intr: Stray interrupt: %d (mask:%04x)\n", 159 vector, imask_enable); 160 return; 161 } 162 if ((sr & PSL_IPL) >= (iinfo_p->ipl & PSL_IPL)) { 163 /* 164 * We're running at a too high priority now. 165 */ 166 add_sicallback((si_farg)isa_callback, (void*)vector, 0); 167 } 168 else { 169 s = splx(iinfo_p->ipl); 170 (void) (iinfo_p->ifunc)(iinfo_p->iarg); 171 if (vector > 7) 172 WICU(AD_8259_SLAVE, 0x60 | (vector & 7)); 173 else WICU(AD_8259_MASTER, 0x60 | (vector & 7)); 174 splx(s); 175 } 176 } 177 178 /* 179 * Try to allocate a free interrupt... On the Milan, we have available: 180 * 5, 9, 10, 11, 13. Or in a bitmask: 0x1720. 181 */ 182 #define MILAN_AVAIL_ISA_INTS 0x1720 183 184 int 185 isa_intr_alloc(ic, mask, type, irq) 186 isa_chipset_tag_t ic; 187 int mask; 188 int type; 189 int *irq; 190 { 191 int i; 192 193 /* 194 * Say no to impossible questions... 195 */ 196 if (!(mask &= MILAN_AVAIL_ISA_INTS)) 197 return 1; 198 199 for (i = 0; i < MILAN_MAX_ISA_INTS; i++) { 200 if (mask & (1<<i)) { 201 if (milan_isa_iinfo[i].ifunc == NULL) { 202 *irq = i; 203 return 0; 204 } 205 } 206 } 207 return (1); 208 } 209 210 void * 211 isa_intr_establish(ic, irq, type, level, ih_fun, ih_arg) 212 isa_chipset_tag_t ic; 213 int irq, type, level; 214 int (*ih_fun) __P((void *)); 215 void *ih_arg; 216 { 217 isa_intr_info_t *iinfo_p; 218 219 iinfo_p = &milan_isa_iinfo[irq]; 220 221 if (iinfo_p->ifunc != NULL) { 222 printf("isa_intr_establish: interrupt %d was already " 223 "established\n", irq); 224 return NULL; 225 } 226 227 iinfo_p->slot = 0; /* Unused on Milan */ 228 iinfo_p->ihand = NULL; /* Unused on Milan */ 229 iinfo_p->ipl = level; 230 iinfo_p->ifunc = ih_fun; 231 iinfo_p->iarg = ih_arg; 232 233 new_imask(); 234 return(iinfo_p); 235 } 236 237 void 238 isa_intr_disestablish(ic, handler) 239 isa_chipset_tag_t ic; 240 void *handler; 241 { 242 isa_intr_info_t *iinfo_p = (isa_intr_info_t *)handler; 243 244 if (iinfo_p->ifunc == NULL) 245 panic("isa_intr_disestablish: interrupt was not established"); 246 247 iinfo_p->ifunc = NULL; 248 new_imask(); 249 } 250
Indexes created Fri Oct 03 02:09:57 GMT 2025