pci_machdep.c revision 1.26 1 1.26 leo /* $NetBSD: pci_machdep.c,v 1.26 2000/09/28 06:39:52 leo Exp $ */
2 1.1 leo
3 1.1 leo /*
4 1.1 leo * Copyright (c) 1996 Leo Weppelman. All rights reserved.
5 1.7 cgd * Copyright (c) 1996, 1997 Christopher G. Demetriou. All rights reserved.
6 1.13 mycroft * Copyright (c) 1994 Charles M. Hannum. All rights reserved.
7 1.1 leo *
8 1.1 leo * Redistribution and use in source and binary forms, with or without
9 1.1 leo * modification, are permitted provided that the following conditions
10 1.1 leo * are met:
11 1.1 leo * 1. Redistributions of source code must retain the above copyright
12 1.1 leo * notice, this list of conditions and the following disclaimer.
13 1.1 leo * 2. Redistributions in binary form must reproduce the above copyright
14 1.1 leo * notice, this list of conditions and the following disclaimer in the
15 1.1 leo * documentation and/or other materials provided with the distribution.
16 1.1 leo * 3. All advertising materials mentioning features or use of this software
17 1.1 leo * must display the following acknowledgement:
18 1.13 mycroft * This product includes software developed by Charles M. Hannum.
19 1.1 leo * 4. The name of the author may not be used to endorse or promote products
20 1.1 leo * derived from this software without specific prior written permission.
21 1.1 leo *
22 1.1 leo * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 1.1 leo * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 1.1 leo * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 1.1 leo * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 1.1 leo * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 1.1 leo * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 1.1 leo * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 1.1 leo * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 1.1 leo * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 1.1 leo * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 1.1 leo */
33 1.1 leo
34 1.1 leo #include <sys/types.h>
35 1.1 leo #include <sys/param.h>
36 1.1 leo #include <sys/time.h>
37 1.1 leo #include <sys/systm.h>
38 1.1 leo #include <sys/errno.h>
39 1.1 leo #include <sys/device.h>
40 1.14 thomas #include <sys/malloc.h>
41 1.1 leo
42 1.24 mrg #include <uvm/uvm_extern.h>
43 1.1 leo
44 1.1 leo #include <dev/pci/pcivar.h>
45 1.1 leo #include <dev/pci/pcireg.h>
46 1.1 leo
47 1.1 leo #include <machine/cpu.h>
48 1.1 leo #include <machine/iomap.h>
49 1.9 leo #include <machine/mfp.h>
50 1.16 leo #include <machine/bswap.h>
51 1.10 leo #include <machine/bus.h>
52 1.10 leo
53 1.1 leo #include <atari/atari/device.h>
54 1.17 leo #include <atari/pci/pci_vga.h>
55 1.1 leo
56 1.9 leo /*
57 1.14 thomas * Sizes of pci memory and I/O area.
58 1.9 leo */
59 1.14 thomas #define PCI_MEM_END 0x10000000 /* 256 MByte */
60 1.14 thomas #define PCI_IO_END 0x10000000 /* 256 MByte */
61 1.14 thomas
62 1.14 thomas /*
63 1.14 thomas * We preserve some space at the begin of the pci area for 32BIT_1M
64 1.14 thomas * devices and standard vga.
65 1.14 thomas */
66 1.14 thomas #define PCI_MEM_START 0x00100000 /* 1 MByte */
67 1.15 thomas #define PCI_IO_START 0x00004000 /* 16 kByte (some PCI cards allow only
68 1.25 leo I/O addresses up to 0xffff) */
69 1.20 thomas
70 1.20 thomas /*
71 1.20 thomas * PCI memory and IO should be aligned acording to this masks
72 1.20 thomas */
73 1.20 thomas #define PCI_MACHDEP_IO_ALIGN_MASK 0xffffff00
74 1.20 thomas #define PCI_MACHDEP_MEM_ALIGN_MASK 0xfffff000
75 1.20 thomas
76 1.19 leo /*
77 1.19 leo * Convert a PCI 'device' number to a slot number.
78 1.19 leo */
79 1.19 leo #define DEV2SLOT(dev) (3 - dev)
80 1.14 thomas
81 1.14 thomas /*
82 1.14 thomas * Struct to hold the memory and I/O datas of the pci devices
83 1.14 thomas */
84 1.14 thomas struct pci_memreg {
85 1.14 thomas LIST_ENTRY(pci_memreg) link;
86 1.14 thomas int dev;
87 1.14 thomas pcitag_t tag;
88 1.14 thomas pcireg_t reg, address, mask;
89 1.14 thomas u_int32_t size;
90 1.14 thomas u_int32_t csr;
91 1.14 thomas };
92 1.14 thomas
93 1.14 thomas typedef LIST_HEAD(pci_memreg_head, pci_memreg) PCI_MEMREG;
94 1.9 leo
95 1.1 leo int pcibusprint __P((void *auxp, const char *));
96 1.5 leo int pcibusmatch __P((struct device *, struct cfdata *, void *));
97 1.1 leo void pcibusattach __P((struct device *, struct device *, void *));
98 1.1 leo
99 1.14 thomas static void enable_pci_devices __P((void));
100 1.14 thomas static void insert_into_list __P((PCI_MEMREG *head, struct pci_memreg *elem));
101 1.14 thomas static int overlap_pci_areas __P((struct pci_memreg *p,
102 1.14 thomas struct pci_memreg *self, u_int addr, u_int size, u_int what));
103 1.1 leo static int pci_config_offset __P((pcitag_t));
104 1.1 leo
105 1.1 leo struct cfattach pcibus_ca = {
106 1.1 leo sizeof(struct device), pcibusmatch, pcibusattach
107 1.1 leo };
108 1.1 leo
109 1.1 leo int
110 1.5 leo pcibusmatch(pdp, cfp, auxp)
111 1.1 leo struct device *pdp;
112 1.5 leo struct cfdata *cfp;
113 1.5 leo void *auxp;
114 1.1 leo {
115 1.26 leo static int nmatched = 0;
116 1.26 leo
117 1.1 leo if(atari_realconfig == 0)
118 1.1 leo return (0);
119 1.26 leo
120 1.26 leo if (strcmp((char *)auxp, "pcibus"))
121 1.26 leo return (0); /* Wrong number... */
122 1.26 leo
123 1.26 leo if (machineid & ATARI_HADES) {
124 1.26 leo /*
125 1.26 leo * The Hades has only one pci bus
126 1.26 leo */
127 1.26 leo if (nmatched)
128 1.26 leo return (0);
129 1.26 leo nmatched++;
130 1.26 leo return (1);
131 1.26 leo }
132 1.26 leo return (0);
133 1.1 leo }
134 1.1 leo
135 1.1 leo void
136 1.1 leo pcibusattach(pdp, dp, auxp)
137 1.1 leo struct device *pdp, *dp;
138 1.1 leo void *auxp;
139 1.1 leo {
140 1.1 leo struct pcibus_attach_args pba;
141 1.1 leo
142 1.14 thomas enable_pci_devices();
143 1.14 thomas
144 1.1 leo pba.pba_busname = "pci";
145 1.4 leo pba.pba_pc = NULL;
146 1.1 leo pba.pba_bus = 0;
147 1.7 cgd pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED;
148 1.10 leo pba.pba_dmat = BUS_PCI_DMA_TAG;
149 1.21 leo pba.pba_iot = leb_alloc_bus_space_tag(NULL);
150 1.21 leo pba.pba_memt = leb_alloc_bus_space_tag(NULL);
151 1.11 leo if ((pba.pba_iot == NULL) || (pba.pba_memt == NULL)) {
152 1.11 leo printf("leb_alloc_bus_space_tag failed!\n");
153 1.11 leo return;
154 1.11 leo }
155 1.11 leo pba.pba_iot->base = PCI_IO_PHYS;
156 1.11 leo pba.pba_memt->base = PCI_MEM_PHYS;
157 1.6 leo
158 1.9 leo MFP2->mf_aer &= ~(0x27); /* PCI interrupts: HIGH -> LOW */
159 1.9 leo
160 1.6 leo printf("\n");
161 1.1 leo
162 1.1 leo config_found(dp, &pba, pcibusprint);
163 1.1 leo }
164 1.1 leo
165 1.1 leo int
166 1.1 leo pcibusprint(auxp, name)
167 1.1 leo void *auxp;
168 1.1 leo const char *name;
169 1.1 leo {
170 1.1 leo if(name == NULL)
171 1.1 leo return(UNCONF);
172 1.1 leo return(QUIET);
173 1.1 leo }
174 1.1 leo
175 1.1 leo void
176 1.1 leo pci_attach_hook(parent, self, pba)
177 1.1 leo struct device *parent, *self;
178 1.1 leo struct pcibus_attach_args *pba;
179 1.1 leo {
180 1.1 leo }
181 1.1 leo
182 1.1 leo /*
183 1.9 leo * Initialize the PCI-bus. The Atari-BIOS does not do this, so....
184 1.14 thomas * We only disable all devices here. Memory and I/O enabling is done
185 1.14 thomas * later at pcibusattach.
186 1.9 leo */
187 1.9 leo void
188 1.9 leo init_pci_bus()
189 1.9 leo {
190 1.9 leo pci_chipset_tag_t pc = NULL; /* XXX */
191 1.9 leo pcitag_t tag;
192 1.14 thomas pcireg_t csr;
193 1.14 thomas int device, id, maxndevs;
194 1.9 leo
195 1.14 thomas tag = 0;
196 1.14 thomas id = 0;
197 1.9 leo
198 1.9 leo maxndevs = pci_bus_maxdevs(pc, 0);
199 1.9 leo
200 1.9 leo for (device = 0; device < maxndevs; device++) {
201 1.9 leo
202 1.9 leo tag = pci_make_tag(pc, 0, device, 0);
203 1.9 leo id = pci_conf_read(pc, tag, PCI_ID_REG);
204 1.9 leo if (id == 0 || id == 0xffffffff)
205 1.9 leo continue;
206 1.9 leo
207 1.14 thomas csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
208 1.14 thomas csr &= ~(PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_IO_ENABLE);
209 1.14 thomas csr &= ~PCI_COMMAND_MASTER_ENABLE;
210 1.14 thomas pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
211 1.14 thomas }
212 1.17 leo
213 1.17 leo /*
214 1.17 leo * Scan the bus for a VGA-card that we support. If we find
215 1.17 leo * one, try to initialize it to a 'standard' text mode (80x25).
216 1.17 leo */
217 1.17 leo check_for_vga();
218 1.14 thomas }
219 1.14 thomas
220 1.14 thomas /*
221 1.14 thomas * insert a new element in an existing list that the ID's (size in struct
222 1.14 thomas * pci_memreg) are sorted.
223 1.14 thomas */
224 1.14 thomas static void
225 1.14 thomas insert_into_list(head, elem)
226 1.14 thomas PCI_MEMREG *head;
227 1.14 thomas struct pci_memreg *elem;
228 1.14 thomas {
229 1.14 thomas struct pci_memreg *p, *q;
230 1.14 thomas
231 1.14 thomas p = LIST_FIRST(head);
232 1.14 thomas q = NULL;
233 1.14 thomas
234 1.14 thomas for (; p != NULL && p->size < elem->size; q = p, p = LIST_NEXT(p, link));
235 1.14 thomas
236 1.14 thomas if (q == NULL) {
237 1.14 thomas LIST_INSERT_HEAD(head, elem, link);
238 1.14 thomas } else {
239 1.14 thomas LIST_INSERT_AFTER(q, elem, link);
240 1.14 thomas }
241 1.14 thomas }
242 1.14 thomas
243 1.14 thomas /*
244 1.14 thomas * Test if a new selected area overlaps with an already (probably preselected)
245 1.14 thomas * pci area.
246 1.14 thomas */
247 1.14 thomas static int
248 1.14 thomas overlap_pci_areas(p, self, addr, size, what)
249 1.14 thomas struct pci_memreg *p, *self;
250 1.14 thomas u_int addr, size, what;
251 1.14 thomas {
252 1.14 thomas struct pci_memreg *q;
253 1.14 thomas
254 1.14 thomas if (p == NULL)
255 1.14 thomas return 0;
256 1.14 thomas
257 1.14 thomas q = p;
258 1.14 thomas while (q != NULL) {
259 1.14 thomas if ((q != self) && (q->csr & what)) {
260 1.14 thomas if ((addr >= q->address) && (addr < (q->address + q->size))) {
261 1.14 thomas #ifdef DEBUG_PCI_MACHDEP
262 1.14 thomas printf("\noverlap area dev %d reg 0x%02x with dev %d reg 0x%02x",
263 1.14 thomas self->dev, self->reg, q->dev, q->reg);
264 1.14 thomas #endif
265 1.14 thomas return 1;
266 1.14 thomas }
267 1.14 thomas if ((q->address >= addr) && (q->address < (addr + size))) {
268 1.14 thomas #ifdef DEBUG_PCI_MACHDEP
269 1.14 thomas printf("\noverlap area dev %d reg 0x%02x with dev %d reg 0x%02x",
270 1.14 thomas self->dev, self->reg, q->dev, q->reg);
271 1.14 thomas #endif
272 1.14 thomas return 1;
273 1.14 thomas }
274 1.14 thomas }
275 1.14 thomas q = LIST_NEXT(q, link);
276 1.14 thomas }
277 1.14 thomas return 0;
278 1.14 thomas }
279 1.14 thomas
280 1.14 thomas /*
281 1.14 thomas * Enable memory and I/O on pci devices. Care about already enabled devices
282 1.14 thomas * (probabaly by the console driver).
283 1.14 thomas *
284 1.14 thomas * The idea behind the following code is:
285 1.14 thomas * We build a by sizes sorted list of the requirements of the different
286 1.14 thomas * pci devices. After that we choose the start addresses of that areas
287 1.14 thomas * in such a way that they are placed as closed as possible together.
288 1.14 thomas */
289 1.14 thomas static void
290 1.14 thomas enable_pci_devices()
291 1.14 thomas {
292 1.14 thomas PCI_MEMREG memlist;
293 1.14 thomas PCI_MEMREG iolist;
294 1.14 thomas struct pci_memreg *p, *q;
295 1.14 thomas int dev, reg, id, class;
296 1.14 thomas pcitag_t tag;
297 1.14 thomas pcireg_t csr, address, mask;
298 1.14 thomas pci_chipset_tag_t pc;
299 1.14 thomas int sizecnt, membase_1m;
300 1.14 thomas
301 1.14 thomas pc = 0;
302 1.14 thomas csr = 0;
303 1.14 thomas tag = 0;
304 1.14 thomas
305 1.14 thomas LIST_INIT(&memlist);
306 1.14 thomas LIST_INIT(&iolist);
307 1.14 thomas
308 1.14 thomas /*
309 1.14 thomas * first step: go through all devices and gather memory and I/O
310 1.14 thomas * sizes
311 1.14 thomas */
312 1.14 thomas for (dev = 0; dev < pci_bus_maxdevs(pc,0); dev++) {
313 1.14 thomas
314 1.14 thomas tag = pci_make_tag(pc, 0, dev, 0);
315 1.14 thomas id = pci_conf_read(pc, tag, PCI_ID_REG);
316 1.14 thomas if (id == 0 || id == 0xffffffff)
317 1.14 thomas continue;
318 1.14 thomas
319 1.14 thomas csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
320 1.14 thomas
321 1.14 thomas /*
322 1.14 thomas * special case: if a display card is found and memory is enabled
323 1.14 thomas * preserve 128k at 0xa0000 as vga memory.
324 1.18 leo * XXX: if a display card is found without being enabled, leave
325 1.18 leo * it alone! You will usually only create conflicts by enabeling
326 1.18 leo * it.
327 1.14 thomas */
328 1.14 thomas class = pci_conf_read(pc, tag, PCI_CLASS_REG);
329 1.14 thomas switch (PCI_CLASS(class)) {
330 1.14 thomas case PCI_CLASS_PREHISTORIC:
331 1.14 thomas case PCI_CLASS_DISPLAY:
332 1.18 leo if (csr & (PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE)) {
333 1.14 thomas p = (struct pci_memreg *)malloc(sizeof(struct pci_memreg),
334 1.14 thomas M_TEMP, M_WAITOK);
335 1.14 thomas memset(p, '\0', sizeof(struct pci_memreg));
336 1.14 thomas p->dev = dev;
337 1.14 thomas p->csr = csr;
338 1.14 thomas p->tag = tag;
339 1.14 thomas p->reg = 0; /* there is no register about this */
340 1.14 thomas p->size = 0x20000; /* 128kByte */
341 1.14 thomas p->mask = 0xfffe0000;
342 1.14 thomas p->address = 0xa0000;
343 1.14 thomas
344 1.14 thomas insert_into_list(&memlist, p);
345 1.18 leo }
346 1.18 leo else continue;
347 1.9 leo }
348 1.9 leo
349 1.14 thomas for (reg = PCI_MAPREG_START; reg < PCI_MAPREG_END; reg += 4) {
350 1.14 thomas
351 1.14 thomas address = pci_conf_read(pc, tag, reg);
352 1.14 thomas pci_conf_write(pc, tag, reg, 0xffffffff);
353 1.14 thomas mask = pci_conf_read(pc, tag, reg);
354 1.14 thomas pci_conf_write(pc, tag, reg, address);
355 1.14 thomas if (mask == 0)
356 1.14 thomas continue; /* Register unused */
357 1.14 thomas
358 1.14 thomas p = (struct pci_memreg *)malloc(sizeof(struct pci_memreg),
359 1.14 thomas M_TEMP, M_WAITOK);
360 1.14 thomas memset(p, '\0', sizeof(struct pci_memreg));
361 1.14 thomas p->dev = dev;
362 1.14 thomas p->csr = csr;
363 1.14 thomas p->tag = tag;
364 1.14 thomas p->reg = reg;
365 1.14 thomas p->mask = mask;
366 1.14 thomas p->address = 0;
367 1.14 thomas
368 1.14 thomas if (mask & PCI_MAPREG_TYPE_IO) {
369 1.14 thomas p->size = PCI_MAPREG_IO_SIZE(mask);
370 1.14 thomas
371 1.14 thomas /*
372 1.20 thomas * Align IO if necessary
373 1.20 thomas */
374 1.20 thomas if (p->size < PCI_MAPREG_IO_SIZE(PCI_MACHDEP_IO_ALIGN_MASK)) {
375 1.20 thomas p->mask = PCI_MACHDEP_IO_ALIGN_MASK;
376 1.20 thomas p->size = PCI_MAPREG_IO_SIZE(p->mask);
377 1.20 thomas }
378 1.20 thomas
379 1.20 thomas /*
380 1.14 thomas * if I/O is already enabled (probably by the console driver)
381 1.14 thomas * save the address in order to take care about it later.
382 1.14 thomas */
383 1.14 thomas if (csr & PCI_COMMAND_IO_ENABLE)
384 1.14 thomas p->address = address;
385 1.14 thomas
386 1.14 thomas insert_into_list(&iolist, p);
387 1.14 thomas } else {
388 1.14 thomas p->size = PCI_MAPREG_MEM_SIZE(mask);
389 1.14 thomas
390 1.14 thomas /*
391 1.20 thomas * Align memory if necessary
392 1.20 thomas */
393 1.20 thomas if (p->size < PCI_MAPREG_IO_SIZE(PCI_MACHDEP_MEM_ALIGN_MASK)) {
394 1.20 thomas p->mask = PCI_MACHDEP_MEM_ALIGN_MASK;
395 1.20 thomas p->size = PCI_MAPREG_MEM_SIZE(p->mask);
396 1.20 thomas }
397 1.20 thomas
398 1.20 thomas /*
399 1.14 thomas * if memory is already enabled (probably by the console driver)
400 1.14 thomas * save the address in order to take care about it later.
401 1.14 thomas */
402 1.14 thomas if (csr & PCI_COMMAND_MEM_ENABLE)
403 1.14 thomas p->address = address;
404 1.14 thomas
405 1.14 thomas insert_into_list(&memlist, p);
406 1.9 leo
407 1.14 thomas if (PCI_MAPREG_MEM_TYPE(mask) == PCI_MAPREG_MEM_TYPE_64BIT)
408 1.14 thomas reg++;
409 1.14 thomas }
410 1.14 thomas }
411 1.9 leo
412 1.14 thomas /*
413 1.14 thomas * Both interrupt pin & line are set to the device (== slot)
414 1.14 thomas * number. This makes sense on the atari because the
415 1.14 thomas * individual slots are hard-wired to a specific MFP-pin.
416 1.14 thomas */
417 1.19 leo csr = (DEV2SLOT(dev) << PCI_INTERRUPT_PIN_SHIFT);
418 1.19 leo csr |= (DEV2SLOT(dev) << PCI_INTERRUPT_LINE_SHIFT);
419 1.14 thomas pci_conf_write(pc, tag, PCI_INTERRUPT_REG, csr);
420 1.14 thomas }
421 1.14 thomas
422 1.14 thomas /*
423 1.14 thomas * second step: calculate the memory and I/O adresses beginning from
424 1.14 thomas * PCI_MEM_START and PCI_IO_START. Care about already mapped areas.
425 1.14 thomas *
426 1.25 leo * begin with memory list
427 1.14 thomas */
428 1.14 thomas
429 1.14 thomas address = PCI_MEM_START;
430 1.14 thomas sizecnt = 0;
431 1.14 thomas membase_1m = 0;
432 1.14 thomas p = LIST_FIRST(&memlist);
433 1.14 thomas while (p != NULL) {
434 1.14 thomas if (!(p->csr & PCI_COMMAND_MEM_ENABLE)) {
435 1.14 thomas if (PCI_MAPREG_MEM_TYPE(p->mask) == PCI_MAPREG_MEM_TYPE_32BIT_1M) {
436 1.14 thomas if (p->size > membase_1m)
437 1.14 thomas membase_1m = p->size;
438 1.14 thomas do {
439 1.14 thomas p->address = membase_1m;
440 1.14 thomas membase_1m += p->size;
441 1.14 thomas } while (overlap_pci_areas(LIST_FIRST(&memlist), p, p->address,
442 1.14 thomas p->size, PCI_COMMAND_MEM_ENABLE));
443 1.14 thomas if (membase_1m > 0x00100000) {
444 1.14 thomas /*
445 1.14 thomas * Should we panic here?
446 1.14 thomas */
447 1.14 thomas printf("\npcibus0: dev %d reg %d: memory not configured",
448 1.14 thomas p->dev, p->reg);
449 1.14 thomas p->reg = 0;
450 1.9 leo }
451 1.14 thomas } else {
452 1.9 leo
453 1.14 thomas if (sizecnt && (p->size > sizecnt))
454 1.14 thomas sizecnt = ((p->size + sizecnt) & p->mask) &
455 1.14 thomas PCI_MAPREG_MEM_ADDR_MASK;
456 1.14 thomas if (sizecnt > address) {
457 1.14 thomas address = sizecnt;
458 1.14 thomas sizecnt = 0;
459 1.14 thomas }
460 1.9 leo
461 1.14 thomas do {
462 1.14 thomas p->address = address + sizecnt;
463 1.14 thomas sizecnt += p->size;
464 1.14 thomas } while (overlap_pci_areas(LIST_FIRST(&memlist), p, p->address,
465 1.14 thomas p->size, PCI_COMMAND_MEM_ENABLE));
466 1.14 thomas
467 1.14 thomas if ((address + sizecnt) > PCI_MEM_END) {
468 1.14 thomas /*
469 1.14 thomas * Should we panic here?
470 1.14 thomas */
471 1.14 thomas printf("\npcibus0: dev %d reg %d: memory not configured",
472 1.14 thomas p->dev, p->reg);
473 1.14 thomas p->reg = 0;
474 1.14 thomas }
475 1.14 thomas }
476 1.14 thomas if (p->reg > 0) {
477 1.14 thomas pci_conf_write(pc, p->tag, p->reg, p->address);
478 1.14 thomas csr = pci_conf_read(pc, p->tag, PCI_COMMAND_STATUS_REG);
479 1.14 thomas csr |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE;
480 1.14 thomas pci_conf_write(pc, p->tag, PCI_COMMAND_STATUS_REG, csr);
481 1.20 thomas p->csr = csr;
482 1.14 thomas }
483 1.14 thomas }
484 1.14 thomas p = LIST_NEXT(p, link);
485 1.14 thomas }
486 1.9 leo
487 1.14 thomas /*
488 1.14 thomas * now the I/O list
489 1.14 thomas */
490 1.14 thomas
491 1.14 thomas address = PCI_IO_START;
492 1.14 thomas sizecnt = 0;
493 1.14 thomas p = LIST_FIRST(&iolist);
494 1.14 thomas while (p != NULL) {
495 1.14 thomas if (!(p->csr & PCI_COMMAND_IO_ENABLE)) {
496 1.14 thomas
497 1.14 thomas if (sizecnt && (p->size > sizecnt))
498 1.14 thomas sizecnt = ((p->size + sizecnt) & p->mask) &
499 1.14 thomas PCI_MAPREG_IO_ADDR_MASK;
500 1.14 thomas if (sizecnt > address) {
501 1.14 thomas address = sizecnt;
502 1.14 thomas sizecnt = 0;
503 1.14 thomas }
504 1.14 thomas
505 1.14 thomas do {
506 1.14 thomas p->address = address + sizecnt;
507 1.14 thomas sizecnt += p->size;
508 1.14 thomas } while (overlap_pci_areas(LIST_FIRST(&iolist), p, p->address,
509 1.14 thomas p->size, PCI_COMMAND_IO_ENABLE));
510 1.9 leo
511 1.14 thomas if ((address + sizecnt) > PCI_IO_END) {
512 1.9 leo /*
513 1.14 thomas * Should we panic here?
514 1.9 leo */
515 1.14 thomas printf("\npcibus0: dev %d reg %d: io not configured",
516 1.14 thomas p->dev, p->reg);
517 1.14 thomas } else {
518 1.14 thomas pci_conf_write(pc, p->tag, p->reg, p->address);
519 1.14 thomas csr = pci_conf_read(pc, p->tag, PCI_COMMAND_STATUS_REG);
520 1.14 thomas csr |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE;
521 1.14 thomas pci_conf_write(pc, p->tag, PCI_COMMAND_STATUS_REG, csr);
522 1.20 thomas p->csr = csr;
523 1.14 thomas }
524 1.9 leo }
525 1.14 thomas p = LIST_NEXT(p, link);
526 1.14 thomas }
527 1.14 thomas
528 1.14 thomas #ifdef DEBUG_PCI_MACHDEP
529 1.14 thomas printf("\nI/O List:\n");
530 1.14 thomas p = LIST_FIRST(&iolist);
531 1.14 thomas
532 1.14 thomas while (p != NULL) {
533 1.14 thomas printf("\ndev: %d, reg: 0x%02x, size: 0x%08x, addr: 0x%08x", p->dev,
534 1.14 thomas p->reg, p->size, p->address);
535 1.14 thomas p = LIST_NEXT(p, link);
536 1.14 thomas }
537 1.14 thomas printf("\nMemlist:");
538 1.14 thomas p = LIST_FIRST(&memlist);
539 1.14 thomas
540 1.14 thomas while (p != NULL) {
541 1.14 thomas printf("\ndev: %d, reg: 0x%02x, size: 0x%08x, addr: 0x%08x", p->dev,
542 1.14 thomas p->reg, p->size, p->address);
543 1.14 thomas p = LIST_NEXT(p, link);
544 1.14 thomas }
545 1.14 thomas #endif
546 1.14 thomas
547 1.14 thomas /*
548 1.14 thomas * Free the lists
549 1.14 thomas */
550 1.14 thomas p = LIST_FIRST(&iolist);
551 1.14 thomas while (p != NULL) {
552 1.14 thomas q = p;
553 1.14 thomas LIST_REMOVE(q, link);
554 1.14 thomas free(p, M_WAITOK);
555 1.14 thomas p = LIST_FIRST(&iolist);
556 1.14 thomas }
557 1.14 thomas p = LIST_FIRST(&memlist);
558 1.14 thomas while (p != NULL) {
559 1.14 thomas q = p;
560 1.14 thomas LIST_REMOVE(q, link);
561 1.14 thomas free(p, M_WAITOK);
562 1.14 thomas p = LIST_FIRST(&memlist);
563 1.14 thomas }
564 1.9 leo }
565 1.9 leo
566 1.9 leo /*
567 1.1 leo * Atari_init.c maps the config areas NBPG bytes apart....
568 1.1 leo */
569 1.1 leo static int pci_config_offset(tag)
570 1.1 leo pcitag_t tag;
571 1.1 leo {
572 1.1 leo int device;
573 1.1 leo
574 1.1 leo device = (tag >> 11) & 0x1f;
575 1.1 leo return(device * NBPG);
576 1.1 leo }
577 1.1 leo
578 1.1 leo int
579 1.1 leo pci_bus_maxdevs(pc, busno)
580 1.1 leo pci_chipset_tag_t pc;
581 1.1 leo int busno;
582 1.1 leo {
583 1.1 leo return (4);
584 1.1 leo }
585 1.1 leo
586 1.1 leo pcitag_t
587 1.1 leo pci_make_tag(pc, bus, device, function)
588 1.1 leo pci_chipset_tag_t pc;
589 1.1 leo int bus, device, function;
590 1.1 leo {
591 1.1 leo return ((bus << 16) | (device << 11) | (function << 8));
592 1.1 leo }
593 1.1 leo
594 1.1 leo pcireg_t
595 1.1 leo pci_conf_read(pc, tag, reg)
596 1.1 leo pci_chipset_tag_t pc;
597 1.1 leo pcitag_t tag;
598 1.1 leo int reg;
599 1.1 leo {
600 1.1 leo u_long data;
601 1.1 leo
602 1.1 leo data = *(u_long *)(pci_conf_addr + pci_config_offset(tag) + reg);
603 1.9 leo return (bswap32(data));
604 1.1 leo }
605 1.1 leo
606 1.1 leo void
607 1.1 leo pci_conf_write(pc, tag, reg, data)
608 1.1 leo pci_chipset_tag_t pc;
609 1.1 leo pcitag_t tag;
610 1.1 leo int reg;
611 1.1 leo pcireg_t data;
612 1.1 leo {
613 1.9 leo *((u_long *)(pci_conf_addr + pci_config_offset(tag) + reg))
614 1.9 leo = bswap32(data);
615 1.1 leo }
616 1.1 leo
617 1.1 leo int
618 1.1 leo pci_intr_map(pc, intrtag, pin, line, ihp)
619 1.1 leo pci_chipset_tag_t pc;
620 1.1 leo pcitag_t intrtag;
621 1.1 leo int pin, line;
622 1.1 leo pci_intr_handle_t *ihp;
623 1.1 leo {
624 1.9 leo /*
625 1.9 leo * According to the PCI-spec, 255 means `unknown' or `no connection'.
626 1.9 leo * Interpret this as 'no interrupt assigned'.
627 1.9 leo */
628 1.9 leo if (line == 255) {
629 1.9 leo *ihp = -1;
630 1.9 leo return 1;
631 1.9 leo }
632 1.9 leo
633 1.9 leo /*
634 1.9 leo * Values are pretty useless because the on the Hades all interrupt
635 1.9 leo * lines for a card are tied together and hardwired to the TT-MFP
636 1.9 leo * I/O port.
637 1.9 leo */
638 1.9 leo *ihp = line;
639 1.9 leo return 0;
640 1.1 leo }
641 1.1 leo
642 1.1 leo const char *
643 1.1 leo pci_intr_string(pc, ih)
644 1.1 leo pci_chipset_tag_t pc;
645 1.1 leo pci_intr_handle_t ih;
646 1.1 leo {
647 1.1 leo static char irqstr[8]; /* 4 + 2 + NULL + sanity */
648 1.1 leo
649 1.9 leo if (ih == -1)
650 1.1 leo panic("pci_intr_string: bogus handle 0x%x\n", ih);
651 1.1 leo
652 1.3 christos sprintf(irqstr, "irq %d", ih);
653 1.1 leo return (irqstr);
654 1.1 leo
655 1.22 cgd }
656 1.22 cgd
657 1.22 cgd const struct evcnt *
658 1.22 cgd pci_intr_evcnt(pc, ih)
659 1.22 cgd pci_chipset_tag_t pc;
660 1.22 cgd pci_intr_handle_t ih;
661 1.22 cgd {
662 1.22 cgd
663 1.22 cgd /* XXX for now, no evcnt parent reported */
664 1.22 cgd return NULL;
665 1.1 leo }
666 1.1 leo
667 1.9 leo /*
668 1.9 leo * The interrupt stuff is rather ugly. On the Hades, all interrupt lines
669 1.9 leo * for a slot are wired together and connected to IO 0,1,2 or 5 (slots:
670 1.9 leo * (0-3) on the TT-MFP. The Pci-config code initializes the irq. number
671 1.9 leo * to the slot position.
672 1.9 leo */
673 1.9 leo static pci_intr_info_t iinfo[4] = { { -1 }, { -1 }, { -1 }, { -1 } };
674 1.9 leo
675 1.9 leo static int iifun __P((int, int));
676 1.9 leo
677 1.9 leo static int
678 1.9 leo iifun(slot, sr)
679 1.9 leo int slot;
680 1.9 leo int sr;
681 1.9 leo {
682 1.9 leo pci_intr_info_t *iinfo_p;
683 1.9 leo int s;
684 1.9 leo
685 1.9 leo iinfo_p = &iinfo[slot];
686 1.9 leo
687 1.9 leo /*
688 1.9 leo * Disable the interrupts
689 1.9 leo */
690 1.9 leo MFP2->mf_imrb &= ~iinfo_p->imask;
691 1.9 leo
692 1.12 leo if ((sr & PSL_IPL) >= (iinfo_p->ipl & PSL_IPL)) {
693 1.9 leo /*
694 1.9 leo * We're running at a too high priority now.
695 1.9 leo */
696 1.9 leo add_sicallback((si_farg)iifun, (void*)slot, 0);
697 1.9 leo }
698 1.9 leo else {
699 1.9 leo s = splx(iinfo_p->ipl);
700 1.9 leo (void) (iinfo_p->ifunc)(iinfo_p->iarg);
701 1.9 leo splx(s);
702 1.9 leo
703 1.9 leo /*
704 1.9 leo * Re-enable interrupts after handling
705 1.9 leo */
706 1.9 leo MFP2->mf_imrb |= iinfo_p->imask;
707 1.9 leo }
708 1.9 leo return 1;
709 1.9 leo }
710 1.9 leo
711 1.1 leo void *
712 1.9 leo pci_intr_establish(pc, ih, level, ih_fun, ih_arg)
713 1.9 leo pci_chipset_tag_t pc;
714 1.9 leo pci_intr_handle_t ih;
715 1.9 leo int level;
716 1.9 leo int (*ih_fun) __P((void *));
717 1.9 leo void *ih_arg;
718 1.9 leo {
719 1.9 leo pci_intr_info_t *iinfo_p;
720 1.9 leo struct intrhand *ihand;
721 1.9 leo int slot;
722 1.9 leo
723 1.9 leo slot = ih;
724 1.9 leo iinfo_p = &iinfo[slot];
725 1.9 leo
726 1.9 leo if (iinfo_p->ipl > 0)
727 1.9 leo panic("pci_intr_establish: interrupt was already established\n");
728 1.9 leo
729 1.9 leo ihand = intr_establish((slot == 3) ? 23 : 16 + slot, USER_VEC, 0,
730 1.9 leo (hw_ifun_t)iifun, (void *)slot);
731 1.9 leo if (ihand != NULL) {
732 1.9 leo iinfo_p->ipl = level;
733 1.9 leo iinfo_p->imask = (slot == 3) ? 0x80 : (0x01 << slot);
734 1.9 leo iinfo_p->ifunc = ih_fun;
735 1.9 leo iinfo_p->iarg = ih_arg;
736 1.9 leo iinfo_p->ihand = ihand;
737 1.9 leo
738 1.9 leo /*
739 1.9 leo * Enable (unmask) the interrupt
740 1.9 leo */
741 1.9 leo MFP2->mf_imrb |= iinfo_p->imask;
742 1.9 leo MFP2->mf_ierb |= iinfo_p->imask;
743 1.9 leo return(iinfo_p);
744 1.9 leo }
745 1.1 leo return NULL;
746 1.1 leo }
747 1.1 leo
748 1.1 leo void
749 1.1 leo pci_intr_disestablish(pc, cookie)
750 1.1 leo pci_chipset_tag_t pc;
751 1.1 leo void *cookie;
752 1.1 leo {
753 1.9 leo pci_intr_info_t *iinfo_p = (pci_intr_info_t *)cookie;
754 1.9 leo
755 1.9 leo if (iinfo->ipl < 0)
756 1.9 leo panic("pci_intr_disestablish: interrupt was not established\n");
757 1.9 leo
758 1.9 leo MFP2->mf_imrb &= ~iinfo->imask;
759 1.9 leo MFP2->mf_ierb &= ~iinfo->imask;
760 1.9 leo (void) intr_disestablish(iinfo_p->ihand);
761 1.9 leo iinfo_p->ipl = -1;
762 1.1 leo }
763