pci_machdep.c revision 1.32 1 1.32 leo /* $NetBSD: pci_machdep.c,v 1.32 2001/05/28 07:22:37 leo Exp $ */
2 1.1 leo
3 1.1 leo /*
4 1.1 leo * Copyright (c) 1996 Leo Weppelman. All rights reserved.
5 1.7 cgd * Copyright (c) 1996, 1997 Christopher G. Demetriou. All rights reserved.
6 1.13 mycroft * Copyright (c) 1994 Charles M. Hannum. All rights reserved.
7 1.1 leo *
8 1.1 leo * Redistribution and use in source and binary forms, with or without
9 1.1 leo * modification, are permitted provided that the following conditions
10 1.1 leo * are met:
11 1.1 leo * 1. Redistributions of source code must retain the above copyright
12 1.1 leo * notice, this list of conditions and the following disclaimer.
13 1.1 leo * 2. Redistributions in binary form must reproduce the above copyright
14 1.1 leo * notice, this list of conditions and the following disclaimer in the
15 1.1 leo * documentation and/or other materials provided with the distribution.
16 1.1 leo * 3. All advertising materials mentioning features or use of this software
17 1.1 leo * must display the following acknowledgement:
18 1.13 mycroft * This product includes software developed by Charles M. Hannum.
19 1.1 leo * 4. The name of the author may not be used to endorse or promote products
20 1.1 leo * derived from this software without specific prior written permission.
21 1.1 leo *
22 1.1 leo * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 1.1 leo * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 1.1 leo * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 1.1 leo * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 1.1 leo * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 1.1 leo * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 1.1 leo * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 1.1 leo * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 1.1 leo * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 1.1 leo * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 1.1 leo */
33 1.1 leo
34 1.31 leo #include "opt_mbtype.h"
35 1.1 leo #include <sys/types.h>
36 1.1 leo #include <sys/param.h>
37 1.1 leo #include <sys/time.h>
38 1.1 leo #include <sys/systm.h>
39 1.1 leo #include <sys/errno.h>
40 1.1 leo #include <sys/device.h>
41 1.14 thomas #include <sys/malloc.h>
42 1.1 leo
43 1.30 leo #define _ATARI_BUS_DMA_PRIVATE
44 1.30 leo #include <machine/bus.h>
45 1.1 leo
46 1.1 leo #include <dev/pci/pcivar.h>
47 1.1 leo #include <dev/pci/pcireg.h>
48 1.1 leo
49 1.30 leo #include <uvm/uvm_extern.h>
50 1.30 leo
51 1.1 leo #include <machine/cpu.h>
52 1.1 leo #include <machine/iomap.h>
53 1.9 leo #include <machine/mfp.h>
54 1.10 leo
55 1.1 leo #include <atari/atari/device.h>
56 1.17 leo #include <atari/pci/pci_vga.h>
57 1.1 leo
58 1.9 leo /*
59 1.14 thomas * Sizes of pci memory and I/O area.
60 1.9 leo */
61 1.14 thomas #define PCI_MEM_END 0x10000000 /* 256 MByte */
62 1.14 thomas #define PCI_IO_END 0x10000000 /* 256 MByte */
63 1.14 thomas
64 1.14 thomas /*
65 1.14 thomas * We preserve some space at the begin of the pci area for 32BIT_1M
66 1.14 thomas * devices and standard vga.
67 1.14 thomas */
68 1.14 thomas #define PCI_MEM_START 0x00100000 /* 1 MByte */
69 1.15 thomas #define PCI_IO_START 0x00004000 /* 16 kByte (some PCI cards allow only
70 1.25 leo I/O addresses up to 0xffff) */
71 1.20 thomas
72 1.20 thomas /*
73 1.20 thomas * PCI memory and IO should be aligned acording to this masks
74 1.20 thomas */
75 1.20 thomas #define PCI_MACHDEP_IO_ALIGN_MASK 0xffffff00
76 1.20 thomas #define PCI_MACHDEP_MEM_ALIGN_MASK 0xfffff000
77 1.20 thomas
78 1.19 leo /*
79 1.19 leo * Convert a PCI 'device' number to a slot number.
80 1.19 leo */
81 1.19 leo #define DEV2SLOT(dev) (3 - dev)
82 1.14 thomas
83 1.14 thomas /*
84 1.14 thomas * Struct to hold the memory and I/O datas of the pci devices
85 1.14 thomas */
86 1.14 thomas struct pci_memreg {
87 1.14 thomas LIST_ENTRY(pci_memreg) link;
88 1.14 thomas int dev;
89 1.14 thomas pcitag_t tag;
90 1.14 thomas pcireg_t reg, address, mask;
91 1.14 thomas u_int32_t size;
92 1.14 thomas u_int32_t csr;
93 1.14 thomas };
94 1.14 thomas
95 1.14 thomas typedef LIST_HEAD(pci_memreg_head, pci_memreg) PCI_MEMREG;
96 1.9 leo
97 1.30 leo /*
98 1.30 leo * Entry points for PCI DMA. Use only the 'standard' functions.
99 1.30 leo */
100 1.30 leo int _bus_dmamap_create __P((bus_dma_tag_t, bus_size_t, int, bus_size_t,
101 1.30 leo bus_size_t, int, bus_dmamap_t *));
102 1.30 leo struct atari_bus_dma_tag pci_bus_dma_tag = {
103 1.30 leo 0,
104 1.31 leo #ifdef _ATARIHW_
105 1.31 leo 0x80000000, /* On the Hades, CPU memory starts here PCI-wise */
106 1.31 leo #else
107 1.31 leo 0,
108 1.31 leo #endif
109 1.30 leo _bus_dmamap_create,
110 1.30 leo _bus_dmamap_destroy,
111 1.30 leo _bus_dmamap_load,
112 1.30 leo _bus_dmamap_load_mbuf,
113 1.30 leo _bus_dmamap_load_uio,
114 1.30 leo _bus_dmamap_load_raw,
115 1.30 leo _bus_dmamap_unload,
116 1.30 leo _bus_dmamap_sync,
117 1.30 leo };
118 1.30 leo
119 1.1 leo int pcibusprint __P((void *auxp, const char *));
120 1.5 leo int pcibusmatch __P((struct device *, struct cfdata *, void *));
121 1.1 leo void pcibusattach __P((struct device *, struct device *, void *));
122 1.1 leo
123 1.14 thomas static void enable_pci_devices __P((void));
124 1.14 thomas static void insert_into_list __P((PCI_MEMREG *head, struct pci_memreg *elem));
125 1.14 thomas static int overlap_pci_areas __P((struct pci_memreg *p,
126 1.14 thomas struct pci_memreg *self, u_int addr, u_int size, u_int what));
127 1.1 leo
128 1.1 leo struct cfattach pcibus_ca = {
129 1.1 leo sizeof(struct device), pcibusmatch, pcibusattach
130 1.1 leo };
131 1.1 leo
132 1.27 leo /*
133 1.27 leo * We need some static storage to probe pci-busses for VGA cards during
134 1.27 leo * early console init.
135 1.27 leo */
136 1.27 leo static struct atari_bus_space bs_storage[2]; /* 1 iot, 1 memt */
137 1.27 leo
138 1.1 leo int
139 1.5 leo pcibusmatch(pdp, cfp, auxp)
140 1.1 leo struct device *pdp;
141 1.5 leo struct cfdata *cfp;
142 1.5 leo void *auxp;
143 1.1 leo {
144 1.26 leo static int nmatched = 0;
145 1.26 leo
146 1.26 leo if (strcmp((char *)auxp, "pcibus"))
147 1.26 leo return (0); /* Wrong number... */
148 1.26 leo
149 1.27 leo if(atari_realconfig == 0)
150 1.27 leo return (1);
151 1.27 leo
152 1.31 leo if (machineid & (ATARI_HADES|ATARI_MILAN)) {
153 1.26 leo /*
154 1.31 leo * Both Hades and Milan have only one pci bus
155 1.26 leo */
156 1.26 leo if (nmatched)
157 1.26 leo return (0);
158 1.26 leo nmatched++;
159 1.26 leo return (1);
160 1.26 leo }
161 1.26 leo return (0);
162 1.1 leo }
163 1.1 leo
164 1.1 leo void
165 1.1 leo pcibusattach(pdp, dp, auxp)
166 1.1 leo struct device *pdp, *dp;
167 1.1 leo void *auxp;
168 1.1 leo {
169 1.1 leo struct pcibus_attach_args pba;
170 1.1 leo
171 1.1 leo pba.pba_busname = "pci";
172 1.4 leo pba.pba_pc = NULL;
173 1.1 leo pba.pba_bus = 0;
174 1.7 cgd pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED;
175 1.30 leo pba.pba_dmat = &pci_bus_dma_tag;
176 1.27 leo pba.pba_iot = leb_alloc_bus_space_tag(&bs_storage[0]);
177 1.29 leo pba.pba_memt = leb_alloc_bus_space_tag(&bs_storage[1]);
178 1.11 leo if ((pba.pba_iot == NULL) || (pba.pba_memt == NULL)) {
179 1.11 leo printf("leb_alloc_bus_space_tag failed!\n");
180 1.11 leo return;
181 1.11 leo }
182 1.11 leo pba.pba_iot->base = PCI_IO_PHYS;
183 1.11 leo pba.pba_memt->base = PCI_MEM_PHYS;
184 1.6 leo
185 1.27 leo if (dp == NULL) {
186 1.27 leo /*
187 1.27 leo * Scan the bus for a VGA-card that we support. If we
188 1.27 leo * find one, try to initialize it to a 'standard' text
189 1.27 leo * mode (80x25).
190 1.27 leo */
191 1.32 leo check_for_vga(pba.pba_iot, pba.pba_memt);
192 1.27 leo return;
193 1.27 leo }
194 1.27 leo
195 1.27 leo enable_pci_devices();
196 1.27 leo
197 1.31 leo #if defined(_ATARIHW_)
198 1.9 leo MFP2->mf_aer &= ~(0x27); /* PCI interrupts: HIGH -> LOW */
199 1.31 leo #endif
200 1.9 leo
201 1.6 leo printf("\n");
202 1.1 leo
203 1.1 leo config_found(dp, &pba, pcibusprint);
204 1.1 leo }
205 1.1 leo
206 1.1 leo int
207 1.1 leo pcibusprint(auxp, name)
208 1.1 leo void *auxp;
209 1.1 leo const char *name;
210 1.1 leo {
211 1.1 leo if(name == NULL)
212 1.1 leo return(UNCONF);
213 1.1 leo return(QUIET);
214 1.1 leo }
215 1.1 leo
216 1.1 leo void
217 1.1 leo pci_attach_hook(parent, self, pba)
218 1.1 leo struct device *parent, *self;
219 1.1 leo struct pcibus_attach_args *pba;
220 1.1 leo {
221 1.1 leo }
222 1.1 leo
223 1.1 leo /*
224 1.9 leo * Initialize the PCI-bus. The Atari-BIOS does not do this, so....
225 1.14 thomas * We only disable all devices here. Memory and I/O enabling is done
226 1.14 thomas * later at pcibusattach.
227 1.9 leo */
228 1.9 leo void
229 1.9 leo init_pci_bus()
230 1.9 leo {
231 1.9 leo pci_chipset_tag_t pc = NULL; /* XXX */
232 1.9 leo pcitag_t tag;
233 1.14 thomas pcireg_t csr;
234 1.14 thomas int device, id, maxndevs;
235 1.9 leo
236 1.14 thomas tag = 0;
237 1.14 thomas id = 0;
238 1.9 leo
239 1.9 leo maxndevs = pci_bus_maxdevs(pc, 0);
240 1.9 leo
241 1.9 leo for (device = 0; device < maxndevs; device++) {
242 1.9 leo
243 1.9 leo tag = pci_make_tag(pc, 0, device, 0);
244 1.9 leo id = pci_conf_read(pc, tag, PCI_ID_REG);
245 1.9 leo if (id == 0 || id == 0xffffffff)
246 1.9 leo continue;
247 1.9 leo
248 1.14 thomas csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
249 1.14 thomas csr &= ~(PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_IO_ENABLE);
250 1.14 thomas csr &= ~PCI_COMMAND_MASTER_ENABLE;
251 1.14 thomas pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
252 1.14 thomas }
253 1.14 thomas }
254 1.14 thomas
255 1.14 thomas /*
256 1.14 thomas * insert a new element in an existing list that the ID's (size in struct
257 1.14 thomas * pci_memreg) are sorted.
258 1.14 thomas */
259 1.14 thomas static void
260 1.14 thomas insert_into_list(head, elem)
261 1.14 thomas PCI_MEMREG *head;
262 1.14 thomas struct pci_memreg *elem;
263 1.14 thomas {
264 1.14 thomas struct pci_memreg *p, *q;
265 1.14 thomas
266 1.14 thomas p = LIST_FIRST(head);
267 1.14 thomas q = NULL;
268 1.14 thomas
269 1.14 thomas for (; p != NULL && p->size < elem->size; q = p, p = LIST_NEXT(p, link));
270 1.14 thomas
271 1.14 thomas if (q == NULL) {
272 1.14 thomas LIST_INSERT_HEAD(head, elem, link);
273 1.14 thomas } else {
274 1.14 thomas LIST_INSERT_AFTER(q, elem, link);
275 1.14 thomas }
276 1.14 thomas }
277 1.14 thomas
278 1.14 thomas /*
279 1.14 thomas * Test if a new selected area overlaps with an already (probably preselected)
280 1.14 thomas * pci area.
281 1.14 thomas */
282 1.14 thomas static int
283 1.14 thomas overlap_pci_areas(p, self, addr, size, what)
284 1.14 thomas struct pci_memreg *p, *self;
285 1.14 thomas u_int addr, size, what;
286 1.14 thomas {
287 1.14 thomas struct pci_memreg *q;
288 1.14 thomas
289 1.14 thomas if (p == NULL)
290 1.14 thomas return 0;
291 1.14 thomas
292 1.14 thomas q = p;
293 1.14 thomas while (q != NULL) {
294 1.31 leo if ((q != self) && (q->csr & what)) {
295 1.31 leo if ((addr >= q->address) && (addr < (q->address + q->size))) {
296 1.14 thomas #ifdef DEBUG_PCI_MACHDEP
297 1.31 leo printf("\noverlap area dev %d reg 0x%02x with dev %d reg 0x%02x",
298 1.14 thomas self->dev, self->reg, q->dev, q->reg);
299 1.14 thomas #endif
300 1.31 leo return 1;
301 1.31 leo }
302 1.31 leo if ((q->address >= addr) && (q->address < (addr + size))) {
303 1.14 thomas #ifdef DEBUG_PCI_MACHDEP
304 1.31 leo printf("\noverlap area dev %d reg 0x%02x with dev %d reg 0x%02x",
305 1.14 thomas self->dev, self->reg, q->dev, q->reg);
306 1.14 thomas #endif
307 1.31 leo return 1;
308 1.14 thomas }
309 1.31 leo }
310 1.31 leo q = LIST_NEXT(q, link);
311 1.14 thomas }
312 1.14 thomas return 0;
313 1.14 thomas }
314 1.14 thomas
315 1.14 thomas /*
316 1.14 thomas * Enable memory and I/O on pci devices. Care about already enabled devices
317 1.14 thomas * (probabaly by the console driver).
318 1.14 thomas *
319 1.14 thomas * The idea behind the following code is:
320 1.14 thomas * We build a by sizes sorted list of the requirements of the different
321 1.14 thomas * pci devices. After that we choose the start addresses of that areas
322 1.14 thomas * in such a way that they are placed as closed as possible together.
323 1.14 thomas */
324 1.14 thomas static void
325 1.14 thomas enable_pci_devices()
326 1.14 thomas {
327 1.14 thomas PCI_MEMREG memlist;
328 1.14 thomas PCI_MEMREG iolist;
329 1.14 thomas struct pci_memreg *p, *q;
330 1.14 thomas int dev, reg, id, class;
331 1.14 thomas pcitag_t tag;
332 1.14 thomas pcireg_t csr, address, mask;
333 1.14 thomas pci_chipset_tag_t pc;
334 1.14 thomas int sizecnt, membase_1m;
335 1.14 thomas
336 1.14 thomas pc = 0;
337 1.14 thomas csr = 0;
338 1.14 thomas tag = 0;
339 1.14 thomas
340 1.14 thomas LIST_INIT(&memlist);
341 1.14 thomas LIST_INIT(&iolist);
342 1.14 thomas
343 1.14 thomas /*
344 1.14 thomas * first step: go through all devices and gather memory and I/O
345 1.14 thomas * sizes
346 1.14 thomas */
347 1.14 thomas for (dev = 0; dev < pci_bus_maxdevs(pc,0); dev++) {
348 1.14 thomas
349 1.14 thomas tag = pci_make_tag(pc, 0, dev, 0);
350 1.14 thomas id = pci_conf_read(pc, tag, PCI_ID_REG);
351 1.14 thomas if (id == 0 || id == 0xffffffff)
352 1.14 thomas continue;
353 1.14 thomas
354 1.14 thomas csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
355 1.14 thomas
356 1.14 thomas /*
357 1.14 thomas * special case: if a display card is found and memory is enabled
358 1.14 thomas * preserve 128k at 0xa0000 as vga memory.
359 1.18 leo * XXX: if a display card is found without being enabled, leave
360 1.18 leo * it alone! You will usually only create conflicts by enabeling
361 1.18 leo * it.
362 1.14 thomas */
363 1.14 thomas class = pci_conf_read(pc, tag, PCI_CLASS_REG);
364 1.14 thomas switch (PCI_CLASS(class)) {
365 1.14 thomas case PCI_CLASS_PREHISTORIC:
366 1.14 thomas case PCI_CLASS_DISPLAY:
367 1.18 leo if (csr & (PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE)) {
368 1.14 thomas p = (struct pci_memreg *)malloc(sizeof(struct pci_memreg),
369 1.14 thomas M_TEMP, M_WAITOK);
370 1.14 thomas memset(p, '\0', sizeof(struct pci_memreg));
371 1.14 thomas p->dev = dev;
372 1.14 thomas p->csr = csr;
373 1.14 thomas p->tag = tag;
374 1.14 thomas p->reg = 0; /* there is no register about this */
375 1.14 thomas p->size = 0x20000; /* 128kByte */
376 1.14 thomas p->mask = 0xfffe0000;
377 1.14 thomas p->address = 0xa0000;
378 1.14 thomas
379 1.14 thomas insert_into_list(&memlist, p);
380 1.18 leo }
381 1.18 leo else continue;
382 1.9 leo }
383 1.9 leo
384 1.14 thomas for (reg = PCI_MAPREG_START; reg < PCI_MAPREG_END; reg += 4) {
385 1.14 thomas
386 1.14 thomas address = pci_conf_read(pc, tag, reg);
387 1.14 thomas pci_conf_write(pc, tag, reg, 0xffffffff);
388 1.14 thomas mask = pci_conf_read(pc, tag, reg);
389 1.14 thomas pci_conf_write(pc, tag, reg, address);
390 1.14 thomas if (mask == 0)
391 1.14 thomas continue; /* Register unused */
392 1.14 thomas
393 1.14 thomas p = (struct pci_memreg *)malloc(sizeof(struct pci_memreg),
394 1.14 thomas M_TEMP, M_WAITOK);
395 1.14 thomas memset(p, '\0', sizeof(struct pci_memreg));
396 1.14 thomas p->dev = dev;
397 1.14 thomas p->csr = csr;
398 1.14 thomas p->tag = tag;
399 1.14 thomas p->reg = reg;
400 1.14 thomas p->mask = mask;
401 1.14 thomas p->address = 0;
402 1.14 thomas
403 1.14 thomas if (mask & PCI_MAPREG_TYPE_IO) {
404 1.14 thomas p->size = PCI_MAPREG_IO_SIZE(mask);
405 1.14 thomas
406 1.14 thomas /*
407 1.20 thomas * Align IO if necessary
408 1.20 thomas */
409 1.20 thomas if (p->size < PCI_MAPREG_IO_SIZE(PCI_MACHDEP_IO_ALIGN_MASK)) {
410 1.20 thomas p->mask = PCI_MACHDEP_IO_ALIGN_MASK;
411 1.20 thomas p->size = PCI_MAPREG_IO_SIZE(p->mask);
412 1.20 thomas }
413 1.20 thomas
414 1.20 thomas /*
415 1.14 thomas * if I/O is already enabled (probably by the console driver)
416 1.14 thomas * save the address in order to take care about it later.
417 1.14 thomas */
418 1.14 thomas if (csr & PCI_COMMAND_IO_ENABLE)
419 1.14 thomas p->address = address;
420 1.14 thomas
421 1.14 thomas insert_into_list(&iolist, p);
422 1.14 thomas } else {
423 1.14 thomas p->size = PCI_MAPREG_MEM_SIZE(mask);
424 1.14 thomas
425 1.14 thomas /*
426 1.20 thomas * Align memory if necessary
427 1.20 thomas */
428 1.20 thomas if (p->size < PCI_MAPREG_IO_SIZE(PCI_MACHDEP_MEM_ALIGN_MASK)) {
429 1.20 thomas p->mask = PCI_MACHDEP_MEM_ALIGN_MASK;
430 1.20 thomas p->size = PCI_MAPREG_MEM_SIZE(p->mask);
431 1.20 thomas }
432 1.20 thomas
433 1.20 thomas /*
434 1.14 thomas * if memory is already enabled (probably by the console driver)
435 1.14 thomas * save the address in order to take care about it later.
436 1.14 thomas */
437 1.14 thomas if (csr & PCI_COMMAND_MEM_ENABLE)
438 1.14 thomas p->address = address;
439 1.14 thomas
440 1.14 thomas insert_into_list(&memlist, p);
441 1.9 leo
442 1.14 thomas if (PCI_MAPREG_MEM_TYPE(mask) == PCI_MAPREG_MEM_TYPE_64BIT)
443 1.14 thomas reg++;
444 1.14 thomas }
445 1.14 thomas }
446 1.9 leo
447 1.14 thomas /*
448 1.14 thomas * Both interrupt pin & line are set to the device (== slot)
449 1.14 thomas * number. This makes sense on the atari because the
450 1.14 thomas * individual slots are hard-wired to a specific MFP-pin.
451 1.31 leo * XXX: This is _not_ true on the Milan.
452 1.14 thomas */
453 1.19 leo csr = (DEV2SLOT(dev) << PCI_INTERRUPT_PIN_SHIFT);
454 1.19 leo csr |= (DEV2SLOT(dev) << PCI_INTERRUPT_LINE_SHIFT);
455 1.14 thomas pci_conf_write(pc, tag, PCI_INTERRUPT_REG, csr);
456 1.14 thomas }
457 1.14 thomas
458 1.14 thomas /*
459 1.14 thomas * second step: calculate the memory and I/O adresses beginning from
460 1.14 thomas * PCI_MEM_START and PCI_IO_START. Care about already mapped areas.
461 1.14 thomas *
462 1.25 leo * begin with memory list
463 1.14 thomas */
464 1.14 thomas
465 1.14 thomas address = PCI_MEM_START;
466 1.14 thomas sizecnt = 0;
467 1.14 thomas membase_1m = 0;
468 1.14 thomas p = LIST_FIRST(&memlist);
469 1.14 thomas while (p != NULL) {
470 1.14 thomas if (!(p->csr & PCI_COMMAND_MEM_ENABLE)) {
471 1.14 thomas if (PCI_MAPREG_MEM_TYPE(p->mask) == PCI_MAPREG_MEM_TYPE_32BIT_1M) {
472 1.14 thomas if (p->size > membase_1m)
473 1.14 thomas membase_1m = p->size;
474 1.14 thomas do {
475 1.14 thomas p->address = membase_1m;
476 1.14 thomas membase_1m += p->size;
477 1.14 thomas } while (overlap_pci_areas(LIST_FIRST(&memlist), p, p->address,
478 1.14 thomas p->size, PCI_COMMAND_MEM_ENABLE));
479 1.14 thomas if (membase_1m > 0x00100000) {
480 1.14 thomas /*
481 1.14 thomas * Should we panic here?
482 1.14 thomas */
483 1.14 thomas printf("\npcibus0: dev %d reg %d: memory not configured",
484 1.14 thomas p->dev, p->reg);
485 1.14 thomas p->reg = 0;
486 1.9 leo }
487 1.14 thomas } else {
488 1.9 leo
489 1.14 thomas if (sizecnt && (p->size > sizecnt))
490 1.14 thomas sizecnt = ((p->size + sizecnt) & p->mask) &
491 1.14 thomas PCI_MAPREG_MEM_ADDR_MASK;
492 1.14 thomas if (sizecnt > address) {
493 1.14 thomas address = sizecnt;
494 1.14 thomas sizecnt = 0;
495 1.14 thomas }
496 1.9 leo
497 1.14 thomas do {
498 1.14 thomas p->address = address + sizecnt;
499 1.14 thomas sizecnt += p->size;
500 1.14 thomas } while (overlap_pci_areas(LIST_FIRST(&memlist), p, p->address,
501 1.14 thomas p->size, PCI_COMMAND_MEM_ENABLE));
502 1.14 thomas
503 1.14 thomas if ((address + sizecnt) > PCI_MEM_END) {
504 1.14 thomas /*
505 1.14 thomas * Should we panic here?
506 1.14 thomas */
507 1.14 thomas printf("\npcibus0: dev %d reg %d: memory not configured",
508 1.14 thomas p->dev, p->reg);
509 1.14 thomas p->reg = 0;
510 1.14 thomas }
511 1.14 thomas }
512 1.14 thomas if (p->reg > 0) {
513 1.14 thomas pci_conf_write(pc, p->tag, p->reg, p->address);
514 1.14 thomas csr = pci_conf_read(pc, p->tag, PCI_COMMAND_STATUS_REG);
515 1.14 thomas csr |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE;
516 1.14 thomas pci_conf_write(pc, p->tag, PCI_COMMAND_STATUS_REG, csr);
517 1.20 thomas p->csr = csr;
518 1.14 thomas }
519 1.14 thomas }
520 1.14 thomas p = LIST_NEXT(p, link);
521 1.14 thomas }
522 1.9 leo
523 1.14 thomas /*
524 1.14 thomas * now the I/O list
525 1.14 thomas */
526 1.14 thomas
527 1.14 thomas address = PCI_IO_START;
528 1.14 thomas sizecnt = 0;
529 1.14 thomas p = LIST_FIRST(&iolist);
530 1.14 thomas while (p != NULL) {
531 1.14 thomas if (!(p->csr & PCI_COMMAND_IO_ENABLE)) {
532 1.14 thomas
533 1.14 thomas if (sizecnt && (p->size > sizecnt))
534 1.14 thomas sizecnt = ((p->size + sizecnt) & p->mask) &
535 1.14 thomas PCI_MAPREG_IO_ADDR_MASK;
536 1.14 thomas if (sizecnt > address) {
537 1.14 thomas address = sizecnt;
538 1.14 thomas sizecnt = 0;
539 1.14 thomas }
540 1.14 thomas
541 1.14 thomas do {
542 1.14 thomas p->address = address + sizecnt;
543 1.14 thomas sizecnt += p->size;
544 1.14 thomas } while (overlap_pci_areas(LIST_FIRST(&iolist), p, p->address,
545 1.14 thomas p->size, PCI_COMMAND_IO_ENABLE));
546 1.9 leo
547 1.14 thomas if ((address + sizecnt) > PCI_IO_END) {
548 1.9 leo /*
549 1.14 thomas * Should we panic here?
550 1.9 leo */
551 1.14 thomas printf("\npcibus0: dev %d reg %d: io not configured",
552 1.14 thomas p->dev, p->reg);
553 1.14 thomas } else {
554 1.14 thomas pci_conf_write(pc, p->tag, p->reg, p->address);
555 1.14 thomas csr = pci_conf_read(pc, p->tag, PCI_COMMAND_STATUS_REG);
556 1.14 thomas csr |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE;
557 1.14 thomas pci_conf_write(pc, p->tag, PCI_COMMAND_STATUS_REG, csr);
558 1.20 thomas p->csr = csr;
559 1.14 thomas }
560 1.9 leo }
561 1.14 thomas p = LIST_NEXT(p, link);
562 1.14 thomas }
563 1.14 thomas
564 1.14 thomas #ifdef DEBUG_PCI_MACHDEP
565 1.14 thomas printf("\nI/O List:\n");
566 1.14 thomas p = LIST_FIRST(&iolist);
567 1.14 thomas
568 1.14 thomas while (p != NULL) {
569 1.14 thomas printf("\ndev: %d, reg: 0x%02x, size: 0x%08x, addr: 0x%08x", p->dev,
570 1.14 thomas p->reg, p->size, p->address);
571 1.14 thomas p = LIST_NEXT(p, link);
572 1.14 thomas }
573 1.14 thomas printf("\nMemlist:");
574 1.14 thomas p = LIST_FIRST(&memlist);
575 1.14 thomas
576 1.14 thomas while (p != NULL) {
577 1.14 thomas printf("\ndev: %d, reg: 0x%02x, size: 0x%08x, addr: 0x%08x", p->dev,
578 1.14 thomas p->reg, p->size, p->address);
579 1.14 thomas p = LIST_NEXT(p, link);
580 1.14 thomas }
581 1.14 thomas #endif
582 1.14 thomas
583 1.14 thomas /*
584 1.14 thomas * Free the lists
585 1.14 thomas */
586 1.14 thomas p = LIST_FIRST(&iolist);
587 1.14 thomas while (p != NULL) {
588 1.14 thomas q = p;
589 1.14 thomas LIST_REMOVE(q, link);
590 1.14 thomas free(p, M_WAITOK);
591 1.14 thomas p = LIST_FIRST(&iolist);
592 1.14 thomas }
593 1.14 thomas p = LIST_FIRST(&memlist);
594 1.14 thomas while (p != NULL) {
595 1.14 thomas q = p;
596 1.14 thomas LIST_REMOVE(q, link);
597 1.14 thomas free(p, M_WAITOK);
598 1.14 thomas p = LIST_FIRST(&memlist);
599 1.14 thomas }
600 1.9 leo }
601 1.9 leo
602 1.1 leo pcitag_t
603 1.1 leo pci_make_tag(pc, bus, device, function)
604 1.1 leo pci_chipset_tag_t pc;
605 1.1 leo int bus, device, function;
606 1.1 leo {
607 1.1 leo return ((bus << 16) | (device << 11) | (function << 8));
608 1.1 leo }
609 1.1 leo
610 1.1 leo int
611 1.28 sommerfe pci_intr_map(pa, ihp)
612 1.28 sommerfe struct pci_attach_args *pa;
613 1.1 leo pci_intr_handle_t *ihp;
614 1.1 leo {
615 1.28 sommerfe int line = pa->pa_intrline;
616 1.28 sommerfe
617 1.9 leo /*
618 1.9 leo * According to the PCI-spec, 255 means `unknown' or `no connection'.
619 1.9 leo * Interpret this as 'no interrupt assigned'.
620 1.9 leo */
621 1.9 leo if (line == 255) {
622 1.9 leo *ihp = -1;
623 1.9 leo return 1;
624 1.9 leo }
625 1.9 leo
626 1.9 leo /*
627 1.31 leo * Values are pretty useless on the Hades since all interrupt
628 1.31 leo * lines for a card are tied together and hardwired to a
629 1.31 leo * specific TT-MFP I/O port.
630 1.9 leo */
631 1.9 leo *ihp = line;
632 1.9 leo return 0;
633 1.1 leo }
634 1.1 leo
635 1.1 leo const char *
636 1.1 leo pci_intr_string(pc, ih)
637 1.1 leo pci_chipset_tag_t pc;
638 1.1 leo pci_intr_handle_t ih;
639 1.1 leo {
640 1.1 leo static char irqstr[8]; /* 4 + 2 + NULL + sanity */
641 1.1 leo
642 1.9 leo if (ih == -1)
643 1.1 leo panic("pci_intr_string: bogus handle 0x%x\n", ih);
644 1.1 leo
645 1.3 christos sprintf(irqstr, "irq %d", ih);
646 1.1 leo return (irqstr);
647 1.1 leo
648 1.22 cgd }
649 1.22 cgd
650 1.22 cgd const struct evcnt *
651 1.22 cgd pci_intr_evcnt(pc, ih)
652 1.22 cgd pci_chipset_tag_t pc;
653 1.22 cgd pci_intr_handle_t ih;
654 1.22 cgd {
655 1.22 cgd
656 1.22 cgd /* XXX for now, no evcnt parent reported */
657 1.22 cgd return NULL;
658 1.1 leo }
659