pci_machdep.c revision 1.15
1 /* $NetBSD: pci_machdep.c,v 1.15 1999/01/01 19:54:52 thomas Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Leo Weppelman. All rights reserved. 5 * Copyright (c) 1996, 1997 Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/types.h> 35 #include <sys/param.h> 36 #include <sys/time.h> 37 #include <sys/systm.h> 38 #include <sys/errno.h> 39 #include <sys/device.h> 40 #include <sys/malloc.h> 41 42 #include <vm/vm.h> 43 #include <vm/vm_kern.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcireg.h> 47 48 #include <machine/cpu.h> 49 #include <machine/iomap.h> 50 #include <machine/mfp.h> 51 #include <machine/bus.h> 52 53 #include <atari/atari/device.h> 54 55 /* 56 * Sizes of pci memory and I/O area. 57 */ 58 #define PCI_MEM_END 0x10000000 /* 256 MByte */ 59 #define PCI_IO_END 0x10000000 /* 256 MByte */ 60 61 /* 62 * We preserve some space at the begin of the pci area for 32BIT_1M 63 * devices and standard vga. 64 */ 65 #define PCI_MEM_START 0x00100000 /* 1 MByte */ 66 #define PCI_IO_START 0x00004000 /* 16 kByte (some PCI cards allow only 67 I/O addresses up to 0xffff) */ 68 69 /* 70 * Struct to hold the memory and I/O datas of the pci devices 71 */ 72 struct pci_memreg { 73 LIST_ENTRY(pci_memreg) link; 74 int dev; 75 pcitag_t tag; 76 pcireg_t reg, address, mask; 77 u_int32_t size; 78 u_int32_t csr; 79 }; 80 81 typedef LIST_HEAD(pci_memreg_head, pci_memreg) PCI_MEMREG; 82 83 int pcibusprint __P((void *auxp, const char *)); 84 int pcibusmatch __P((struct device *, struct cfdata *, void *)); 85 void pcibusattach __P((struct device *, struct device *, void *)); 86 87 static void enable_pci_devices __P((void)); 88 static void insert_into_list __P((PCI_MEMREG *head, struct pci_memreg *elem)); 89 static int overlap_pci_areas __P((struct pci_memreg *p, 90 struct pci_memreg *self, u_int addr, u_int size, u_int what)); 91 static int pci_config_offset __P((pcitag_t)); 92 93 struct cfattach pcibus_ca = { 94 sizeof(struct device), pcibusmatch, pcibusattach 95 }; 96 97 int 98 pcibusmatch(pdp, cfp, auxp) 99 struct device *pdp; 100 struct cfdata *cfp; 101 void *auxp; 102 { 103 if(atari_realconfig == 0) 104 return (0); 105 if (strcmp((char *)auxp, "pcibus") || cfp->cf_unit != 0) 106 return(0); 107 return(machineid & ATARI_HADES ? 1 : 0); 108 } 109 110 void 111 pcibusattach(pdp, dp, auxp) 112 struct device *pdp, *dp; 113 void *auxp; 114 { 115 struct pcibus_attach_args pba; 116 bus_space_tag_t leb_alloc_bus_space_tag __P((void)); 117 118 119 enable_pci_devices(); 120 121 pba.pba_busname = "pci"; 122 pba.pba_pc = NULL; 123 pba.pba_bus = 0; 124 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 125 pba.pba_dmat = BUS_PCI_DMA_TAG; 126 pba.pba_iot = leb_alloc_bus_space_tag(); 127 pba.pba_memt = leb_alloc_bus_space_tag(); 128 if ((pba.pba_iot == NULL) || (pba.pba_memt == NULL)) { 129 printf("leb_alloc_bus_space_tag failed!\n"); 130 return; 131 } 132 pba.pba_iot->base = PCI_IO_PHYS; 133 pba.pba_memt->base = PCI_MEM_PHYS; 134 135 MFP2->mf_aer &= ~(0x27); /* PCI interrupts: HIGH -> LOW */ 136 137 printf("\n"); 138 139 config_found(dp, &pba, pcibusprint); 140 } 141 142 int 143 pcibusprint(auxp, name) 144 void *auxp; 145 const char *name; 146 { 147 if(name == NULL) 148 return(UNCONF); 149 return(QUIET); 150 } 151 152 void 153 pci_attach_hook(parent, self, pba) 154 struct device *parent, *self; 155 struct pcibus_attach_args *pba; 156 { 157 } 158 159 /* 160 * Initialize the PCI-bus. The Atari-BIOS does not do this, so.... 161 * We only disable all devices here. Memory and I/O enabling is done 162 * later at pcibusattach. 163 */ 164 void 165 init_pci_bus() 166 { 167 pci_chipset_tag_t pc = NULL; /* XXX */ 168 pcitag_t tag; 169 pcireg_t csr; 170 int device, id, maxndevs; 171 172 tag = 0; 173 id = 0; 174 175 maxndevs = pci_bus_maxdevs(pc, 0); 176 177 for (device = 0; device < maxndevs; device++) { 178 179 tag = pci_make_tag(pc, 0, device, 0); 180 id = pci_conf_read(pc, tag, PCI_ID_REG); 181 if (id == 0 || id == 0xffffffff) 182 continue; 183 184 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 185 csr &= ~(PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_IO_ENABLE); 186 csr &= ~PCI_COMMAND_MASTER_ENABLE; 187 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 188 } 189 } 190 191 /* 192 * insert a new element in an existing list that the ID's (size in struct 193 * pci_memreg) are sorted. 194 */ 195 static void 196 insert_into_list(head, elem) 197 PCI_MEMREG *head; 198 struct pci_memreg *elem; 199 { 200 struct pci_memreg *p, *q; 201 202 p = LIST_FIRST(head); 203 q = NULL; 204 205 for (; p != NULL && p->size < elem->size; q = p, p = LIST_NEXT(p, link)); 206 207 if (q == NULL) { 208 LIST_INSERT_HEAD(head, elem, link); 209 } else { 210 LIST_INSERT_AFTER(q, elem, link); 211 } 212 } 213 214 /* 215 * Test if a new selected area overlaps with an already (probably preselected) 216 * pci area. 217 */ 218 static int 219 overlap_pci_areas(p, self, addr, size, what) 220 struct pci_memreg *p, *self; 221 u_int addr, size, what; 222 { 223 struct pci_memreg *q; 224 225 if (p == NULL) 226 return 0; 227 228 q = p; 229 while (q != NULL) { 230 if ((q != self) && (q->csr & what)) { 231 if ((addr >= q->address) && (addr < (q->address + q->size))) { 232 #ifdef DEBUG_PCI_MACHDEP 233 printf("\noverlap area dev %d reg 0x%02x with dev %d reg 0x%02x", 234 self->dev, self->reg, q->dev, q->reg); 235 #endif 236 return 1; 237 } 238 if ((q->address >= addr) && (q->address < (addr + size))) { 239 #ifdef DEBUG_PCI_MACHDEP 240 printf("\noverlap area dev %d reg 0x%02x with dev %d reg 0x%02x", 241 self->dev, self->reg, q->dev, q->reg); 242 #endif 243 return 1; 244 } 245 } 246 q = LIST_NEXT(q, link); 247 } 248 return 0; 249 } 250 251 /* 252 * Enable memory and I/O on pci devices. Care about already enabled devices 253 * (probabaly by the console driver). 254 * 255 * The idea behind the following code is: 256 * We build a by sizes sorted list of the requirements of the different 257 * pci devices. After that we choose the start addresses of that areas 258 * in such a way that they are placed as closed as possible together. 259 */ 260 static void 261 enable_pci_devices() 262 { 263 PCI_MEMREG memlist; 264 PCI_MEMREG iolist; 265 struct pci_memreg *p, *q; 266 int dev, reg, id, class; 267 pcitag_t tag; 268 pcireg_t csr, address, mask; 269 pci_chipset_tag_t pc; 270 int sizecnt, membase_1m; 271 272 pc = 0; 273 csr = 0; 274 tag = 0; 275 276 LIST_INIT(&memlist); 277 LIST_INIT(&iolist); 278 279 /* 280 * first step: go through all devices and gather memory and I/O 281 * sizes 282 */ 283 for (dev = 0; dev < pci_bus_maxdevs(pc,0); dev++) { 284 285 tag = pci_make_tag(pc, 0, dev, 0); 286 id = pci_conf_read(pc, tag, PCI_ID_REG); 287 if (id == 0 || id == 0xffffffff) 288 continue; 289 290 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 291 292 /* 293 * special case: if a display card is found and memory is enabled 294 * preserve 128k at 0xa0000 as vga memory. 295 */ 296 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 297 switch (PCI_CLASS(class)) { 298 case PCI_CLASS_PREHISTORIC: 299 case PCI_CLASS_DISPLAY: 300 if (csr & (PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE)) { 301 p = (struct pci_memreg *)malloc(sizeof(struct pci_memreg), 302 M_TEMP, M_WAITOK); 303 memset(p, '\0', sizeof(struct pci_memreg)); 304 p->dev = dev; 305 p->csr = csr; 306 p->tag = tag; 307 p->reg = 0; /* there is no register about this */ 308 p->size = 0x20000; /* 128kByte */ 309 p->mask = 0xfffe0000; 310 p->address = 0xa0000; 311 312 insert_into_list(&memlist, p); 313 } 314 } 315 316 for (reg = PCI_MAPREG_START; reg < PCI_MAPREG_END; reg += 4) { 317 318 address = pci_conf_read(pc, tag, reg); 319 pci_conf_write(pc, tag, reg, 0xffffffff); 320 mask = pci_conf_read(pc, tag, reg); 321 pci_conf_write(pc, tag, reg, address); 322 if (mask == 0) 323 continue; /* Register unused */ 324 325 p = (struct pci_memreg *)malloc(sizeof(struct pci_memreg), 326 M_TEMP, M_WAITOK); 327 memset(p, '\0', sizeof(struct pci_memreg)); 328 p->dev = dev; 329 p->csr = csr; 330 p->tag = tag; 331 p->reg = reg; 332 p->mask = mask; 333 p->address = 0; 334 335 if (mask & PCI_MAPREG_TYPE_IO) { 336 p->size = PCI_MAPREG_IO_SIZE(mask); 337 338 /* 339 * if I/O is already enabled (probably by the console driver) 340 * save the address in order to take care about it later. 341 */ 342 if (csr & PCI_COMMAND_IO_ENABLE) 343 p->address = address; 344 345 insert_into_list(&iolist, p); 346 } else { 347 p->size = PCI_MAPREG_MEM_SIZE(mask); 348 349 /* 350 * if memory is already enabled (probably by the console driver) 351 * save the address in order to take care about it later. 352 */ 353 if (csr & PCI_COMMAND_MEM_ENABLE) 354 p->address = address; 355 356 insert_into_list(&memlist, p); 357 358 if (PCI_MAPREG_MEM_TYPE(mask) == PCI_MAPREG_MEM_TYPE_64BIT) 359 reg++; 360 } 361 } 362 363 /* 364 * Both interrupt pin & line are set to the device (== slot) 365 * number. This makes sense on the atari because the 366 * individual slots are hard-wired to a specific MFP-pin. 367 */ 368 csr = (dev << PCI_INTERRUPT_PIN_SHIFT); 369 csr |= (dev << PCI_INTERRUPT_LINE_SHIFT); 370 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, csr); 371 } 372 373 /* 374 * second step: calculate the memory and I/O adresses beginning from 375 * PCI_MEM_START and PCI_IO_START. Care about already mapped areas. 376 * 377 * beginn with memory list 378 */ 379 380 address = PCI_MEM_START; 381 sizecnt = 0; 382 membase_1m = 0; 383 p = LIST_FIRST(&memlist); 384 while (p != NULL) { 385 if (!(p->csr & PCI_COMMAND_MEM_ENABLE)) { 386 if (PCI_MAPREG_MEM_TYPE(p->mask) == PCI_MAPREG_MEM_TYPE_32BIT_1M) { 387 if (p->size > membase_1m) 388 membase_1m = p->size; 389 do { 390 p->address = membase_1m; 391 membase_1m += p->size; 392 } while (overlap_pci_areas(LIST_FIRST(&memlist), p, p->address, 393 p->size, PCI_COMMAND_MEM_ENABLE)); 394 if (membase_1m > 0x00100000) { 395 /* 396 * Should we panic here? 397 */ 398 printf("\npcibus0: dev %d reg %d: memory not configured", 399 p->dev, p->reg); 400 p->reg = 0; 401 } 402 } else { 403 404 if (sizecnt && (p->size > sizecnt)) 405 sizecnt = ((p->size + sizecnt) & p->mask) & 406 PCI_MAPREG_MEM_ADDR_MASK; 407 if (sizecnt > address) { 408 address = sizecnt; 409 sizecnt = 0; 410 } 411 412 do { 413 p->address = address + sizecnt; 414 sizecnt += p->size; 415 } while (overlap_pci_areas(LIST_FIRST(&memlist), p, p->address, 416 p->size, PCI_COMMAND_MEM_ENABLE)); 417 418 if ((address + sizecnt) > PCI_MEM_END) { 419 /* 420 * Should we panic here? 421 */ 422 printf("\npcibus0: dev %d reg %d: memory not configured", 423 p->dev, p->reg); 424 p->reg = 0; 425 } 426 } 427 if (p->reg > 0) { 428 pci_conf_write(pc, p->tag, p->reg, p->address); 429 csr = pci_conf_read(pc, p->tag, PCI_COMMAND_STATUS_REG); 430 csr |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 431 pci_conf_write(pc, p->tag, PCI_COMMAND_STATUS_REG, csr); 432 } 433 } 434 p = LIST_NEXT(p, link); 435 } 436 437 /* 438 * now the I/O list 439 */ 440 441 address = PCI_IO_START; 442 sizecnt = 0; 443 p = LIST_FIRST(&iolist); 444 while (p != NULL) { 445 if (!(p->csr & PCI_COMMAND_IO_ENABLE)) { 446 447 if (sizecnt && (p->size > sizecnt)) 448 sizecnt = ((p->size + sizecnt) & p->mask) & 449 PCI_MAPREG_IO_ADDR_MASK; 450 if (sizecnt > address) { 451 address = sizecnt; 452 sizecnt = 0; 453 } 454 455 do { 456 p->address = address + sizecnt; 457 sizecnt += p->size; 458 } while (overlap_pci_areas(LIST_FIRST(&iolist), p, p->address, 459 p->size, PCI_COMMAND_IO_ENABLE)); 460 461 if ((address + sizecnt) > PCI_IO_END) { 462 /* 463 * Should we panic here? 464 */ 465 printf("\npcibus0: dev %d reg %d: io not configured", 466 p->dev, p->reg); 467 } else { 468 pci_conf_write(pc, p->tag, p->reg, p->address); 469 csr = pci_conf_read(pc, p->tag, PCI_COMMAND_STATUS_REG); 470 csr |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE; 471 pci_conf_write(pc, p->tag, PCI_COMMAND_STATUS_REG, csr); 472 } 473 } 474 p = LIST_NEXT(p, link); 475 } 476 477 #ifdef DEBUG_PCI_MACHDEP 478 printf("\nI/O List:\n"); 479 p = LIST_FIRST(&iolist); 480 481 while (p != NULL) { 482 printf("\ndev: %d, reg: 0x%02x, size: 0x%08x, addr: 0x%08x", p->dev, 483 p->reg, p->size, p->address); 484 p = LIST_NEXT(p, link); 485 } 486 printf("\nMemlist:"); 487 p = LIST_FIRST(&memlist); 488 489 while (p != NULL) { 490 printf("\ndev: %d, reg: 0x%02x, size: 0x%08x, addr: 0x%08x", p->dev, 491 p->reg, p->size, p->address); 492 p = LIST_NEXT(p, link); 493 } 494 #endif 495 496 /* 497 * Free the lists 498 */ 499 p = LIST_FIRST(&iolist); 500 while (p != NULL) { 501 q = p; 502 LIST_REMOVE(q, link); 503 free(p, M_WAITOK); 504 p = LIST_FIRST(&iolist); 505 } 506 p = LIST_FIRST(&memlist); 507 while (p != NULL) { 508 q = p; 509 LIST_REMOVE(q, link); 510 free(p, M_WAITOK); 511 p = LIST_FIRST(&memlist); 512 } 513 } 514 515 /* 516 * Atari_init.c maps the config areas NBPG bytes apart.... 517 */ 518 static int pci_config_offset(tag) 519 pcitag_t tag; 520 { 521 int device; 522 523 device = (tag >> 11) & 0x1f; 524 return(device * NBPG); 525 } 526 527 int 528 pci_bus_maxdevs(pc, busno) 529 pci_chipset_tag_t pc; 530 int busno; 531 { 532 return (4); 533 } 534 535 pcitag_t 536 pci_make_tag(pc, bus, device, function) 537 pci_chipset_tag_t pc; 538 int bus, device, function; 539 { 540 return ((bus << 16) | (device << 11) | (function << 8)); 541 } 542 543 pcireg_t 544 pci_conf_read(pc, tag, reg) 545 pci_chipset_tag_t pc; 546 pcitag_t tag; 547 int reg; 548 { 549 u_long data; 550 551 data = *(u_long *)(pci_conf_addr + pci_config_offset(tag) + reg); 552 return (bswap32(data)); 553 } 554 555 void 556 pci_conf_write(pc, tag, reg, data) 557 pci_chipset_tag_t pc; 558 pcitag_t tag; 559 int reg; 560 pcireg_t data; 561 { 562 *((u_long *)(pci_conf_addr + pci_config_offset(tag) + reg)) 563 = bswap32(data); 564 } 565 566 int 567 pci_intr_map(pc, intrtag, pin, line, ihp) 568 pci_chipset_tag_t pc; 569 pcitag_t intrtag; 570 int pin, line; 571 pci_intr_handle_t *ihp; 572 { 573 /* 574 * According to the PCI-spec, 255 means `unknown' or `no connection'. 575 * Interpret this as 'no interrupt assigned'. 576 */ 577 if (line == 255) { 578 *ihp = -1; 579 return 1; 580 } 581 582 /* 583 * Values are pretty useless because the on the Hades all interrupt 584 * lines for a card are tied together and hardwired to the TT-MFP 585 * I/O port. 586 */ 587 *ihp = line; 588 return 0; 589 } 590 591 const char * 592 pci_intr_string(pc, ih) 593 pci_chipset_tag_t pc; 594 pci_intr_handle_t ih; 595 { 596 static char irqstr[8]; /* 4 + 2 + NULL + sanity */ 597 598 if (ih == -1) 599 panic("pci_intr_string: bogus handle 0x%x\n", ih); 600 601 sprintf(irqstr, "irq %d", ih); 602 return (irqstr); 603 604 } 605 606 /* 607 * The interrupt stuff is rather ugly. On the Hades, all interrupt lines 608 * for a slot are wired together and connected to IO 0,1,2 or 5 (slots: 609 * (0-3) on the TT-MFP. The Pci-config code initializes the irq. number 610 * to the slot position. 611 */ 612 static pci_intr_info_t iinfo[4] = { { -1 }, { -1 }, { -1 }, { -1 } }; 613 614 static int iifun __P((int, int)); 615 616 static int 617 iifun(slot, sr) 618 int slot; 619 int sr; 620 { 621 pci_intr_info_t *iinfo_p; 622 int s; 623 624 iinfo_p = &iinfo[slot]; 625 626 /* 627 * Disable the interrupts 628 */ 629 MFP2->mf_imrb &= ~iinfo_p->imask; 630 631 if ((sr & PSL_IPL) >= (iinfo_p->ipl & PSL_IPL)) { 632 /* 633 * We're running at a too high priority now. 634 */ 635 add_sicallback((si_farg)iifun, (void*)slot, 0); 636 } 637 else { 638 s = splx(iinfo_p->ipl); 639 (void) (iinfo_p->ifunc)(iinfo_p->iarg); 640 splx(s); 641 642 /* 643 * Re-enable interrupts after handling 644 */ 645 MFP2->mf_imrb |= iinfo_p->imask; 646 } 647 return 1; 648 } 649 650 void * 651 pci_intr_establish(pc, ih, level, ih_fun, ih_arg) 652 pci_chipset_tag_t pc; 653 pci_intr_handle_t ih; 654 int level; 655 int (*ih_fun) __P((void *)); 656 void *ih_arg; 657 { 658 pci_intr_info_t *iinfo_p; 659 struct intrhand *ihand; 660 int slot; 661 662 slot = ih; 663 iinfo_p = &iinfo[slot]; 664 665 if (iinfo_p->ipl > 0) 666 panic("pci_intr_establish: interrupt was already established\n"); 667 668 ihand = intr_establish((slot == 3) ? 23 : 16 + slot, USER_VEC, 0, 669 (hw_ifun_t)iifun, (void *)slot); 670 if (ihand != NULL) { 671 iinfo_p->ipl = level; 672 iinfo_p->imask = (slot == 3) ? 0x80 : (0x01 << slot); 673 iinfo_p->ifunc = ih_fun; 674 iinfo_p->iarg = ih_arg; 675 iinfo_p->ihand = ihand; 676 677 /* 678 * Enable (unmask) the interrupt 679 */ 680 MFP2->mf_imrb |= iinfo_p->imask; 681 MFP2->mf_ierb |= iinfo_p->imask; 682 return(iinfo_p); 683 } 684 return NULL; 685 } 686 687 void 688 pci_intr_disestablish(pc, cookie) 689 pci_chipset_tag_t pc; 690 void *cookie; 691 { 692 pci_intr_info_t *iinfo_p = (pci_intr_info_t *)cookie; 693 694 if (iinfo->ipl < 0) 695 panic("pci_intr_disestablish: interrupt was not established\n"); 696 697 MFP2->mf_imrb &= ~iinfo->imask; 698 MFP2->mf_ierb &= ~iinfo->imask; 699 (void) intr_disestablish(iinfo_p->ihand); 700 iinfo_p->ipl = -1; 701 } 702
Indexes created Thu Sep 25 16:09:42 GMT 2025