pci_machdep.c revision 1.17
1 /* $NetBSD: pci_machdep.c,v 1.17 1999/03/15 15:47:22 leo Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Leo Weppelman. All rights reserved. 5 * Copyright (c) 1996, 1997 Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/types.h> 35 #include <sys/param.h> 36 #include <sys/time.h> 37 #include <sys/systm.h> 38 #include <sys/errno.h> 39 #include <sys/device.h> 40 #include <sys/malloc.h> 41 42 #include <vm/vm.h> 43 #include <vm/vm_kern.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcireg.h> 47 48 #include <machine/cpu.h> 49 #include <machine/iomap.h> 50 #include <machine/mfp.h> 51 #include <machine/bswap.h> 52 #include <machine/bus.h> 53 54 #include <atari/atari/device.h> 55 #include <atari/pci/pci_vga.h> 56 57 /* 58 * Sizes of pci memory and I/O area. 59 */ 60 #define PCI_MEM_END 0x10000000 /* 256 MByte */ 61 #define PCI_IO_END 0x10000000 /* 256 MByte */ 62 63 /* 64 * We preserve some space at the begin of the pci area for 32BIT_1M 65 * devices and standard vga. 66 */ 67 #define PCI_MEM_START 0x00100000 /* 1 MByte */ 68 #define PCI_IO_START 0x00004000 /* 16 kByte (some PCI cards allow only 69 I/O addresses up to 0xffff) */ 70 71 /* 72 * Struct to hold the memory and I/O datas of the pci devices 73 */ 74 struct pci_memreg { 75 LIST_ENTRY(pci_memreg) link; 76 int dev; 77 pcitag_t tag; 78 pcireg_t reg, address, mask; 79 u_int32_t size; 80 u_int32_t csr; 81 }; 82 83 typedef LIST_HEAD(pci_memreg_head, pci_memreg) PCI_MEMREG; 84 85 int pcibusprint __P((void *auxp, const char *)); 86 int pcibusmatch __P((struct device *, struct cfdata *, void *)); 87 void pcibusattach __P((struct device *, struct device *, void *)); 88 89 static void enable_pci_devices __P((void)); 90 static void insert_into_list __P((PCI_MEMREG *head, struct pci_memreg *elem)); 91 static int overlap_pci_areas __P((struct pci_memreg *p, 92 struct pci_memreg *self, u_int addr, u_int size, u_int what)); 93 static int pci_config_offset __P((pcitag_t)); 94 95 struct cfattach pcibus_ca = { 96 sizeof(struct device), pcibusmatch, pcibusattach 97 }; 98 99 int 100 pcibusmatch(pdp, cfp, auxp) 101 struct device *pdp; 102 struct cfdata *cfp; 103 void *auxp; 104 { 105 if(atari_realconfig == 0) 106 return (0); 107 if (strcmp((char *)auxp, "pcibus") || cfp->cf_unit != 0) 108 return(0); 109 return(machineid & ATARI_HADES ? 1 : 0); 110 } 111 112 void 113 pcibusattach(pdp, dp, auxp) 114 struct device *pdp, *dp; 115 void *auxp; 116 { 117 struct pcibus_attach_args pba; 118 bus_space_tag_t leb_alloc_bus_space_tag __P((void)); 119 120 121 enable_pci_devices(); 122 123 pba.pba_busname = "pci"; 124 pba.pba_pc = NULL; 125 pba.pba_bus = 0; 126 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 127 pba.pba_dmat = BUS_PCI_DMA_TAG; 128 pba.pba_iot = leb_alloc_bus_space_tag(); 129 pba.pba_memt = leb_alloc_bus_space_tag(); 130 if ((pba.pba_iot == NULL) || (pba.pba_memt == NULL)) { 131 printf("leb_alloc_bus_space_tag failed!\n"); 132 return; 133 } 134 pba.pba_iot->base = PCI_IO_PHYS; 135 pba.pba_memt->base = PCI_MEM_PHYS; 136 137 MFP2->mf_aer &= ~(0x27); /* PCI interrupts: HIGH -> LOW */ 138 139 printf("\n"); 140 141 config_found(dp, &pba, pcibusprint); 142 } 143 144 int 145 pcibusprint(auxp, name) 146 void *auxp; 147 const char *name; 148 { 149 if(name == NULL) 150 return(UNCONF); 151 return(QUIET); 152 } 153 154 void 155 pci_attach_hook(parent, self, pba) 156 struct device *parent, *self; 157 struct pcibus_attach_args *pba; 158 { 159 } 160 161 /* 162 * Initialize the PCI-bus. The Atari-BIOS does not do this, so.... 163 * We only disable all devices here. Memory and I/O enabling is done 164 * later at pcibusattach. 165 */ 166 void 167 init_pci_bus() 168 { 169 pci_chipset_tag_t pc = NULL; /* XXX */ 170 pcitag_t tag; 171 pcireg_t csr; 172 int device, id, maxndevs; 173 174 tag = 0; 175 id = 0; 176 177 maxndevs = pci_bus_maxdevs(pc, 0); 178 179 for (device = 0; device < maxndevs; device++) { 180 181 tag = pci_make_tag(pc, 0, device, 0); 182 id = pci_conf_read(pc, tag, PCI_ID_REG); 183 if (id == 0 || id == 0xffffffff) 184 continue; 185 186 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 187 csr &= ~(PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_IO_ENABLE); 188 csr &= ~PCI_COMMAND_MASTER_ENABLE; 189 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 190 } 191 192 /* 193 * Scan the bus for a VGA-card that we support. If we find 194 * one, try to initialize it to a 'standard' text mode (80x25). 195 */ 196 check_for_vga(); 197 } 198 199 /* 200 * insert a new element in an existing list that the ID's (size in struct 201 * pci_memreg) are sorted. 202 */ 203 static void 204 insert_into_list(head, elem) 205 PCI_MEMREG *head; 206 struct pci_memreg *elem; 207 { 208 struct pci_memreg *p, *q; 209 210 p = LIST_FIRST(head); 211 q = NULL; 212 213 for (; p != NULL && p->size < elem->size; q = p, p = LIST_NEXT(p, link)); 214 215 if (q == NULL) { 216 LIST_INSERT_HEAD(head, elem, link); 217 } else { 218 LIST_INSERT_AFTER(q, elem, link); 219 } 220 } 221 222 /* 223 * Test if a new selected area overlaps with an already (probably preselected) 224 * pci area. 225 */ 226 static int 227 overlap_pci_areas(p, self, addr, size, what) 228 struct pci_memreg *p, *self; 229 u_int addr, size, what; 230 { 231 struct pci_memreg *q; 232 233 if (p == NULL) 234 return 0; 235 236 q = p; 237 while (q != NULL) { 238 if ((q != self) && (q->csr & what)) { 239 if ((addr >= q->address) && (addr < (q->address + q->size))) { 240 #ifdef DEBUG_PCI_MACHDEP 241 printf("\noverlap area dev %d reg 0x%02x with dev %d reg 0x%02x", 242 self->dev, self->reg, q->dev, q->reg); 243 #endif 244 return 1; 245 } 246 if ((q->address >= addr) && (q->address < (addr + size))) { 247 #ifdef DEBUG_PCI_MACHDEP 248 printf("\noverlap area dev %d reg 0x%02x with dev %d reg 0x%02x", 249 self->dev, self->reg, q->dev, q->reg); 250 #endif 251 return 1; 252 } 253 } 254 q = LIST_NEXT(q, link); 255 } 256 return 0; 257 } 258 259 /* 260 * Enable memory and I/O on pci devices. Care about already enabled devices 261 * (probabaly by the console driver). 262 * 263 * The idea behind the following code is: 264 * We build a by sizes sorted list of the requirements of the different 265 * pci devices. After that we choose the start addresses of that areas 266 * in such a way that they are placed as closed as possible together. 267 */ 268 static void 269 enable_pci_devices() 270 { 271 PCI_MEMREG memlist; 272 PCI_MEMREG iolist; 273 struct pci_memreg *p, *q; 274 int dev, reg, id, class; 275 pcitag_t tag; 276 pcireg_t csr, address, mask; 277 pci_chipset_tag_t pc; 278 int sizecnt, membase_1m; 279 280 pc = 0; 281 csr = 0; 282 tag = 0; 283 284 LIST_INIT(&memlist); 285 LIST_INIT(&iolist); 286 287 /* 288 * first step: go through all devices and gather memory and I/O 289 * sizes 290 */ 291 for (dev = 0; dev < pci_bus_maxdevs(pc,0); dev++) { 292 293 tag = pci_make_tag(pc, 0, dev, 0); 294 id = pci_conf_read(pc, tag, PCI_ID_REG); 295 if (id == 0 || id == 0xffffffff) 296 continue; 297 298 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 299 300 /* 301 * special case: if a display card is found and memory is enabled 302 * preserve 128k at 0xa0000 as vga memory. 303 */ 304 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 305 switch (PCI_CLASS(class)) { 306 case PCI_CLASS_PREHISTORIC: 307 case PCI_CLASS_DISPLAY: 308 if (csr & (PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE)) { 309 p = (struct pci_memreg *)malloc(sizeof(struct pci_memreg), 310 M_TEMP, M_WAITOK); 311 memset(p, '\0', sizeof(struct pci_memreg)); 312 p->dev = dev; 313 p->csr = csr; 314 p->tag = tag; 315 p->reg = 0; /* there is no register about this */ 316 p->size = 0x20000; /* 128kByte */ 317 p->mask = 0xfffe0000; 318 p->address = 0xa0000; 319 320 insert_into_list(&memlist, p); 321 } 322 } 323 324 for (reg = PCI_MAPREG_START; reg < PCI_MAPREG_END; reg += 4) { 325 326 address = pci_conf_read(pc, tag, reg); 327 pci_conf_write(pc, tag, reg, 0xffffffff); 328 mask = pci_conf_read(pc, tag, reg); 329 pci_conf_write(pc, tag, reg, address); 330 if (mask == 0) 331 continue; /* Register unused */ 332 333 p = (struct pci_memreg *)malloc(sizeof(struct pci_memreg), 334 M_TEMP, M_WAITOK); 335 memset(p, '\0', sizeof(struct pci_memreg)); 336 p->dev = dev; 337 p->csr = csr; 338 p->tag = tag; 339 p->reg = reg; 340 p->mask = mask; 341 p->address = 0; 342 343 if (mask & PCI_MAPREG_TYPE_IO) { 344 p->size = PCI_MAPREG_IO_SIZE(mask); 345 346 /* 347 * if I/O is already enabled (probably by the console driver) 348 * save the address in order to take care about it later. 349 */ 350 if (csr & PCI_COMMAND_IO_ENABLE) 351 p->address = address; 352 353 insert_into_list(&iolist, p); 354 } else { 355 p->size = PCI_MAPREG_MEM_SIZE(mask); 356 357 /* 358 * if memory is already enabled (probably by the console driver) 359 * save the address in order to take care about it later. 360 */ 361 if (csr & PCI_COMMAND_MEM_ENABLE) 362 p->address = address; 363 364 insert_into_list(&memlist, p); 365 366 if (PCI_MAPREG_MEM_TYPE(mask) == PCI_MAPREG_MEM_TYPE_64BIT) 367 reg++; 368 } 369 } 370 371 /* 372 * Both interrupt pin & line are set to the device (== slot) 373 * number. This makes sense on the atari because the 374 * individual slots are hard-wired to a specific MFP-pin. 375 */ 376 csr = (dev << PCI_INTERRUPT_PIN_SHIFT); 377 csr |= (dev << PCI_INTERRUPT_LINE_SHIFT); 378 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, csr); 379 } 380 381 /* 382 * second step: calculate the memory and I/O adresses beginning from 383 * PCI_MEM_START and PCI_IO_START. Care about already mapped areas. 384 * 385 * beginn with memory list 386 */ 387 388 address = PCI_MEM_START; 389 sizecnt = 0; 390 membase_1m = 0; 391 p = LIST_FIRST(&memlist); 392 while (p != NULL) { 393 if (!(p->csr & PCI_COMMAND_MEM_ENABLE)) { 394 if (PCI_MAPREG_MEM_TYPE(p->mask) == PCI_MAPREG_MEM_TYPE_32BIT_1M) { 395 if (p->size > membase_1m) 396 membase_1m = p->size; 397 do { 398 p->address = membase_1m; 399 membase_1m += p->size; 400 } while (overlap_pci_areas(LIST_FIRST(&memlist), p, p->address, 401 p->size, PCI_COMMAND_MEM_ENABLE)); 402 if (membase_1m > 0x00100000) { 403 /* 404 * Should we panic here? 405 */ 406 printf("\npcibus0: dev %d reg %d: memory not configured", 407 p->dev, p->reg); 408 p->reg = 0; 409 } 410 } else { 411 412 if (sizecnt && (p->size > sizecnt)) 413 sizecnt = ((p->size + sizecnt) & p->mask) & 414 PCI_MAPREG_MEM_ADDR_MASK; 415 if (sizecnt > address) { 416 address = sizecnt; 417 sizecnt = 0; 418 } 419 420 do { 421 p->address = address + sizecnt; 422 sizecnt += p->size; 423 } while (overlap_pci_areas(LIST_FIRST(&memlist), p, p->address, 424 p->size, PCI_COMMAND_MEM_ENABLE)); 425 426 if ((address + sizecnt) > PCI_MEM_END) { 427 /* 428 * Should we panic here? 429 */ 430 printf("\npcibus0: dev %d reg %d: memory not configured", 431 p->dev, p->reg); 432 p->reg = 0; 433 } 434 } 435 if (p->reg > 0) { 436 pci_conf_write(pc, p->tag, p->reg, p->address); 437 csr = pci_conf_read(pc, p->tag, PCI_COMMAND_STATUS_REG); 438 csr |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 439 pci_conf_write(pc, p->tag, PCI_COMMAND_STATUS_REG, csr); 440 } 441 } 442 p = LIST_NEXT(p, link); 443 } 444 445 /* 446 * now the I/O list 447 */ 448 449 address = PCI_IO_START; 450 sizecnt = 0; 451 p = LIST_FIRST(&iolist); 452 while (p != NULL) { 453 if (!(p->csr & PCI_COMMAND_IO_ENABLE)) { 454 455 if (sizecnt && (p->size > sizecnt)) 456 sizecnt = ((p->size + sizecnt) & p->mask) & 457 PCI_MAPREG_IO_ADDR_MASK; 458 if (sizecnt > address) { 459 address = sizecnt; 460 sizecnt = 0; 461 } 462 463 do { 464 p->address = address + sizecnt; 465 sizecnt += p->size; 466 } while (overlap_pci_areas(LIST_FIRST(&iolist), p, p->address, 467 p->size, PCI_COMMAND_IO_ENABLE)); 468 469 if ((address + sizecnt) > PCI_IO_END) { 470 /* 471 * Should we panic here? 472 */ 473 printf("\npcibus0: dev %d reg %d: io not configured", 474 p->dev, p->reg); 475 } else { 476 pci_conf_write(pc, p->tag, p->reg, p->address); 477 csr = pci_conf_read(pc, p->tag, PCI_COMMAND_STATUS_REG); 478 csr |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE; 479 pci_conf_write(pc, p->tag, PCI_COMMAND_STATUS_REG, csr); 480 } 481 } 482 p = LIST_NEXT(p, link); 483 } 484 485 #ifdef DEBUG_PCI_MACHDEP 486 printf("\nI/O List:\n"); 487 p = LIST_FIRST(&iolist); 488 489 while (p != NULL) { 490 printf("\ndev: %d, reg: 0x%02x, size: 0x%08x, addr: 0x%08x", p->dev, 491 p->reg, p->size, p->address); 492 p = LIST_NEXT(p, link); 493 } 494 printf("\nMemlist:"); 495 p = LIST_FIRST(&memlist); 496 497 while (p != NULL) { 498 printf("\ndev: %d, reg: 0x%02x, size: 0x%08x, addr: 0x%08x", p->dev, 499 p->reg, p->size, p->address); 500 p = LIST_NEXT(p, link); 501 } 502 #endif 503 504 /* 505 * Free the lists 506 */ 507 p = LIST_FIRST(&iolist); 508 while (p != NULL) { 509 q = p; 510 LIST_REMOVE(q, link); 511 free(p, M_WAITOK); 512 p = LIST_FIRST(&iolist); 513 } 514 p = LIST_FIRST(&memlist); 515 while (p != NULL) { 516 q = p; 517 LIST_REMOVE(q, link); 518 free(p, M_WAITOK); 519 p = LIST_FIRST(&memlist); 520 } 521 } 522 523 /* 524 * Atari_init.c maps the config areas NBPG bytes apart.... 525 */ 526 static int pci_config_offset(tag) 527 pcitag_t tag; 528 { 529 int device; 530 531 device = (tag >> 11) & 0x1f; 532 return(device * NBPG); 533 } 534 535 int 536 pci_bus_maxdevs(pc, busno) 537 pci_chipset_tag_t pc; 538 int busno; 539 { 540 return (4); 541 } 542 543 pcitag_t 544 pci_make_tag(pc, bus, device, function) 545 pci_chipset_tag_t pc; 546 int bus, device, function; 547 { 548 return ((bus << 16) | (device << 11) | (function << 8)); 549 } 550 551 pcireg_t 552 pci_conf_read(pc, tag, reg) 553 pci_chipset_tag_t pc; 554 pcitag_t tag; 555 int reg; 556 { 557 u_long data; 558 559 data = *(u_long *)(pci_conf_addr + pci_config_offset(tag) + reg); 560 return (bswap32(data)); 561 } 562 563 void 564 pci_conf_write(pc, tag, reg, data) 565 pci_chipset_tag_t pc; 566 pcitag_t tag; 567 int reg; 568 pcireg_t data; 569 { 570 *((u_long *)(pci_conf_addr + pci_config_offset(tag) + reg)) 571 = bswap32(data); 572 } 573 574 int 575 pci_intr_map(pc, intrtag, pin, line, ihp) 576 pci_chipset_tag_t pc; 577 pcitag_t intrtag; 578 int pin, line; 579 pci_intr_handle_t *ihp; 580 { 581 /* 582 * According to the PCI-spec, 255 means `unknown' or `no connection'. 583 * Interpret this as 'no interrupt assigned'. 584 */ 585 if (line == 255) { 586 *ihp = -1; 587 return 1; 588 } 589 590 /* 591 * Values are pretty useless because the on the Hades all interrupt 592 * lines for a card are tied together and hardwired to the TT-MFP 593 * I/O port. 594 */ 595 *ihp = line; 596 return 0; 597 } 598 599 const char * 600 pci_intr_string(pc, ih) 601 pci_chipset_tag_t pc; 602 pci_intr_handle_t ih; 603 { 604 static char irqstr[8]; /* 4 + 2 + NULL + sanity */ 605 606 if (ih == -1) 607 panic("pci_intr_string: bogus handle 0x%x\n", ih); 608 609 sprintf(irqstr, "irq %d", ih); 610 return (irqstr); 611 612 } 613 614 /* 615 * The interrupt stuff is rather ugly. On the Hades, all interrupt lines 616 * for a slot are wired together and connected to IO 0,1,2 or 5 (slots: 617 * (0-3) on the TT-MFP. The Pci-config code initializes the irq. number 618 * to the slot position. 619 */ 620 static pci_intr_info_t iinfo[4] = { { -1 }, { -1 }, { -1 }, { -1 } }; 621 622 static int iifun __P((int, int)); 623 624 static int 625 iifun(slot, sr) 626 int slot; 627 int sr; 628 { 629 pci_intr_info_t *iinfo_p; 630 int s; 631 632 iinfo_p = &iinfo[slot]; 633 634 /* 635 * Disable the interrupts 636 */ 637 MFP2->mf_imrb &= ~iinfo_p->imask; 638 639 if ((sr & PSL_IPL) >= (iinfo_p->ipl & PSL_IPL)) { 640 /* 641 * We're running at a too high priority now. 642 */ 643 add_sicallback((si_farg)iifun, (void*)slot, 0); 644 } 645 else { 646 s = splx(iinfo_p->ipl); 647 (void) (iinfo_p->ifunc)(iinfo_p->iarg); 648 splx(s); 649 650 /* 651 * Re-enable interrupts after handling 652 */ 653 MFP2->mf_imrb |= iinfo_p->imask; 654 } 655 return 1; 656 } 657 658 void * 659 pci_intr_establish(pc, ih, level, ih_fun, ih_arg) 660 pci_chipset_tag_t pc; 661 pci_intr_handle_t ih; 662 int level; 663 int (*ih_fun) __P((void *)); 664 void *ih_arg; 665 { 666 pci_intr_info_t *iinfo_p; 667 struct intrhand *ihand; 668 int slot; 669 670 slot = ih; 671 iinfo_p = &iinfo[slot]; 672 673 if (iinfo_p->ipl > 0) 674 panic("pci_intr_establish: interrupt was already established\n"); 675 676 ihand = intr_establish((slot == 3) ? 23 : 16 + slot, USER_VEC, 0, 677 (hw_ifun_t)iifun, (void *)slot); 678 if (ihand != NULL) { 679 iinfo_p->ipl = level; 680 iinfo_p->imask = (slot == 3) ? 0x80 : (0x01 << slot); 681 iinfo_p->ifunc = ih_fun; 682 iinfo_p->iarg = ih_arg; 683 iinfo_p->ihand = ihand; 684 685 /* 686 * Enable (unmask) the interrupt 687 */ 688 MFP2->mf_imrb |= iinfo_p->imask; 689 MFP2->mf_ierb |= iinfo_p->imask; 690 return(iinfo_p); 691 } 692 return NULL; 693 } 694 695 void 696 pci_intr_disestablish(pc, cookie) 697 pci_chipset_tag_t pc; 698 void *cookie; 699 { 700 pci_intr_info_t *iinfo_p = (pci_intr_info_t *)cookie; 701 702 if (iinfo->ipl < 0) 703 panic("pci_intr_disestablish: interrupt was not established\n"); 704 705 MFP2->mf_imrb &= ~iinfo->imask; 706 MFP2->mf_ierb &= ~iinfo->imask; 707 (void) intr_disestablish(iinfo_p->ihand); 708 iinfo_p->ipl = -1; 709 } 710
Indexes created Wed Sep 24 15:09:51 GMT 2025