pci_machdep.c revision 1.24
1 /* $NetBSD: pci_machdep.c,v 1.24 2000/06/29 08:28:25 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Leo Weppelman. All rights reserved. 5 * Copyright (c) 1996, 1997 Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/types.h> 35 #include <sys/param.h> 36 #include <sys/time.h> 37 #include <sys/systm.h> 38 #include <sys/errno.h> 39 #include <sys/device.h> 40 #include <sys/malloc.h> 41 42 #include <uvm/uvm_extern.h> 43 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pcireg.h> 46 47 #include <machine/cpu.h> 48 #include <machine/iomap.h> 49 #include <machine/mfp.h> 50 #include <machine/bswap.h> 51 #include <machine/bus.h> 52 53 #include <atari/atari/device.h> 54 #include <atari/pci/pci_vga.h> 55 56 /* 57 * Sizes of pci memory and I/O area. 58 */ 59 #define PCI_MEM_END 0x10000000 /* 256 MByte */ 60 #define PCI_IO_END 0x10000000 /* 256 MByte */ 61 62 /* 63 * We preserve some space at the begin of the pci area for 32BIT_1M 64 * devices and standard vga. 65 */ 66 #define PCI_MEM_START 0x00100000 /* 1 MByte */ 67 #define PCI_IO_START 0x00004000 /* 16 kByte (some PCI cards allow only 68 I/O adresses up to 0xffff) */ 69 70 /* 71 * PCI memory and IO should be aligned acording to this masks 72 */ 73 #define PCI_MACHDEP_IO_ALIGN_MASK 0xffffff00 74 #define PCI_MACHDEP_MEM_ALIGN_MASK 0xfffff000 75 76 /* 77 * Convert a PCI 'device' number to a slot number. 78 */ 79 #define DEV2SLOT(dev) (3 - dev) 80 81 /* 82 * Struct to hold the memory and I/O datas of the pci devices 83 */ 84 struct pci_memreg { 85 LIST_ENTRY(pci_memreg) link; 86 int dev; 87 pcitag_t tag; 88 pcireg_t reg, address, mask; 89 u_int32_t size; 90 u_int32_t csr; 91 }; 92 93 typedef LIST_HEAD(pci_memreg_head, pci_memreg) PCI_MEMREG; 94 95 int pcibusprint __P((void *auxp, const char *)); 96 int pcibusmatch __P((struct device *, struct cfdata *, void *)); 97 void pcibusattach __P((struct device *, struct device *, void *)); 98 99 static void enable_pci_devices __P((void)); 100 static void insert_into_list __P((PCI_MEMREG *head, struct pci_memreg *elem)); 101 static int overlap_pci_areas __P((struct pci_memreg *p, 102 struct pci_memreg *self, u_int addr, u_int size, u_int what)); 103 static int pci_config_offset __P((pcitag_t)); 104 105 struct cfattach pcibus_ca = { 106 sizeof(struct device), pcibusmatch, pcibusattach 107 }; 108 109 int 110 pcibusmatch(pdp, cfp, auxp) 111 struct device *pdp; 112 struct cfdata *cfp; 113 void *auxp; 114 { 115 if(atari_realconfig == 0) 116 return (0); 117 if (strcmp((char *)auxp, "pcibus") || cfp->cf_unit != 0) 118 return(0); 119 return(machineid & ATARI_HADES ? 1 : 0); 120 } 121 122 void 123 pcibusattach(pdp, dp, auxp) 124 struct device *pdp, *dp; 125 void *auxp; 126 { 127 struct pcibus_attach_args pba; 128 129 enable_pci_devices(); 130 131 pba.pba_busname = "pci"; 132 pba.pba_pc = NULL; 133 pba.pba_bus = 0; 134 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 135 pba.pba_dmat = BUS_PCI_DMA_TAG; 136 pba.pba_iot = leb_alloc_bus_space_tag(NULL); 137 pba.pba_memt = leb_alloc_bus_space_tag(NULL); 138 if ((pba.pba_iot == NULL) || (pba.pba_memt == NULL)) { 139 printf("leb_alloc_bus_space_tag failed!\n"); 140 return; 141 } 142 pba.pba_iot->base = PCI_IO_PHYS; 143 pba.pba_memt->base = PCI_MEM_PHYS; 144 145 MFP2->mf_aer &= ~(0x27); /* PCI interrupts: HIGH -> LOW */ 146 147 printf("\n"); 148 149 config_found(dp, &pba, pcibusprint); 150 } 151 152 int 153 pcibusprint(auxp, name) 154 void *auxp; 155 const char *name; 156 { 157 if(name == NULL) 158 return(UNCONF); 159 return(QUIET); 160 } 161 162 void 163 pci_attach_hook(parent, self, pba) 164 struct device *parent, *self; 165 struct pcibus_attach_args *pba; 166 { 167 } 168 169 /* 170 * Initialize the PCI-bus. The Atari-BIOS does not do this, so.... 171 * We only disable all devices here. Memory and I/O enabling is done 172 * later at pcibusattach. 173 */ 174 void 175 init_pci_bus() 176 { 177 pci_chipset_tag_t pc = NULL; /* XXX */ 178 pcitag_t tag; 179 pcireg_t csr; 180 int device, id, maxndevs; 181 182 tag = 0; 183 id = 0; 184 185 maxndevs = pci_bus_maxdevs(pc, 0); 186 187 for (device = 0; device < maxndevs; device++) { 188 189 tag = pci_make_tag(pc, 0, device, 0); 190 id = pci_conf_read(pc, tag, PCI_ID_REG); 191 if (id == 0 || id == 0xffffffff) 192 continue; 193 194 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 195 csr &= ~(PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_IO_ENABLE); 196 csr &= ~PCI_COMMAND_MASTER_ENABLE; 197 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 198 } 199 200 /* 201 * Scan the bus for a VGA-card that we support. If we find 202 * one, try to initialize it to a 'standard' text mode (80x25). 203 */ 204 check_for_vga(); 205 } 206 207 /* 208 * insert a new element in an existing list that the ID's (size in struct 209 * pci_memreg) are sorted. 210 */ 211 static void 212 insert_into_list(head, elem) 213 PCI_MEMREG *head; 214 struct pci_memreg *elem; 215 { 216 struct pci_memreg *p, *q; 217 218 p = LIST_FIRST(head); 219 q = NULL; 220 221 for (; p != NULL && p->size < elem->size; q = p, p = LIST_NEXT(p, link)); 222 223 if (q == NULL) { 224 LIST_INSERT_HEAD(head, elem, link); 225 } else { 226 LIST_INSERT_AFTER(q, elem, link); 227 } 228 } 229 230 /* 231 * Test if a new selected area overlaps with an already (probably preselected) 232 * pci area. 233 */ 234 static int 235 overlap_pci_areas(p, self, addr, size, what) 236 struct pci_memreg *p, *self; 237 u_int addr, size, what; 238 { 239 struct pci_memreg *q; 240 241 if (p == NULL) 242 return 0; 243 244 q = p; 245 while (q != NULL) { 246 if ((q != self) && (q->csr & what)) { 247 if ((addr >= q->address) && (addr < (q->address + q->size))) { 248 #ifdef DEBUG_PCI_MACHDEP 249 printf("\noverlap area dev %d reg 0x%02x with dev %d reg 0x%02x", 250 self->dev, self->reg, q->dev, q->reg); 251 #endif 252 return 1; 253 } 254 if ((q->address >= addr) && (q->address < (addr + size))) { 255 #ifdef DEBUG_PCI_MACHDEP 256 printf("\noverlap area dev %d reg 0x%02x with dev %d reg 0x%02x", 257 self->dev, self->reg, q->dev, q->reg); 258 #endif 259 return 1; 260 } 261 } 262 q = LIST_NEXT(q, link); 263 } 264 return 0; 265 } 266 267 /* 268 * Enable memory and I/O on pci devices. Care about already enabled devices 269 * (probabaly by the console driver). 270 * 271 * The idea behind the following code is: 272 * We build a by sizes sorted list of the requirements of the different 273 * pci devices. After that we choose the start addresses of that areas 274 * in such a way that they are placed as closed as possible together. 275 */ 276 static void 277 enable_pci_devices() 278 { 279 PCI_MEMREG memlist; 280 PCI_MEMREG iolist; 281 struct pci_memreg *p, *q; 282 int dev, reg, id, class; 283 pcitag_t tag; 284 pcireg_t csr, address, mask; 285 pci_chipset_tag_t pc; 286 int sizecnt, membase_1m; 287 288 pc = 0; 289 csr = 0; 290 tag = 0; 291 292 LIST_INIT(&memlist); 293 LIST_INIT(&iolist); 294 295 /* 296 * first step: go through all devices and gather memory and I/O 297 * sizes 298 */ 299 for (dev = 0; dev < pci_bus_maxdevs(pc,0); dev++) { 300 301 tag = pci_make_tag(pc, 0, dev, 0); 302 id = pci_conf_read(pc, tag, PCI_ID_REG); 303 if (id == 0 || id == 0xffffffff) 304 continue; 305 306 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 307 308 /* 309 * special case: if a display card is found and memory is enabled 310 * preserve 128k at 0xa0000 as vga memory. 311 * XXX: if a display card is found without being enabled, leave 312 * it alone! You will usually only create conflicts by enabeling 313 * it. 314 */ 315 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 316 switch (PCI_CLASS(class)) { 317 case PCI_CLASS_PREHISTORIC: 318 case PCI_CLASS_DISPLAY: 319 if (csr & (PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE)) { 320 p = (struct pci_memreg *)malloc(sizeof(struct pci_memreg), 321 M_TEMP, M_WAITOK); 322 memset(p, '\0', sizeof(struct pci_memreg)); 323 p->dev = dev; 324 p->csr = csr; 325 p->tag = tag; 326 p->reg = 0; /* there is no register about this */ 327 p->size = 0x20000; /* 128kByte */ 328 p->mask = 0xfffe0000; 329 p->address = 0xa0000; 330 331 insert_into_list(&memlist, p); 332 } 333 else continue; 334 } 335 336 for (reg = PCI_MAPREG_START; reg < PCI_MAPREG_END; reg += 4) { 337 338 address = pci_conf_read(pc, tag, reg); 339 pci_conf_write(pc, tag, reg, 0xffffffff); 340 mask = pci_conf_read(pc, tag, reg); 341 pci_conf_write(pc, tag, reg, address); 342 if (mask == 0) 343 continue; /* Register unused */ 344 345 p = (struct pci_memreg *)malloc(sizeof(struct pci_memreg), 346 M_TEMP, M_WAITOK); 347 memset(p, '\0', sizeof(struct pci_memreg)); 348 p->dev = dev; 349 p->csr = csr; 350 p->tag = tag; 351 p->reg = reg; 352 p->mask = mask; 353 p->address = 0; 354 355 if (mask & PCI_MAPREG_TYPE_IO) { 356 p->size = PCI_MAPREG_IO_SIZE(mask); 357 358 /* 359 * Align IO if necessary 360 */ 361 if (p->size < PCI_MAPREG_IO_SIZE(PCI_MACHDEP_IO_ALIGN_MASK)) { 362 p->mask = PCI_MACHDEP_IO_ALIGN_MASK; 363 p->size = PCI_MAPREG_IO_SIZE(p->mask); 364 } 365 366 /* 367 * if I/O is already enabled (probably by the console driver) 368 * save the address in order to take care about it later. 369 */ 370 if (csr & PCI_COMMAND_IO_ENABLE) 371 p->address = address; 372 373 insert_into_list(&iolist, p); 374 } else { 375 p->size = PCI_MAPREG_MEM_SIZE(mask); 376 377 /* 378 * Align memory if necessary 379 */ 380 if (p->size < PCI_MAPREG_IO_SIZE(PCI_MACHDEP_MEM_ALIGN_MASK)) { 381 p->mask = PCI_MACHDEP_MEM_ALIGN_MASK; 382 p->size = PCI_MAPREG_MEM_SIZE(p->mask); 383 } 384 385 /* 386 * if memory is already enabled (probably by the console driver) 387 * save the address in order to take care about it later. 388 */ 389 if (csr & PCI_COMMAND_MEM_ENABLE) 390 p->address = address; 391 392 insert_into_list(&memlist, p); 393 394 if (PCI_MAPREG_MEM_TYPE(mask) == PCI_MAPREG_MEM_TYPE_64BIT) 395 reg++; 396 } 397 } 398 399 /* 400 * Both interrupt pin & line are set to the device (== slot) 401 * number. This makes sense on the atari because the 402 * individual slots are hard-wired to a specific MFP-pin. 403 */ 404 csr = (DEV2SLOT(dev) << PCI_INTERRUPT_PIN_SHIFT); 405 csr |= (DEV2SLOT(dev) << PCI_INTERRUPT_LINE_SHIFT); 406 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, csr); 407 } 408 409 /* 410 * second step: calculate the memory and I/O adresses beginning from 411 * PCI_MEM_START and PCI_IO_START. Care about already mapped areas. 412 * 413 * beginn with memory list 414 */ 415 416 address = PCI_MEM_START; 417 sizecnt = 0; 418 membase_1m = 0; 419 p = LIST_FIRST(&memlist); 420 while (p != NULL) { 421 if (!(p->csr & PCI_COMMAND_MEM_ENABLE)) { 422 if (PCI_MAPREG_MEM_TYPE(p->mask) == PCI_MAPREG_MEM_TYPE_32BIT_1M) { 423 if (p->size > membase_1m) 424 membase_1m = p->size; 425 do { 426 p->address = membase_1m; 427 membase_1m += p->size; 428 } while (overlap_pci_areas(LIST_FIRST(&memlist), p, p->address, 429 p->size, PCI_COMMAND_MEM_ENABLE)); 430 if (membase_1m > 0x00100000) { 431 /* 432 * Should we panic here? 433 */ 434 printf("\npcibus0: dev %d reg %d: memory not configured", 435 p->dev, p->reg); 436 p->reg = 0; 437 } 438 } else { 439 440 if (sizecnt && (p->size > sizecnt)) 441 sizecnt = ((p->size + sizecnt) & p->mask) & 442 PCI_MAPREG_MEM_ADDR_MASK; 443 if (sizecnt > address) { 444 address = sizecnt; 445 sizecnt = 0; 446 } 447 448 do { 449 p->address = address + sizecnt; 450 sizecnt += p->size; 451 } while (overlap_pci_areas(LIST_FIRST(&memlist), p, p->address, 452 p->size, PCI_COMMAND_MEM_ENABLE)); 453 454 if ((address + sizecnt) > PCI_MEM_END) { 455 /* 456 * Should we panic here? 457 */ 458 printf("\npcibus0: dev %d reg %d: memory not configured", 459 p->dev, p->reg); 460 p->reg = 0; 461 } 462 } 463 if (p->reg > 0) { 464 pci_conf_write(pc, p->tag, p->reg, p->address); 465 csr = pci_conf_read(pc, p->tag, PCI_COMMAND_STATUS_REG); 466 csr |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 467 pci_conf_write(pc, p->tag, PCI_COMMAND_STATUS_REG, csr); 468 p->csr = csr; 469 } 470 } 471 p = LIST_NEXT(p, link); 472 } 473 474 /* 475 * now the I/O list 476 */ 477 478 address = PCI_IO_START; 479 sizecnt = 0; 480 p = LIST_FIRST(&iolist); 481 while (p != NULL) { 482 if (!(p->csr & PCI_COMMAND_IO_ENABLE)) { 483 484 if (sizecnt && (p->size > sizecnt)) 485 sizecnt = ((p->size + sizecnt) & p->mask) & 486 PCI_MAPREG_IO_ADDR_MASK; 487 if (sizecnt > address) { 488 address = sizecnt; 489 sizecnt = 0; 490 } 491 492 do { 493 p->address = address + sizecnt; 494 sizecnt += p->size; 495 } while (overlap_pci_areas(LIST_FIRST(&iolist), p, p->address, 496 p->size, PCI_COMMAND_IO_ENABLE)); 497 498 if ((address + sizecnt) > PCI_IO_END) { 499 /* 500 * Should we panic here? 501 */ 502 printf("\npcibus0: dev %d reg %d: io not configured", 503 p->dev, p->reg); 504 } else { 505 pci_conf_write(pc, p->tag, p->reg, p->address); 506 csr = pci_conf_read(pc, p->tag, PCI_COMMAND_STATUS_REG); 507 csr |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE; 508 pci_conf_write(pc, p->tag, PCI_COMMAND_STATUS_REG, csr); 509 p->csr = csr; 510 } 511 } 512 p = LIST_NEXT(p, link); 513 } 514 515 #ifdef DEBUG_PCI_MACHDEP 516 printf("\nI/O List:\n"); 517 p = LIST_FIRST(&iolist); 518 519 while (p != NULL) { 520 printf("\ndev: %d, reg: 0x%02x, size: 0x%08x, addr: 0x%08x", p->dev, 521 p->reg, p->size, p->address); 522 p = LIST_NEXT(p, link); 523 } 524 printf("\nMemlist:"); 525 p = LIST_FIRST(&memlist); 526 527 while (p != NULL) { 528 printf("\ndev: %d, reg: 0x%02x, size: 0x%08x, addr: 0x%08x", p->dev, 529 p->reg, p->size, p->address); 530 p = LIST_NEXT(p, link); 531 } 532 #endif 533 534 /* 535 * Free the lists 536 */ 537 p = LIST_FIRST(&iolist); 538 while (p != NULL) { 539 q = p; 540 LIST_REMOVE(q, link); 541 free(p, M_WAITOK); 542 p = LIST_FIRST(&iolist); 543 } 544 p = LIST_FIRST(&memlist); 545 while (p != NULL) { 546 q = p; 547 LIST_REMOVE(q, link); 548 free(p, M_WAITOK); 549 p = LIST_FIRST(&memlist); 550 } 551 } 552 553 /* 554 * Atari_init.c maps the config areas NBPG bytes apart.... 555 */ 556 static int pci_config_offset(tag) 557 pcitag_t tag; 558 { 559 int device; 560 561 device = (tag >> 11) & 0x1f; 562 return(device * NBPG); 563 } 564 565 int 566 pci_bus_maxdevs(pc, busno) 567 pci_chipset_tag_t pc; 568 int busno; 569 { 570 return (4); 571 } 572 573 pcitag_t 574 pci_make_tag(pc, bus, device, function) 575 pci_chipset_tag_t pc; 576 int bus, device, function; 577 { 578 return ((bus << 16) | (device << 11) | (function << 8)); 579 } 580 581 pcireg_t 582 pci_conf_read(pc, tag, reg) 583 pci_chipset_tag_t pc; 584 pcitag_t tag; 585 int reg; 586 { 587 u_long data; 588 589 data = *(u_long *)(pci_conf_addr + pci_config_offset(tag) + reg); 590 return (bswap32(data)); 591 } 592 593 void 594 pci_conf_write(pc, tag, reg, data) 595 pci_chipset_tag_t pc; 596 pcitag_t tag; 597 int reg; 598 pcireg_t data; 599 { 600 *((u_long *)(pci_conf_addr + pci_config_offset(tag) + reg)) 601 = bswap32(data); 602 } 603 604 int 605 pci_intr_map(pc, intrtag, pin, line, ihp) 606 pci_chipset_tag_t pc; 607 pcitag_t intrtag; 608 int pin, line; 609 pci_intr_handle_t *ihp; 610 { 611 /* 612 * According to the PCI-spec, 255 means `unknown' or `no connection'. 613 * Interpret this as 'no interrupt assigned'. 614 */ 615 if (line == 255) { 616 *ihp = -1; 617 return 1; 618 } 619 620 /* 621 * Values are pretty useless because the on the Hades all interrupt 622 * lines for a card are tied together and hardwired to the TT-MFP 623 * I/O port. 624 */ 625 *ihp = line; 626 return 0; 627 } 628 629 const char * 630 pci_intr_string(pc, ih) 631 pci_chipset_tag_t pc; 632 pci_intr_handle_t ih; 633 { 634 static char irqstr[8]; /* 4 + 2 + NULL + sanity */ 635 636 if (ih == -1) 637 panic("pci_intr_string: bogus handle 0x%x\n", ih); 638 639 sprintf(irqstr, "irq %d", ih); 640 return (irqstr); 641 642 } 643 644 const struct evcnt * 645 pci_intr_evcnt(pc, ih) 646 pci_chipset_tag_t pc; 647 pci_intr_handle_t ih; 648 { 649 650 /* XXX for now, no evcnt parent reported */ 651 return NULL; 652 } 653 654 /* 655 * The interrupt stuff is rather ugly. On the Hades, all interrupt lines 656 * for a slot are wired together and connected to IO 0,1,2 or 5 (slots: 657 * (0-3) on the TT-MFP. The Pci-config code initializes the irq. number 658 * to the slot position. 659 */ 660 static pci_intr_info_t iinfo[4] = { { -1 }, { -1 }, { -1 }, { -1 } }; 661 662 static int iifun __P((int, int)); 663 664 static int 665 iifun(slot, sr) 666 int slot; 667 int sr; 668 { 669 pci_intr_info_t *iinfo_p; 670 int s; 671 672 iinfo_p = &iinfo[slot]; 673 674 /* 675 * Disable the interrupts 676 */ 677 MFP2->mf_imrb &= ~iinfo_p->imask; 678 679 if ((sr & PSL_IPL) >= (iinfo_p->ipl & PSL_IPL)) { 680 /* 681 * We're running at a too high priority now. 682 */ 683 add_sicallback((si_farg)iifun, (void*)slot, 0); 684 } 685 else { 686 s = splx(iinfo_p->ipl); 687 (void) (iinfo_p->ifunc)(iinfo_p->iarg); 688 splx(s); 689 690 /* 691 * Re-enable interrupts after handling 692 */ 693 MFP2->mf_imrb |= iinfo_p->imask; 694 } 695 return 1; 696 } 697 698 void * 699 pci_intr_establish(pc, ih, level, ih_fun, ih_arg) 700 pci_chipset_tag_t pc; 701 pci_intr_handle_t ih; 702 int level; 703 int (*ih_fun) __P((void *)); 704 void *ih_arg; 705 { 706 pci_intr_info_t *iinfo_p; 707 struct intrhand *ihand; 708 int slot; 709 710 slot = ih; 711 iinfo_p = &iinfo[slot]; 712 713 if (iinfo_p->ipl > 0) 714 panic("pci_intr_establish: interrupt was already established\n"); 715 716 ihand = intr_establish((slot == 3) ? 23 : 16 + slot, USER_VEC, 0, 717 (hw_ifun_t)iifun, (void *)slot); 718 if (ihand != NULL) { 719 iinfo_p->ipl = level; 720 iinfo_p->imask = (slot == 3) ? 0x80 : (0x01 << slot); 721 iinfo_p->ifunc = ih_fun; 722 iinfo_p->iarg = ih_arg; 723 iinfo_p->ihand = ihand; 724 725 /* 726 * Enable (unmask) the interrupt 727 */ 728 MFP2->mf_imrb |= iinfo_p->imask; 729 MFP2->mf_ierb |= iinfo_p->imask; 730 return(iinfo_p); 731 } 732 return NULL; 733 } 734 735 void 736 pci_intr_disestablish(pc, cookie) 737 pci_chipset_tag_t pc; 738 void *cookie; 739 { 740 pci_intr_info_t *iinfo_p = (pci_intr_info_t *)cookie; 741 742 if (iinfo->ipl < 0) 743 panic("pci_intr_disestablish: interrupt was not established\n"); 744 745 MFP2->mf_imrb &= ~iinfo->imask; 746 MFP2->mf_ierb &= ~iinfo->imask; 747 (void) intr_disestablish(iinfo_p->ihand); 748 iinfo_p->ipl = -1; 749 } 750
Indexes created Wed Sep 24 15:09:51 GMT 2025