pci_machdep.c revision 1.27
1 /* $NetBSD: pci_machdep.c,v 1.27 2000/09/28 07:26:49 leo Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Leo Weppelman. All rights reserved. 5 * Copyright (c) 1996, 1997 Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/types.h> 35 #include <sys/param.h> 36 #include <sys/time.h> 37 #include <sys/systm.h> 38 #include <sys/errno.h> 39 #include <sys/device.h> 40 #include <sys/malloc.h> 41 42 #include <uvm/uvm_extern.h> 43 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pcireg.h> 46 47 #include <machine/cpu.h> 48 #include <machine/iomap.h> 49 #include <machine/mfp.h> 50 #include <machine/bswap.h> 51 #include <machine/bus.h> 52 53 #include <atari/atari/device.h> 54 #include <atari/pci/pci_vga.h> 55 56 /* 57 * Sizes of pci memory and I/O area. 58 */ 59 #define PCI_MEM_END 0x10000000 /* 256 MByte */ 60 #define PCI_IO_END 0x10000000 /* 256 MByte */ 61 62 /* 63 * We preserve some space at the begin of the pci area for 32BIT_1M 64 * devices and standard vga. 65 */ 66 #define PCI_MEM_START 0x00100000 /* 1 MByte */ 67 #define PCI_IO_START 0x00004000 /* 16 kByte (some PCI cards allow only 68 I/O addresses up to 0xffff) */ 69 70 /* 71 * PCI memory and IO should be aligned acording to this masks 72 */ 73 #define PCI_MACHDEP_IO_ALIGN_MASK 0xffffff00 74 #define PCI_MACHDEP_MEM_ALIGN_MASK 0xfffff000 75 76 /* 77 * Convert a PCI 'device' number to a slot number. 78 */ 79 #define DEV2SLOT(dev) (3 - dev) 80 81 /* 82 * Struct to hold the memory and I/O datas of the pci devices 83 */ 84 struct pci_memreg { 85 LIST_ENTRY(pci_memreg) link; 86 int dev; 87 pcitag_t tag; 88 pcireg_t reg, address, mask; 89 u_int32_t size; 90 u_int32_t csr; 91 }; 92 93 typedef LIST_HEAD(pci_memreg_head, pci_memreg) PCI_MEMREG; 94 95 int pcibusprint __P((void *auxp, const char *)); 96 int pcibusmatch __P((struct device *, struct cfdata *, void *)); 97 void pcibusattach __P((struct device *, struct device *, void *)); 98 99 static void enable_pci_devices __P((void)); 100 static void insert_into_list __P((PCI_MEMREG *head, struct pci_memreg *elem)); 101 static int overlap_pci_areas __P((struct pci_memreg *p, 102 struct pci_memreg *self, u_int addr, u_int size, u_int what)); 103 static int pci_config_offset __P((pcitag_t)); 104 105 struct cfattach pcibus_ca = { 106 sizeof(struct device), pcibusmatch, pcibusattach 107 }; 108 109 /* 110 * We need some static storage to probe pci-busses for VGA cards during 111 * early console init. 112 */ 113 static struct atari_bus_space bs_storage[2]; /* 1 iot, 1 memt */ 114 115 int 116 pcibusmatch(pdp, cfp, auxp) 117 struct device *pdp; 118 struct cfdata *cfp; 119 void *auxp; 120 { 121 static int nmatched = 0; 122 123 if (strcmp((char *)auxp, "pcibus")) 124 return (0); /* Wrong number... */ 125 126 if(atari_realconfig == 0) 127 return (1); 128 129 if (machineid & ATARI_HADES) { 130 /* 131 * The Hades has only one pci bus 132 */ 133 if (nmatched) 134 return (0); 135 nmatched++; 136 return (1); 137 } 138 return (0); 139 } 140 141 void 142 pcibusattach(pdp, dp, auxp) 143 struct device *pdp, *dp; 144 void *auxp; 145 { 146 struct pcibus_attach_args pba; 147 148 pba.pba_busname = "pci"; 149 pba.pba_pc = NULL; 150 pba.pba_bus = 0; 151 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 152 pba.pba_dmat = BUS_PCI_DMA_TAG; 153 pba.pba_iot = leb_alloc_bus_space_tag(&bs_storage[0]); 154 pba.pba_memt = leb_alloc_bus_space_tag(&bs_storage[0]); 155 if ((pba.pba_iot == NULL) || (pba.pba_memt == NULL)) { 156 printf("leb_alloc_bus_space_tag failed!\n"); 157 return; 158 } 159 pba.pba_iot->base = PCI_IO_PHYS; 160 pba.pba_memt->base = PCI_MEM_PHYS; 161 162 if (dp == NULL) { 163 /* 164 * Scan the bus for a VGA-card that we support. If we 165 * find one, try to initialize it to a 'standard' text 166 * mode (80x25). 167 */ 168 check_for_vga(); 169 return; 170 } 171 172 enable_pci_devices(); 173 174 MFP2->mf_aer &= ~(0x27); /* PCI interrupts: HIGH -> LOW */ 175 176 printf("\n"); 177 178 config_found(dp, &pba, pcibusprint); 179 } 180 181 int 182 pcibusprint(auxp, name) 183 void *auxp; 184 const char *name; 185 { 186 if(name == NULL) 187 return(UNCONF); 188 return(QUIET); 189 } 190 191 void 192 pci_attach_hook(parent, self, pba) 193 struct device *parent, *self; 194 struct pcibus_attach_args *pba; 195 { 196 } 197 198 /* 199 * Initialize the PCI-bus. The Atari-BIOS does not do this, so.... 200 * We only disable all devices here. Memory and I/O enabling is done 201 * later at pcibusattach. 202 */ 203 void 204 init_pci_bus() 205 { 206 pci_chipset_tag_t pc = NULL; /* XXX */ 207 pcitag_t tag; 208 pcireg_t csr; 209 int device, id, maxndevs; 210 211 tag = 0; 212 id = 0; 213 214 maxndevs = pci_bus_maxdevs(pc, 0); 215 216 for (device = 0; device < maxndevs; device++) { 217 218 tag = pci_make_tag(pc, 0, device, 0); 219 id = pci_conf_read(pc, tag, PCI_ID_REG); 220 if (id == 0 || id == 0xffffffff) 221 continue; 222 223 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 224 csr &= ~(PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_IO_ENABLE); 225 csr &= ~PCI_COMMAND_MASTER_ENABLE; 226 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 227 } 228 } 229 230 /* 231 * insert a new element in an existing list that the ID's (size in struct 232 * pci_memreg) are sorted. 233 */ 234 static void 235 insert_into_list(head, elem) 236 PCI_MEMREG *head; 237 struct pci_memreg *elem; 238 { 239 struct pci_memreg *p, *q; 240 241 p = LIST_FIRST(head); 242 q = NULL; 243 244 for (; p != NULL && p->size < elem->size; q = p, p = LIST_NEXT(p, link)); 245 246 if (q == NULL) { 247 LIST_INSERT_HEAD(head, elem, link); 248 } else { 249 LIST_INSERT_AFTER(q, elem, link); 250 } 251 } 252 253 /* 254 * Test if a new selected area overlaps with an already (probably preselected) 255 * pci area. 256 */ 257 static int 258 overlap_pci_areas(p, self, addr, size, what) 259 struct pci_memreg *p, *self; 260 u_int addr, size, what; 261 { 262 struct pci_memreg *q; 263 264 if (p == NULL) 265 return 0; 266 267 q = p; 268 while (q != NULL) { 269 if ((q != self) && (q->csr & what)) { 270 if ((addr >= q->address) && (addr < (q->address + q->size))) { 271 #ifdef DEBUG_PCI_MACHDEP 272 printf("\noverlap area dev %d reg 0x%02x with dev %d reg 0x%02x", 273 self->dev, self->reg, q->dev, q->reg); 274 #endif 275 return 1; 276 } 277 if ((q->address >= addr) && (q->address < (addr + size))) { 278 #ifdef DEBUG_PCI_MACHDEP 279 printf("\noverlap area dev %d reg 0x%02x with dev %d reg 0x%02x", 280 self->dev, self->reg, q->dev, q->reg); 281 #endif 282 return 1; 283 } 284 } 285 q = LIST_NEXT(q, link); 286 } 287 return 0; 288 } 289 290 /* 291 * Enable memory and I/O on pci devices. Care about already enabled devices 292 * (probabaly by the console driver). 293 * 294 * The idea behind the following code is: 295 * We build a by sizes sorted list of the requirements of the different 296 * pci devices. After that we choose the start addresses of that areas 297 * in such a way that they are placed as closed as possible together. 298 */ 299 static void 300 enable_pci_devices() 301 { 302 PCI_MEMREG memlist; 303 PCI_MEMREG iolist; 304 struct pci_memreg *p, *q; 305 int dev, reg, id, class; 306 pcitag_t tag; 307 pcireg_t csr, address, mask; 308 pci_chipset_tag_t pc; 309 int sizecnt, membase_1m; 310 311 pc = 0; 312 csr = 0; 313 tag = 0; 314 315 LIST_INIT(&memlist); 316 LIST_INIT(&iolist); 317 318 /* 319 * first step: go through all devices and gather memory and I/O 320 * sizes 321 */ 322 for (dev = 0; dev < pci_bus_maxdevs(pc,0); dev++) { 323 324 tag = pci_make_tag(pc, 0, dev, 0); 325 id = pci_conf_read(pc, tag, PCI_ID_REG); 326 if (id == 0 || id == 0xffffffff) 327 continue; 328 329 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 330 331 /* 332 * special case: if a display card is found and memory is enabled 333 * preserve 128k at 0xa0000 as vga memory. 334 * XXX: if a display card is found without being enabled, leave 335 * it alone! You will usually only create conflicts by enabeling 336 * it. 337 */ 338 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 339 switch (PCI_CLASS(class)) { 340 case PCI_CLASS_PREHISTORIC: 341 case PCI_CLASS_DISPLAY: 342 if (csr & (PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE)) { 343 p = (struct pci_memreg *)malloc(sizeof(struct pci_memreg), 344 M_TEMP, M_WAITOK); 345 memset(p, '\0', sizeof(struct pci_memreg)); 346 p->dev = dev; 347 p->csr = csr; 348 p->tag = tag; 349 p->reg = 0; /* there is no register about this */ 350 p->size = 0x20000; /* 128kByte */ 351 p->mask = 0xfffe0000; 352 p->address = 0xa0000; 353 354 insert_into_list(&memlist, p); 355 } 356 else continue; 357 } 358 359 for (reg = PCI_MAPREG_START; reg < PCI_MAPREG_END; reg += 4) { 360 361 address = pci_conf_read(pc, tag, reg); 362 pci_conf_write(pc, tag, reg, 0xffffffff); 363 mask = pci_conf_read(pc, tag, reg); 364 pci_conf_write(pc, tag, reg, address); 365 if (mask == 0) 366 continue; /* Register unused */ 367 368 p = (struct pci_memreg *)malloc(sizeof(struct pci_memreg), 369 M_TEMP, M_WAITOK); 370 memset(p, '\0', sizeof(struct pci_memreg)); 371 p->dev = dev; 372 p->csr = csr; 373 p->tag = tag; 374 p->reg = reg; 375 p->mask = mask; 376 p->address = 0; 377 378 if (mask & PCI_MAPREG_TYPE_IO) { 379 p->size = PCI_MAPREG_IO_SIZE(mask); 380 381 /* 382 * Align IO if necessary 383 */ 384 if (p->size < PCI_MAPREG_IO_SIZE(PCI_MACHDEP_IO_ALIGN_MASK)) { 385 p->mask = PCI_MACHDEP_IO_ALIGN_MASK; 386 p->size = PCI_MAPREG_IO_SIZE(p->mask); 387 } 388 389 /* 390 * if I/O is already enabled (probably by the console driver) 391 * save the address in order to take care about it later. 392 */ 393 if (csr & PCI_COMMAND_IO_ENABLE) 394 p->address = address; 395 396 insert_into_list(&iolist, p); 397 } else { 398 p->size = PCI_MAPREG_MEM_SIZE(mask); 399 400 /* 401 * Align memory if necessary 402 */ 403 if (p->size < PCI_MAPREG_IO_SIZE(PCI_MACHDEP_MEM_ALIGN_MASK)) { 404 p->mask = PCI_MACHDEP_MEM_ALIGN_MASK; 405 p->size = PCI_MAPREG_MEM_SIZE(p->mask); 406 } 407 408 /* 409 * if memory is already enabled (probably by the console driver) 410 * save the address in order to take care about it later. 411 */ 412 if (csr & PCI_COMMAND_MEM_ENABLE) 413 p->address = address; 414 415 insert_into_list(&memlist, p); 416 417 if (PCI_MAPREG_MEM_TYPE(mask) == PCI_MAPREG_MEM_TYPE_64BIT) 418 reg++; 419 } 420 } 421 422 /* 423 * Both interrupt pin & line are set to the device (== slot) 424 * number. This makes sense on the atari because the 425 * individual slots are hard-wired to a specific MFP-pin. 426 */ 427 csr = (DEV2SLOT(dev) << PCI_INTERRUPT_PIN_SHIFT); 428 csr |= (DEV2SLOT(dev) << PCI_INTERRUPT_LINE_SHIFT); 429 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, csr); 430 } 431 432 /* 433 * second step: calculate the memory and I/O adresses beginning from 434 * PCI_MEM_START and PCI_IO_START. Care about already mapped areas. 435 * 436 * begin with memory list 437 */ 438 439 address = PCI_MEM_START; 440 sizecnt = 0; 441 membase_1m = 0; 442 p = LIST_FIRST(&memlist); 443 while (p != NULL) { 444 if (!(p->csr & PCI_COMMAND_MEM_ENABLE)) { 445 if (PCI_MAPREG_MEM_TYPE(p->mask) == PCI_MAPREG_MEM_TYPE_32BIT_1M) { 446 if (p->size > membase_1m) 447 membase_1m = p->size; 448 do { 449 p->address = membase_1m; 450 membase_1m += p->size; 451 } while (overlap_pci_areas(LIST_FIRST(&memlist), p, p->address, 452 p->size, PCI_COMMAND_MEM_ENABLE)); 453 if (membase_1m > 0x00100000) { 454 /* 455 * Should we panic here? 456 */ 457 printf("\npcibus0: dev %d reg %d: memory not configured", 458 p->dev, p->reg); 459 p->reg = 0; 460 } 461 } else { 462 463 if (sizecnt && (p->size > sizecnt)) 464 sizecnt = ((p->size + sizecnt) & p->mask) & 465 PCI_MAPREG_MEM_ADDR_MASK; 466 if (sizecnt > address) { 467 address = sizecnt; 468 sizecnt = 0; 469 } 470 471 do { 472 p->address = address + sizecnt; 473 sizecnt += p->size; 474 } while (overlap_pci_areas(LIST_FIRST(&memlist), p, p->address, 475 p->size, PCI_COMMAND_MEM_ENABLE)); 476 477 if ((address + sizecnt) > PCI_MEM_END) { 478 /* 479 * Should we panic here? 480 */ 481 printf("\npcibus0: dev %d reg %d: memory not configured", 482 p->dev, p->reg); 483 p->reg = 0; 484 } 485 } 486 if (p->reg > 0) { 487 pci_conf_write(pc, p->tag, p->reg, p->address); 488 csr = pci_conf_read(pc, p->tag, PCI_COMMAND_STATUS_REG); 489 csr |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 490 pci_conf_write(pc, p->tag, PCI_COMMAND_STATUS_REG, csr); 491 p->csr = csr; 492 } 493 } 494 p = LIST_NEXT(p, link); 495 } 496 497 /* 498 * now the I/O list 499 */ 500 501 address = PCI_IO_START; 502 sizecnt = 0; 503 p = LIST_FIRST(&iolist); 504 while (p != NULL) { 505 if (!(p->csr & PCI_COMMAND_IO_ENABLE)) { 506 507 if (sizecnt && (p->size > sizecnt)) 508 sizecnt = ((p->size + sizecnt) & p->mask) & 509 PCI_MAPREG_IO_ADDR_MASK; 510 if (sizecnt > address) { 511 address = sizecnt; 512 sizecnt = 0; 513 } 514 515 do { 516 p->address = address + sizecnt; 517 sizecnt += p->size; 518 } while (overlap_pci_areas(LIST_FIRST(&iolist), p, p->address, 519 p->size, PCI_COMMAND_IO_ENABLE)); 520 521 if ((address + sizecnt) > PCI_IO_END) { 522 /* 523 * Should we panic here? 524 */ 525 printf("\npcibus0: dev %d reg %d: io not configured", 526 p->dev, p->reg); 527 } else { 528 pci_conf_write(pc, p->tag, p->reg, p->address); 529 csr = pci_conf_read(pc, p->tag, PCI_COMMAND_STATUS_REG); 530 csr |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE; 531 pci_conf_write(pc, p->tag, PCI_COMMAND_STATUS_REG, csr); 532 p->csr = csr; 533 } 534 } 535 p = LIST_NEXT(p, link); 536 } 537 538 #ifdef DEBUG_PCI_MACHDEP 539 printf("\nI/O List:\n"); 540 p = LIST_FIRST(&iolist); 541 542 while (p != NULL) { 543 printf("\ndev: %d, reg: 0x%02x, size: 0x%08x, addr: 0x%08x", p->dev, 544 p->reg, p->size, p->address); 545 p = LIST_NEXT(p, link); 546 } 547 printf("\nMemlist:"); 548 p = LIST_FIRST(&memlist); 549 550 while (p != NULL) { 551 printf("\ndev: %d, reg: 0x%02x, size: 0x%08x, addr: 0x%08x", p->dev, 552 p->reg, p->size, p->address); 553 p = LIST_NEXT(p, link); 554 } 555 #endif 556 557 /* 558 * Free the lists 559 */ 560 p = LIST_FIRST(&iolist); 561 while (p != NULL) { 562 q = p; 563 LIST_REMOVE(q, link); 564 free(p, M_WAITOK); 565 p = LIST_FIRST(&iolist); 566 } 567 p = LIST_FIRST(&memlist); 568 while (p != NULL) { 569 q = p; 570 LIST_REMOVE(q, link); 571 free(p, M_WAITOK); 572 p = LIST_FIRST(&memlist); 573 } 574 } 575 576 /* 577 * Atari_init.c maps the config areas NBPG bytes apart.... 578 */ 579 static int pci_config_offset(tag) 580 pcitag_t tag; 581 { 582 int device; 583 584 device = (tag >> 11) & 0x1f; 585 return(device * NBPG); 586 } 587 588 int 589 pci_bus_maxdevs(pc, busno) 590 pci_chipset_tag_t pc; 591 int busno; 592 { 593 return (4); 594 } 595 596 pcitag_t 597 pci_make_tag(pc, bus, device, function) 598 pci_chipset_tag_t pc; 599 int bus, device, function; 600 { 601 return ((bus << 16) | (device << 11) | (function << 8)); 602 } 603 604 pcireg_t 605 pci_conf_read(pc, tag, reg) 606 pci_chipset_tag_t pc; 607 pcitag_t tag; 608 int reg; 609 { 610 u_long data; 611 612 data = *(u_long *)(pci_conf_addr + pci_config_offset(tag) + reg); 613 return (bswap32(data)); 614 } 615 616 void 617 pci_conf_write(pc, tag, reg, data) 618 pci_chipset_tag_t pc; 619 pcitag_t tag; 620 int reg; 621 pcireg_t data; 622 { 623 *((u_long *)(pci_conf_addr + pci_config_offset(tag) + reg)) 624 = bswap32(data); 625 } 626 627 int 628 pci_intr_map(pc, intrtag, pin, line, ihp) 629 pci_chipset_tag_t pc; 630 pcitag_t intrtag; 631 int pin, line; 632 pci_intr_handle_t *ihp; 633 { 634 /* 635 * According to the PCI-spec, 255 means `unknown' or `no connection'. 636 * Interpret this as 'no interrupt assigned'. 637 */ 638 if (line == 255) { 639 *ihp = -1; 640 return 1; 641 } 642 643 /* 644 * Values are pretty useless because the on the Hades all interrupt 645 * lines for a card are tied together and hardwired to the TT-MFP 646 * I/O port. 647 */ 648 *ihp = line; 649 return 0; 650 } 651 652 const char * 653 pci_intr_string(pc, ih) 654 pci_chipset_tag_t pc; 655 pci_intr_handle_t ih; 656 { 657 static char irqstr[8]; /* 4 + 2 + NULL + sanity */ 658 659 if (ih == -1) 660 panic("pci_intr_string: bogus handle 0x%x\n", ih); 661 662 sprintf(irqstr, "irq %d", ih); 663 return (irqstr); 664 665 } 666 667 const struct evcnt * 668 pci_intr_evcnt(pc, ih) 669 pci_chipset_tag_t pc; 670 pci_intr_handle_t ih; 671 { 672 673 /* XXX for now, no evcnt parent reported */ 674 return NULL; 675 } 676 677 /* 678 * The interrupt stuff is rather ugly. On the Hades, all interrupt lines 679 * for a slot are wired together and connected to IO 0,1,2 or 5 (slots: 680 * (0-3) on the TT-MFP. The Pci-config code initializes the irq. number 681 * to the slot position. 682 */ 683 static pci_intr_info_t iinfo[4] = { { -1 }, { -1 }, { -1 }, { -1 } }; 684 685 static int iifun __P((int, int)); 686 687 static int 688 iifun(slot, sr) 689 int slot; 690 int sr; 691 { 692 pci_intr_info_t *iinfo_p; 693 int s; 694 695 iinfo_p = &iinfo[slot]; 696 697 /* 698 * Disable the interrupts 699 */ 700 MFP2->mf_imrb &= ~iinfo_p->imask; 701 702 if ((sr & PSL_IPL) >= (iinfo_p->ipl & PSL_IPL)) { 703 /* 704 * We're running at a too high priority now. 705 */ 706 add_sicallback((si_farg)iifun, (void*)slot, 0); 707 } 708 else { 709 s = splx(iinfo_p->ipl); 710 (void) (iinfo_p->ifunc)(iinfo_p->iarg); 711 splx(s); 712 713 /* 714 * Re-enable interrupts after handling 715 */ 716 MFP2->mf_imrb |= iinfo_p->imask; 717 } 718 return 1; 719 } 720 721 void * 722 pci_intr_establish(pc, ih, level, ih_fun, ih_arg) 723 pci_chipset_tag_t pc; 724 pci_intr_handle_t ih; 725 int level; 726 int (*ih_fun) __P((void *)); 727 void *ih_arg; 728 { 729 pci_intr_info_t *iinfo_p; 730 struct intrhand *ihand; 731 int slot; 732 733 slot = ih; 734 iinfo_p = &iinfo[slot]; 735 736 if (iinfo_p->ipl > 0) 737 panic("pci_intr_establish: interrupt was already established\n"); 738 739 ihand = intr_establish((slot == 3) ? 23 : 16 + slot, USER_VEC, 0, 740 (hw_ifun_t)iifun, (void *)slot); 741 if (ihand != NULL) { 742 iinfo_p->ipl = level; 743 iinfo_p->imask = (slot == 3) ? 0x80 : (0x01 << slot); 744 iinfo_p->ifunc = ih_fun; 745 iinfo_p->iarg = ih_arg; 746 iinfo_p->ihand = ihand; 747 748 /* 749 * Enable (unmask) the interrupt 750 */ 751 MFP2->mf_imrb |= iinfo_p->imask; 752 MFP2->mf_ierb |= iinfo_p->imask; 753 return(iinfo_p); 754 } 755 return NULL; 756 } 757 758 void 759 pci_intr_disestablish(pc, cookie) 760 pci_chipset_tag_t pc; 761 void *cookie; 762 { 763 pci_intr_info_t *iinfo_p = (pci_intr_info_t *)cookie; 764 765 if (iinfo->ipl < 0) 766 panic("pci_intr_disestablish: interrupt was not established\n"); 767 768 MFP2->mf_imrb &= ~iinfo->imask; 769 MFP2->mf_ierb &= ~iinfo->imask; 770 (void) intr_disestablish(iinfo_p->ihand); 771 iinfo_p->ipl = -1; 772 } 773
Indexes created Tue Sep 23 14:10:03 GMT 2025