pci_machdep.c revision 1.32
1 /* $NetBSD: pci_machdep.c,v 1.32 2001/05/28 07:22:37 leo Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Leo Weppelman. All rights reserved. 5 * Copyright (c) 1996, 1997 Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles M. Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include "opt_mbtype.h" 35 #include <sys/types.h> 36 #include <sys/param.h> 37 #include <sys/time.h> 38 #include <sys/systm.h> 39 #include <sys/errno.h> 40 #include <sys/device.h> 41 #include <sys/malloc.h> 42 43 #define _ATARI_BUS_DMA_PRIVATE 44 #include <machine/bus.h> 45 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcireg.h> 48 49 #include <uvm/uvm_extern.h> 50 51 #include <machine/cpu.h> 52 #include <machine/iomap.h> 53 #include <machine/mfp.h> 54 55 #include <atari/atari/device.h> 56 #include <atari/pci/pci_vga.h> 57 58 /* 59 * Sizes of pci memory and I/O area. 60 */ 61 #define PCI_MEM_END 0x10000000 /* 256 MByte */ 62 #define PCI_IO_END 0x10000000 /* 256 MByte */ 63 64 /* 65 * We preserve some space at the begin of the pci area for 32BIT_1M 66 * devices and standard vga. 67 */ 68 #define PCI_MEM_START 0x00100000 /* 1 MByte */ 69 #define PCI_IO_START 0x00004000 /* 16 kByte (some PCI cards allow only 70 I/O addresses up to 0xffff) */ 71 72 /* 73 * PCI memory and IO should be aligned acording to this masks 74 */ 75 #define PCI_MACHDEP_IO_ALIGN_MASK 0xffffff00 76 #define PCI_MACHDEP_MEM_ALIGN_MASK 0xfffff000 77 78 /* 79 * Convert a PCI 'device' number to a slot number. 80 */ 81 #define DEV2SLOT(dev) (3 - dev) 82 83 /* 84 * Struct to hold the memory and I/O datas of the pci devices 85 */ 86 struct pci_memreg { 87 LIST_ENTRY(pci_memreg) link; 88 int dev; 89 pcitag_t tag; 90 pcireg_t reg, address, mask; 91 u_int32_t size; 92 u_int32_t csr; 93 }; 94 95 typedef LIST_HEAD(pci_memreg_head, pci_memreg) PCI_MEMREG; 96 97 /* 98 * Entry points for PCI DMA. Use only the 'standard' functions. 99 */ 100 int _bus_dmamap_create __P((bus_dma_tag_t, bus_size_t, int, bus_size_t, 101 bus_size_t, int, bus_dmamap_t *)); 102 struct atari_bus_dma_tag pci_bus_dma_tag = { 103 0, 104 #ifdef _ATARIHW_ 105 0x80000000, /* On the Hades, CPU memory starts here PCI-wise */ 106 #else 107 0, 108 #endif 109 _bus_dmamap_create, 110 _bus_dmamap_destroy, 111 _bus_dmamap_load, 112 _bus_dmamap_load_mbuf, 113 _bus_dmamap_load_uio, 114 _bus_dmamap_load_raw, 115 _bus_dmamap_unload, 116 _bus_dmamap_sync, 117 }; 118 119 int pcibusprint __P((void *auxp, const char *)); 120 int pcibusmatch __P((struct device *, struct cfdata *, void *)); 121 void pcibusattach __P((struct device *, struct device *, void *)); 122 123 static void enable_pci_devices __P((void)); 124 static void insert_into_list __P((PCI_MEMREG *head, struct pci_memreg *elem)); 125 static int overlap_pci_areas __P((struct pci_memreg *p, 126 struct pci_memreg *self, u_int addr, u_int size, u_int what)); 127 128 struct cfattach pcibus_ca = { 129 sizeof(struct device), pcibusmatch, pcibusattach 130 }; 131 132 /* 133 * We need some static storage to probe pci-busses for VGA cards during 134 * early console init. 135 */ 136 static struct atari_bus_space bs_storage[2]; /* 1 iot, 1 memt */ 137 138 int 139 pcibusmatch(pdp, cfp, auxp) 140 struct device *pdp; 141 struct cfdata *cfp; 142 void *auxp; 143 { 144 static int nmatched = 0; 145 146 if (strcmp((char *)auxp, "pcibus")) 147 return (0); /* Wrong number... */ 148 149 if(atari_realconfig == 0) 150 return (1); 151 152 if (machineid & (ATARI_HADES|ATARI_MILAN)) { 153 /* 154 * Both Hades and Milan have only one pci bus 155 */ 156 if (nmatched) 157 return (0); 158 nmatched++; 159 return (1); 160 } 161 return (0); 162 } 163 164 void 165 pcibusattach(pdp, dp, auxp) 166 struct device *pdp, *dp; 167 void *auxp; 168 { 169 struct pcibus_attach_args pba; 170 171 pba.pba_busname = "pci"; 172 pba.pba_pc = NULL; 173 pba.pba_bus = 0; 174 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 175 pba.pba_dmat = &pci_bus_dma_tag; 176 pba.pba_iot = leb_alloc_bus_space_tag(&bs_storage[0]); 177 pba.pba_memt = leb_alloc_bus_space_tag(&bs_storage[1]); 178 if ((pba.pba_iot == NULL) || (pba.pba_memt == NULL)) { 179 printf("leb_alloc_bus_space_tag failed!\n"); 180 return; 181 } 182 pba.pba_iot->base = PCI_IO_PHYS; 183 pba.pba_memt->base = PCI_MEM_PHYS; 184 185 if (dp == NULL) { 186 /* 187 * Scan the bus for a VGA-card that we support. If we 188 * find one, try to initialize it to a 'standard' text 189 * mode (80x25). 190 */ 191 check_for_vga(pba.pba_iot, pba.pba_memt); 192 return; 193 } 194 195 enable_pci_devices(); 196 197 #if defined(_ATARIHW_) 198 MFP2->mf_aer &= ~(0x27); /* PCI interrupts: HIGH -> LOW */ 199 #endif 200 201 printf("\n"); 202 203 config_found(dp, &pba, pcibusprint); 204 } 205 206 int 207 pcibusprint(auxp, name) 208 void *auxp; 209 const char *name; 210 { 211 if(name == NULL) 212 return(UNCONF); 213 return(QUIET); 214 } 215 216 void 217 pci_attach_hook(parent, self, pba) 218 struct device *parent, *self; 219 struct pcibus_attach_args *pba; 220 { 221 } 222 223 /* 224 * Initialize the PCI-bus. The Atari-BIOS does not do this, so.... 225 * We only disable all devices here. Memory and I/O enabling is done 226 * later at pcibusattach. 227 */ 228 void 229 init_pci_bus() 230 { 231 pci_chipset_tag_t pc = NULL; /* XXX */ 232 pcitag_t tag; 233 pcireg_t csr; 234 int device, id, maxndevs; 235 236 tag = 0; 237 id = 0; 238 239 maxndevs = pci_bus_maxdevs(pc, 0); 240 241 for (device = 0; device < maxndevs; device++) { 242 243 tag = pci_make_tag(pc, 0, device, 0); 244 id = pci_conf_read(pc, tag, PCI_ID_REG); 245 if (id == 0 || id == 0xffffffff) 246 continue; 247 248 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 249 csr &= ~(PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_IO_ENABLE); 250 csr &= ~PCI_COMMAND_MASTER_ENABLE; 251 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 252 } 253 } 254 255 /* 256 * insert a new element in an existing list that the ID's (size in struct 257 * pci_memreg) are sorted. 258 */ 259 static void 260 insert_into_list(head, elem) 261 PCI_MEMREG *head; 262 struct pci_memreg *elem; 263 { 264 struct pci_memreg *p, *q; 265 266 p = LIST_FIRST(head); 267 q = NULL; 268 269 for (; p != NULL && p->size < elem->size; q = p, p = LIST_NEXT(p, link)); 270 271 if (q == NULL) { 272 LIST_INSERT_HEAD(head, elem, link); 273 } else { 274 LIST_INSERT_AFTER(q, elem, link); 275 } 276 } 277 278 /* 279 * Test if a new selected area overlaps with an already (probably preselected) 280 * pci area. 281 */ 282 static int 283 overlap_pci_areas(p, self, addr, size, what) 284 struct pci_memreg *p, *self; 285 u_int addr, size, what; 286 { 287 struct pci_memreg *q; 288 289 if (p == NULL) 290 return 0; 291 292 q = p; 293 while (q != NULL) { 294 if ((q != self) && (q->csr & what)) { 295 if ((addr >= q->address) && (addr < (q->address + q->size))) { 296 #ifdef DEBUG_PCI_MACHDEP 297 printf("\noverlap area dev %d reg 0x%02x with dev %d reg 0x%02x", 298 self->dev, self->reg, q->dev, q->reg); 299 #endif 300 return 1; 301 } 302 if ((q->address >= addr) && (q->address < (addr + size))) { 303 #ifdef DEBUG_PCI_MACHDEP 304 printf("\noverlap area dev %d reg 0x%02x with dev %d reg 0x%02x", 305 self->dev, self->reg, q->dev, q->reg); 306 #endif 307 return 1; 308 } 309 } 310 q = LIST_NEXT(q, link); 311 } 312 return 0; 313 } 314 315 /* 316 * Enable memory and I/O on pci devices. Care about already enabled devices 317 * (probabaly by the console driver). 318 * 319 * The idea behind the following code is: 320 * We build a by sizes sorted list of the requirements of the different 321 * pci devices. After that we choose the start addresses of that areas 322 * in such a way that they are placed as closed as possible together. 323 */ 324 static void 325 enable_pci_devices() 326 { 327 PCI_MEMREG memlist; 328 PCI_MEMREG iolist; 329 struct pci_memreg *p, *q; 330 int dev, reg, id, class; 331 pcitag_t tag; 332 pcireg_t csr, address, mask; 333 pci_chipset_tag_t pc; 334 int sizecnt, membase_1m; 335 336 pc = 0; 337 csr = 0; 338 tag = 0; 339 340 LIST_INIT(&memlist); 341 LIST_INIT(&iolist); 342 343 /* 344 * first step: go through all devices and gather memory and I/O 345 * sizes 346 */ 347 for (dev = 0; dev < pci_bus_maxdevs(pc,0); dev++) { 348 349 tag = pci_make_tag(pc, 0, dev, 0); 350 id = pci_conf_read(pc, tag, PCI_ID_REG); 351 if (id == 0 || id == 0xffffffff) 352 continue; 353 354 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 355 356 /* 357 * special case: if a display card is found and memory is enabled 358 * preserve 128k at 0xa0000 as vga memory. 359 * XXX: if a display card is found without being enabled, leave 360 * it alone! You will usually only create conflicts by enabeling 361 * it. 362 */ 363 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 364 switch (PCI_CLASS(class)) { 365 case PCI_CLASS_PREHISTORIC: 366 case PCI_CLASS_DISPLAY: 367 if (csr & (PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE)) { 368 p = (struct pci_memreg *)malloc(sizeof(struct pci_memreg), 369 M_TEMP, M_WAITOK); 370 memset(p, '\0', sizeof(struct pci_memreg)); 371 p->dev = dev; 372 p->csr = csr; 373 p->tag = tag; 374 p->reg = 0; /* there is no register about this */ 375 p->size = 0x20000; /* 128kByte */ 376 p->mask = 0xfffe0000; 377 p->address = 0xa0000; 378 379 insert_into_list(&memlist, p); 380 } 381 else continue; 382 } 383 384 for (reg = PCI_MAPREG_START; reg < PCI_MAPREG_END; reg += 4) { 385 386 address = pci_conf_read(pc, tag, reg); 387 pci_conf_write(pc, tag, reg, 0xffffffff); 388 mask = pci_conf_read(pc, tag, reg); 389 pci_conf_write(pc, tag, reg, address); 390 if (mask == 0) 391 continue; /* Register unused */ 392 393 p = (struct pci_memreg *)malloc(sizeof(struct pci_memreg), 394 M_TEMP, M_WAITOK); 395 memset(p, '\0', sizeof(struct pci_memreg)); 396 p->dev = dev; 397 p->csr = csr; 398 p->tag = tag; 399 p->reg = reg; 400 p->mask = mask; 401 p->address = 0; 402 403 if (mask & PCI_MAPREG_TYPE_IO) { 404 p->size = PCI_MAPREG_IO_SIZE(mask); 405 406 /* 407 * Align IO if necessary 408 */ 409 if (p->size < PCI_MAPREG_IO_SIZE(PCI_MACHDEP_IO_ALIGN_MASK)) { 410 p->mask = PCI_MACHDEP_IO_ALIGN_MASK; 411 p->size = PCI_MAPREG_IO_SIZE(p->mask); 412 } 413 414 /* 415 * if I/O is already enabled (probably by the console driver) 416 * save the address in order to take care about it later. 417 */ 418 if (csr & PCI_COMMAND_IO_ENABLE) 419 p->address = address; 420 421 insert_into_list(&iolist, p); 422 } else { 423 p->size = PCI_MAPREG_MEM_SIZE(mask); 424 425 /* 426 * Align memory if necessary 427 */ 428 if (p->size < PCI_MAPREG_IO_SIZE(PCI_MACHDEP_MEM_ALIGN_MASK)) { 429 p->mask = PCI_MACHDEP_MEM_ALIGN_MASK; 430 p->size = PCI_MAPREG_MEM_SIZE(p->mask); 431 } 432 433 /* 434 * if memory is already enabled (probably by the console driver) 435 * save the address in order to take care about it later. 436 */ 437 if (csr & PCI_COMMAND_MEM_ENABLE) 438 p->address = address; 439 440 insert_into_list(&memlist, p); 441 442 if (PCI_MAPREG_MEM_TYPE(mask) == PCI_MAPREG_MEM_TYPE_64BIT) 443 reg++; 444 } 445 } 446 447 /* 448 * Both interrupt pin & line are set to the device (== slot) 449 * number. This makes sense on the atari because the 450 * individual slots are hard-wired to a specific MFP-pin. 451 * XXX: This is _not_ true on the Milan. 452 */ 453 csr = (DEV2SLOT(dev) << PCI_INTERRUPT_PIN_SHIFT); 454 csr |= (DEV2SLOT(dev) << PCI_INTERRUPT_LINE_SHIFT); 455 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, csr); 456 } 457 458 /* 459 * second step: calculate the memory and I/O adresses beginning from 460 * PCI_MEM_START and PCI_IO_START. Care about already mapped areas. 461 * 462 * begin with memory list 463 */ 464 465 address = PCI_MEM_START; 466 sizecnt = 0; 467 membase_1m = 0; 468 p = LIST_FIRST(&memlist); 469 while (p != NULL) { 470 if (!(p->csr & PCI_COMMAND_MEM_ENABLE)) { 471 if (PCI_MAPREG_MEM_TYPE(p->mask) == PCI_MAPREG_MEM_TYPE_32BIT_1M) { 472 if (p->size > membase_1m) 473 membase_1m = p->size; 474 do { 475 p->address = membase_1m; 476 membase_1m += p->size; 477 } while (overlap_pci_areas(LIST_FIRST(&memlist), p, p->address, 478 p->size, PCI_COMMAND_MEM_ENABLE)); 479 if (membase_1m > 0x00100000) { 480 /* 481 * Should we panic here? 482 */ 483 printf("\npcibus0: dev %d reg %d: memory not configured", 484 p->dev, p->reg); 485 p->reg = 0; 486 } 487 } else { 488 489 if (sizecnt && (p->size > sizecnt)) 490 sizecnt = ((p->size + sizecnt) & p->mask) & 491 PCI_MAPREG_MEM_ADDR_MASK; 492 if (sizecnt > address) { 493 address = sizecnt; 494 sizecnt = 0; 495 } 496 497 do { 498 p->address = address + sizecnt; 499 sizecnt += p->size; 500 } while (overlap_pci_areas(LIST_FIRST(&memlist), p, p->address, 501 p->size, PCI_COMMAND_MEM_ENABLE)); 502 503 if ((address + sizecnt) > PCI_MEM_END) { 504 /* 505 * Should we panic here? 506 */ 507 printf("\npcibus0: dev %d reg %d: memory not configured", 508 p->dev, p->reg); 509 p->reg = 0; 510 } 511 } 512 if (p->reg > 0) { 513 pci_conf_write(pc, p->tag, p->reg, p->address); 514 csr = pci_conf_read(pc, p->tag, PCI_COMMAND_STATUS_REG); 515 csr |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 516 pci_conf_write(pc, p->tag, PCI_COMMAND_STATUS_REG, csr); 517 p->csr = csr; 518 } 519 } 520 p = LIST_NEXT(p, link); 521 } 522 523 /* 524 * now the I/O list 525 */ 526 527 address = PCI_IO_START; 528 sizecnt = 0; 529 p = LIST_FIRST(&iolist); 530 while (p != NULL) { 531 if (!(p->csr & PCI_COMMAND_IO_ENABLE)) { 532 533 if (sizecnt && (p->size > sizecnt)) 534 sizecnt = ((p->size + sizecnt) & p->mask) & 535 PCI_MAPREG_IO_ADDR_MASK; 536 if (sizecnt > address) { 537 address = sizecnt; 538 sizecnt = 0; 539 } 540 541 do { 542 p->address = address + sizecnt; 543 sizecnt += p->size; 544 } while (overlap_pci_areas(LIST_FIRST(&iolist), p, p->address, 545 p->size, PCI_COMMAND_IO_ENABLE)); 546 547 if ((address + sizecnt) > PCI_IO_END) { 548 /* 549 * Should we panic here? 550 */ 551 printf("\npcibus0: dev %d reg %d: io not configured", 552 p->dev, p->reg); 553 } else { 554 pci_conf_write(pc, p->tag, p->reg, p->address); 555 csr = pci_conf_read(pc, p->tag, PCI_COMMAND_STATUS_REG); 556 csr |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE; 557 pci_conf_write(pc, p->tag, PCI_COMMAND_STATUS_REG, csr); 558 p->csr = csr; 559 } 560 } 561 p = LIST_NEXT(p, link); 562 } 563 564 #ifdef DEBUG_PCI_MACHDEP 565 printf("\nI/O List:\n"); 566 p = LIST_FIRST(&iolist); 567 568 while (p != NULL) { 569 printf("\ndev: %d, reg: 0x%02x, size: 0x%08x, addr: 0x%08x", p->dev, 570 p->reg, p->size, p->address); 571 p = LIST_NEXT(p, link); 572 } 573 printf("\nMemlist:"); 574 p = LIST_FIRST(&memlist); 575 576 while (p != NULL) { 577 printf("\ndev: %d, reg: 0x%02x, size: 0x%08x, addr: 0x%08x", p->dev, 578 p->reg, p->size, p->address); 579 p = LIST_NEXT(p, link); 580 } 581 #endif 582 583 /* 584 * Free the lists 585 */ 586 p = LIST_FIRST(&iolist); 587 while (p != NULL) { 588 q = p; 589 LIST_REMOVE(q, link); 590 free(p, M_WAITOK); 591 p = LIST_FIRST(&iolist); 592 } 593 p = LIST_FIRST(&memlist); 594 while (p != NULL) { 595 q = p; 596 LIST_REMOVE(q, link); 597 free(p, M_WAITOK); 598 p = LIST_FIRST(&memlist); 599 } 600 } 601 602 pcitag_t 603 pci_make_tag(pc, bus, device, function) 604 pci_chipset_tag_t pc; 605 int bus, device, function; 606 { 607 return ((bus << 16) | (device << 11) | (function << 8)); 608 } 609 610 int 611 pci_intr_map(pa, ihp) 612 struct pci_attach_args *pa; 613 pci_intr_handle_t *ihp; 614 { 615 int line = pa->pa_intrline; 616 617 /* 618 * According to the PCI-spec, 255 means `unknown' or `no connection'. 619 * Interpret this as 'no interrupt assigned'. 620 */ 621 if (line == 255) { 622 *ihp = -1; 623 return 1; 624 } 625 626 /* 627 * Values are pretty useless on the Hades since all interrupt 628 * lines for a card are tied together and hardwired to a 629 * specific TT-MFP I/O port. 630 */ 631 *ihp = line; 632 return 0; 633 } 634 635 const char * 636 pci_intr_string(pc, ih) 637 pci_chipset_tag_t pc; 638 pci_intr_handle_t ih; 639 { 640 static char irqstr[8]; /* 4 + 2 + NULL + sanity */ 641 642 if (ih == -1) 643 panic("pci_intr_string: bogus handle 0x%x\n", ih); 644 645 sprintf(irqstr, "irq %d", ih); 646 return (irqstr); 647 648 } 649 650 const struct evcnt * 651 pci_intr_evcnt(pc, ih) 652 pci_chipset_tag_t pc; 653 pci_intr_handle_t ih; 654 { 655 656 /* XXX for now, no evcnt parent reported */ 657 return NULL; 658 } 659
Indexes created Wed Sep 24 05:09:52 GMT 2025