pci_tseng.c revision 1.1 1 /* $NetBSD: pci_tseng.c,v 1.1 1999/03/15 15:47:22 leo Exp $ */
2
3 /*
4 * Copyright (c) 1999 Leo Weppelman. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Leo Weppelman.
17 * 4. The name of the author may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 */
31 #include <sys/param.h>
32 #include <sys/queue.h>
33 #include <sys/systm.h>
34 #include <dev/pci/pcireg.h>
35 #include <dev/pci/pcivar.h>
36 #include <dev/pci/pcidevs.h>
37 #include <atari/pci/pci_vga.h>
38 #include <atari/dev/grf_etreg.h>
39
40 #define PCI_LINMEMBASE 0x0e000000
41 #define PCI_IOBASE 0x800
42
43 static void et6000_init(volatile u_char *, u_char *);
44
45 /*
46 * Use tables for the card init...
47 */
48 static u_char seq_tab[] = {
49 0x03, 0x01, 0x03, 0x00, 0x02, 0x00, 0x00, 0x00 };
50
51 static u_char gfx_tab[] = {
52 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x06, 0x0f, 0xff };
53
54 static u_char attr_tab[] = {
55 0x0a, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00 };
56
57 static u_char crt_tab[] = {
58 0x60, 0x53, 0x4f, 0x94, 0x56, 0x05, 0xc1, 0x1f,
59 0x00, 0x4f, 0x00, 0x0f, 0x00, 0x00, 0x07, 0x80,
60 0x98, 0x3d, 0x8f, 0x28, 0x0f, 0x8f, 0xc2, 0xa3,
61 0xff, 0x3d, 0x8f, 0x28, 0x0f, 0x8f, 0xc2, 0xa3,
62 0x60, 0x08, 0x00, 0x00, 0x56, 0x05, 0xc1, 0x1f,
63 0x00, 0x4f, 0x00, 0x0f, 0x00, 0x00, 0x07, 0x80,
64 0x85, 0x01, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
65 0x05, 0x01, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00 };
66
67 void
68 tseng_init(pc, tag, id, ba, fb)
69 pci_chipset_tag_t pc;
70 pcitag_t tag;
71 int id;
72 volatile u_char *ba;
73 u_char *fb;
74 {
75 int i, csr;
76 int is_et6000 = 0;
77
78 is_et6000 = (id == PCI_PRODUCT_TSENG_ET6000) ? 1 : 0;
79
80 /* Turn on the card */
81 pci_conf_write(pc, tag, PCI_MAPREG_START, PCI_LINMEMBASE);
82 if (is_et6000)
83 pci_conf_write(pc, tag, PCI_MAPREG_START+4,
84 PCI_IOBASE | PCI_MAPREG_TYPE_IO);
85 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
86 csr |= (PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_IO_ENABLE);
87 csr |= PCI_COMMAND_MASTER_ENABLE;
88 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
89
90 if (is_et6000)
91 et6000_init(ba, fb);
92
93 vgaw(ba, GREG_MISC_OUTPUT_W, 0x63);
94 vgaw(ba, GREG_VIDEOSYSENABLE, 0x01);
95 WCrt(ba, 0x17 , 0x00); /* color */
96 WCrt(ba, 0x11 , 0x00); /* color */
97 vgaw(ba, VDAC_MASK , 0xff);
98 WSeq(ba, SEQ_ID_RESET , 0x00);
99 vgaw(ba, GREG_HERCULESCOMPAT, 0x03);
100 vgaw(ba, GREG_DISPMODECONTROL, 0xa0);
101
102 /* Load sequencer */
103 for (i = 1; i < 8; i++)
104 WSeq(ba, i, seq_tab[i]);
105 WSeq(ba, SEQ_ID_RESET , 0x03);
106
107 vgar(ba, VDAC_ADDRESS); /* clear old state */
108 vgar(ba, VDAC_MASK);
109 vgar(ba, VDAC_MASK);
110 vgar(ba, VDAC_MASK);
111 vgar(ba, VDAC_MASK);
112 vgaw(ba, VDAC_MASK, 0); /* set to palette */
113 vgar(ba, VDAC_ADDRESS); /* clear state */
114 vgaw(ba, VDAC_MASK, 0xff);
115
116 /*
117 * Make sure we're allowed to write all crt-registers
118 */
119 WCrt(ba, CRT_ID_END_VER_RETR, (RCrt(ba, CRT_ID_END_VER_RETR) & 0x7f));
120
121 /* CRT registers */
122 for (i = 0; i < 0x3e; i++)
123 WCrt(ba, i, crt_tab[i]);
124
125 /* GCT registers */
126 for (i = 0; i < 0x09; i++)
127 WGfx(ba, i, gfx_tab[i]);
128
129 for (i = 0; i < 0x10; i++)
130 WAttr(ba, i, i);
131 for (; i < 0x18; i++)
132 WAttr(ba, i, attr_tab[i - 0x10]);
133 WAttr(ba, 0x20, 0);
134 }
135
136 /*
137 * Initialize the et6000 specific (PCI) registers. Try to do it like the
138 * video-bios would have done it, so things like Xservers get what they
139 * expect. Most info was kindly provided by Koen Gadeyne.
140 */
141
142 static void
143 et6000_init(ba, fb)
144 volatile u_char *ba;
145 u_char *fb;
146 {
147
148 int i;
149 u_char dac_tab[] = { 0x7d,0x67, 0x5d,0x64, 0x56,0x63,
150 0x28,0x22, 0x79,0x49, 0x6f,0x47,
151 0x28,0x41, 0x6b,0x44, 0x00,0x00,
152 0x00,0x00, 0x5d,0x25, 0x00,0x00,
153 0x00,0x00, 0x00,0x96 };
154
155 ba += 0x800;
156
157
158 ba[0x40] = 0x06; /* Use standard vga addressing */
159 ba[0x41] = 0x2a; /* Performance control */
160 ba[0x43] = 0x02; /* XCLK/SCLK config */
161 ba[0x44] = 0x11; /* RAS/CAS config */
162 ba[0x46] = 0x00; /* CRT display feature */
163 ba[0x47] = 0x10;
164 ba[0x58] = 0x00; /* Video Control 1 */
165 ba[0x59] = 0x04; /* Video Control 2 */
166
167 /*
168 * Setup a 'standard' CLKDAC
169 */
170 ba[0x42] = 0x00; /* MCLK == CLK0 */
171 ba[0x67] = 0x00; /* Start filling from dac-reg 0 and up... */
172 for (i = 0; i < 0x16; i++)
173 ba[0x69] = dac_tab[i];
174
175 if (ba[8] == 0x70) { /* et6100, right? */
176 volatile u_char *ma = (volatile u_char *)fb;
177 u_char bv;
178
179 /*
180 * XXX Black magic to get the bloody MDRAM's to function...
181 * XXX _Only_ tested on my card! [leo]
182 */
183 bv = ba[45];
184 ba[0x45] = bv | 0x40; /* Reset MDRAM's */
185 ba[0x45] = bv | 0x70; /* Program latency value */
186 ma[0x0] = 0; /* Yeah, right :-( */
187 ba[0x45] = bv; /* Back to normal */
188 ba[0x44] = 0x14; /* RAS/CAS config */
189 }
190 }
191