pci_tseng.c revision 1.6
1 /* $NetBSD: pci_tseng.c,v 1.6 2003/02/02 18:12:59 thomas Exp $ */ 2 3 /* 4 * Copyright (c) 1999 Leo Weppelman. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Leo Weppelman. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 #include <sys/param.h> 32 #include <sys/queue.h> 33 #include <sys/systm.h> 34 #include <dev/pci/pcireg.h> 35 #include <dev/pci/pcivar.h> 36 #include <dev/pci/pcidevs.h> 37 #include <atari/pci/pci_vga.h> 38 #include <atari/dev/grf_etreg.h> 39 40 #define PCI_LINMEMBASE 0x0e000000 41 #define PCI_IOBASE 0x800 42 43 static void et6000_init(volatile u_char *, u_char *, int); 44 45 /* 46 * Use tables for the card init... 47 */ 48 static u_char seq_tab[] = { 49 0x03, 0x01, 0x03, 0x00, 0x02, 0x00, 0x00, 0xb4 }; 50 51 static u_char gfx_tab[] = { 52 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0e, 0x0f, 0xff }; 53 54 static u_char attr_tab[] = { 55 0x0a, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00 }; 56 57 static u_char crt_tab[] = { 58 0x60, 0x53, 0x4f, 0x94, 0x56, 0x05, 0xc1, 0x1f, 59 0x00, 0x4f, 0x00, 0x0f, 0x00, 0x00, 0x07, 0x80, 60 0x98, 0x3d, 0x8f, 0x28, 0x0f, 0x8f, 0xc2, 0xa3, 61 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 62 0x00, 0x00, 0x00, 0x00, 0x56, 0x00, 0x00, 0x00, 63 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 64 #ifdef ET4000_HAS_2MB_MEM 65 0x00, 0x80, 0xa0, 0x00, 0x00, 0x10, 0x03, 0x89, /* 2 MB video memory */ 66 #else 67 0x00, 0x80, 0x28, 0x00, 0x00, 0x10, 0x43, 0x09, /* 1 MB video memory */ 68 #endif 69 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; 70 71 static u_char ras_cas_tab[] = { 72 0x11, 0x14, 0x15 }; 73 74 void 75 tseng_init(pc, tag, id, ba, fb) 76 pci_chipset_tag_t pc; 77 pcitag_t tag; 78 int id; 79 volatile u_char *ba; 80 u_char *fb; 81 { 82 int i, j, csr; 83 int is_et6000 = 0; 84 85 is_et6000 = (id == PCI_PRODUCT_TSENG_ET6000) ? 1 : 0; 86 87 /* Turn on the card */ 88 pci_conf_write(pc, tag, PCI_MAPREG_START, PCI_LINMEMBASE); 89 if (is_et6000) 90 pci_conf_write(pc, tag, PCI_MAPREG_START+4, 91 PCI_IOBASE | PCI_MAPREG_TYPE_IO); 92 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 93 csr |= (PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_IO_ENABLE); 94 csr |= PCI_COMMAND_MASTER_ENABLE; 95 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 96 97 if (is_et6000) { 98 /* 99 * The et6[01]000 cards have MDRAM chips. The 100 * timeing to those chips is not properly initialized 101 * by the card on init. The way to determine the 102 * values is not documented either :-( So that's why 103 * all this mess below (and in et6000_init().... 104 */ 105 for (i = 0; i < sizeof(ras_cas_tab); i++) { 106 et6000_init(ba, fb, i); 107 for (j = 0; j < 32; j++) 108 fb[j] = j; 109 for (j = 0; j < 32; j++) 110 if (fb[j] != j) 111 break; 112 if (j == 32) 113 break; 114 } 115 } 116 117 vgaw(ba, GREG_MISC_OUTPUT_W, 0x63); 118 vgaw(ba, GREG_VIDEOSYSENABLE, 0x01); 119 WCrt(ba, 0x17 , 0x00); /* color */ 120 WCrt(ba, 0x11 , 0x00); /* color */ 121 vgaw(ba, VDAC_MASK , 0xff); 122 WSeq(ba, SEQ_ID_RESET , 0x00); 123 vgaw(ba, GREG_HERCULESCOMPAT, 0x03); 124 vgaw(ba, GREG_DISPMODECONTROL, 0xa0); 125 126 /* Load sequencer */ 127 for (i = 1; i < 8; i++) 128 WSeq(ba, i, seq_tab[i]); 129 WSeq(ba, SEQ_ID_RESET , 0x03); 130 131 vgar(ba, VDAC_ADDRESS); /* clear old state */ 132 vgar(ba, VDAC_MASK); 133 vgar(ba, VDAC_MASK); 134 vgar(ba, VDAC_MASK); 135 vgar(ba, VDAC_MASK); 136 vgaw(ba, VDAC_MASK, 0); /* set to palette */ 137 vgar(ba, VDAC_ADDRESS); /* clear state */ 138 vgaw(ba, VDAC_MASK, 0xff); 139 140 /* 141 * Make sure we're allowed to write all crt-registers 142 */ 143 WCrt(ba, CRT_ID_END_VER_RETR, (RCrt(ba, CRT_ID_END_VER_RETR) & 0x7f)); 144 145 /* CRT registers */ 146 for (i = 0; i < 0x3e; i++) 147 WCrt(ba, i, crt_tab[i]); 148 149 /* GCT registers */ 150 for (i = 0; i < 0x09; i++) 151 WGfx(ba, i, gfx_tab[i]); 152 153 for (i = 0; i < 0x10; i++) 154 WAttr(ba, i, i); 155 for (; i < 0x18; i++) 156 WAttr(ba, i, attr_tab[i - 0x10]); 157 WAttr(ba, 0x20, 0); 158 } 159 160 /* 161 * Initialize the et6000 specific (PCI) registers. Try to do it like the 162 * video-bios would have done it, so things like Xservers get what they 163 * expect. Most info was kindly provided by Koen Gadeyne. 164 */ 165 166 static void 167 et6000_init(ba, fb, iter) 168 volatile u_char *ba; 169 u_char *fb; 170 int iter; 171 { 172 173 int i; 174 u_char dac_tab[] = { 0x7d,0x67, 0x5d,0x64, 0x56,0x63, 175 0x28,0x22, 0x79,0x49, 0x6f,0x47, 176 0x28,0x41, 0x6b,0x44, 0x00,0x00, 177 0x00,0x00, 0x5d,0x25, 0x00,0x00, 178 0x00,0x00, 0x00,0x96 }; 179 180 ba += 0x800; 181 182 183 ba[0x40] = 0x06; /* Use standard vga addressing */ 184 ba[0x41] = 0x2a; /* Performance control */ 185 ba[0x43] = 0x02; /* XCLK/SCLK config */ 186 ba[0x44] = ras_cas_tab[iter]; /* RAS/CAS config */ 187 ba[0x46] = 0x00; /* CRT display feature */ 188 ba[0x47] = 0x10; 189 ba[0x58] = 0x00; /* Video Control 1 */ 190 ba[0x59] = 0x04; /* Video Control 2 */ 191 192 /* 193 * Setup a 'standard' CLKDAC 194 */ 195 ba[0x42] = 0x00; /* MCLK == CLK0 */ 196 ba[0x67] = 0x00; /* Start filling from dac-reg 0 and up... */ 197 for (i = 0; i < 0x16; i++) 198 ba[0x69] = dac_tab[i]; 199 200 if (ba[8] == 0x70) { /* et6100, right? */ 201 volatile u_char *ma = (volatile u_char *)fb; 202 u_char bv; 203 204 /* 205 * XXX Black magic to get the bloody MDRAM's to function... 206 * XXX _Only_ tested on my card! [leo] 207 */ 208 bv = ba[45]; 209 ba[0x45] = bv | 0x40; /* Reset MDRAM's */ 210 ba[0x45] = bv | 0x70; /* Program latency value */ 211 ma[0x0] = 0; /* Yeah, right :-( */ 212 ba[0x45] = bv; /* Back to normal */ 213 } 214 } 215
Indexes created Wed Oct 01 18:09:54 GMT 2025