et4000.c revision 1.3
1 /* $NetBSD: et4000.c,v 1.3 1999/03/31 10:44:15 leo Exp $ */ 2 /*- 3 * Copyright (c) 1998 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Julian Coleman. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the NetBSD 20 * Foundation, Inc. and its contributors. 21 * 4. Neither the name of The NetBSD Foundation nor the names of its 22 * contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 26 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Thanks to: 40 * Leo Weppelman 41 * 'Maximum Entropy' 42 * Thomas Gerner 43 * Juergen Orscheidt 44 * for their help and for code that I could refer to when writing this driver. 45 * 46 * Defining DEBUG_ET4000 will cause the driver to *always* attach. Use for 47 * debugging register settings. 48 */ 49 50 /* 51 #define DEBUG_ET4000 52 */ 53 54 #include <sys/param.h> 55 #include <sys/ioctl.h> 56 #include <sys/queue.h> 57 #include <sys/malloc.h> 58 #include <sys/device.h> 59 #include <sys/systm.h> 60 #include <sys/conf.h> 61 #include <atari/vme/vmevar.h> 62 63 #include <machine/iomap.h> 64 #include <machine/video.h> 65 #include <machine/mfp.h> 66 #include <machine/cpu.h> 67 #include <atari/atari/device.h> 68 #include <atari/dev/grfioctl.h> 69 #include <atari/dev/grf_etreg.h> 70 71 /* 72 * Allow a 8Kb io-region and a 1MB frame buffer to be mapped. This 73 * is more or less required by the XFree server. The X server also 74 * requires that the frame buffer be mapped above 0x3fffff. 75 */ 76 #define REG_MAPPABLE (8 * 1024) /* 0x2000 */ 77 #define FRAME_MAPPABLE (1 * 1024 * 1024) /* 0x100000 */ 78 #define FRAME_BASE (4 * 1024 * 1024) /* 0x400000 */ 79 #define VGA_MAPPABLE (128 * 1024) /* 0x20000 */ 80 #define VGA_BASE 0xa0000 81 82 static int et_vme_match __P((struct device *, struct cfdata *, void *)); 83 static void et_vme_attach __P((struct device *, struct device *, void *)); 84 static int et_probe_addresses __P((struct vme_attach_args *)); 85 static void et_start __P((bus_space_tag_t *, bus_space_handle_t *, int *, 86 u_char *)); 87 static void et_stop __P((bus_space_tag_t *, bus_space_handle_t *, int *, 88 u_char *)); 89 static int et_detect __P((bus_space_tag_t *, bus_space_tag_t *, 90 bus_space_handle_t *, bus_space_handle_t *, u_int)); 91 92 dev_decl(et,open); 93 dev_decl(et,close); 94 dev_decl(et,read); 95 dev_decl(et,write); 96 dev_decl(et,ioctl); 97 dev_decl(et,mmap); 98 99 int eton __P((dev_t)); 100 int etoff __P((dev_t)); 101 102 /* Register and screen memory addresses for ET4000 based VME cards */ 103 static struct et_addresses { 104 u_long io_addr; 105 u_long io_size; 106 u_long mem_addr; 107 u_long mem_size; 108 } etstd[] = { 109 { 0xfebf0000, REG_MAPPABLE, 0xfec00000, FRAME_MAPPABLE }, /* Crazy Dots VME & II */ 110 { 0xfed00000, REG_MAPPABLE, 0xfec00000, FRAME_MAPPABLE }, /* Spektrum I & HC */ 111 { 0xfed80000, REG_MAPPABLE, 0xfec00000, FRAME_MAPPABLE } /* Spektrum TC */ 112 }; 113 114 #define NETSTD (sizeof(etstd) / sizeof(etstd[0])) 115 116 struct grfabs_et_priv { 117 volatile caddr_t regkva; 118 volatile caddr_t memkva; 119 int regsz; 120 int memsz; 121 } et_priv; 122 123 struct et_softc { 124 struct device sc_dev; 125 bus_space_tag_t sc_iot; 126 bus_space_tag_t sc_memt; 127 bus_space_handle_t sc_ioh; 128 bus_space_handle_t sc_memh; 129 int sc_flags; 130 int sc_iobase; 131 int sc_maddr; 132 int sc_iosize; 133 int sc_msize; 134 }; 135 136 #define ET_SC_FLAGS_INUSE 1 137 138 struct cfattach et_ca = { 139 sizeof(struct et_softc), et_vme_match, et_vme_attach 140 }; 141 142 extern struct cfdriver et_cd; 143 144 /* 145 * Look for a ET4000 (Crazy Dots) card on the VME bus. We might 146 * match Spektrum cards too (untested). 147 */ 148 int 149 et_vme_match(pdp, cfp, auxp) 150 struct device *pdp; 151 struct cfdata *cfp; 152 void *auxp; 153 { 154 struct vme_attach_args *va = auxp; 155 156 return(et_probe_addresses(va)); 157 } 158 159 static int 160 et_probe_addresses(va) 161 struct vme_attach_args *va; 162 { 163 int i, found = 0; 164 bus_space_tag_t iot; 165 bus_space_tag_t memt; 166 bus_space_handle_t ioh; 167 bus_space_handle_t memh; 168 169 iot = va->va_iot; 170 memt = va->va_memt; 171 172 /* Loop around our possible addresses looking for a match */ 173 for (i = 0; i < NETSTD; i++) { 174 struct et_addresses *et_ap = &etstd[i]; 175 struct vme_attach_args vat = *va; 176 177 if (vat.va_irq != VMECF_IRQ_DEFAULT) { 178 printf("et probe: config error: no irq support\n"); 179 return(0); 180 } 181 if (vat.va_iobase == VMECF_IOPORT_DEFAULT) 182 vat.va_iobase = et_ap->io_addr; 183 if (vat.va_maddr == VMECF_MEM_DEFAULT) 184 vat.va_maddr = et_ap->mem_addr; 185 if (vat.va_iosize == VMECF_IOSIZE_DEFAULT) 186 vat.va_iosize = et_ap->io_size; 187 if (vat.va_msize == VMECF_MEMSIZ_DEFAULT) 188 vat.va_msize = et_ap->mem_size; 189 if (bus_space_map(iot, vat.va_iobase, vat.va_iosize, 0, 190 &ioh)) { 191 printf("et probe: cannot map io area\n"); 192 return(0); 193 } 194 if (bus_space_map(memt, vat.va_maddr, vat.va_msize, 195 BUS_SPACE_MAP_LINEAR|BUS_SPACE_MAP_CACHEABLE, 196 &memh)) { 197 bus_space_unmap(iot, (caddr_t)vat.va_iobase, 198 vat.va_iosize); 199 printf("et probe: cannot map memory area\n"); 200 return(0); 201 } 202 found = et_detect(&iot, &memt, &ioh, &memh, vat.va_msize); 203 bus_space_unmap(iot, (caddr_t)vat.va_iobase, vat.va_iosize); 204 bus_space_unmap(memt, (caddr_t)vat.va_maddr, vat.va_msize); 205 if (found) { 206 *va = vat; 207 return(1); 208 } 209 } 210 return(0); 211 } 212 213 static void 214 et_start(iot, ioh, vgabase, saved) 215 bus_space_tag_t *iot; 216 bus_space_handle_t *ioh; 217 int *vgabase; 218 u_char *saved; 219 { 220 /* Enable VGA */ 221 bus_space_write_1(*iot, *ioh, GREG_VIDEOSYSENABLE, 0x01); 222 /* Check whether colour (base = 3d0) or mono (base = 3b0) mode */ 223 *vgabase = (bus_space_read_1(*iot, *ioh, GREG_MISC_OUTPUT_R) & 0x01) 224 ? 0x3d0 : 0x3b0; 225 /* Enable 'Tseng Extensions' - writes to CRTC and ATC[16] */ 226 bus_space_write_1(*iot, *ioh, GREG_HERCULESCOMPAT, 0x03); 227 bus_space_write_1(*iot, *ioh, *vgabase + 0x08, 0xa0); 228 /* Set up 16 bit I/O, memory, Tseng addressing and linear mapping */ 229 bus_space_write_1(*iot, *ioh, *vgabase + 0x04, 0x36); 230 bus_space_write_1(*iot, *ioh, *vgabase + 0x05, 0xf0); 231 /* Enable writes to CRTC[0..7] */ 232 bus_space_write_1(*iot, *ioh, *vgabase + 0x04, 0x11); 233 *saved = bus_space_read_1(*iot, *ioh, *vgabase + 0x05); 234 bus_space_write_1(*iot, *ioh, *vgabase + 0x05, *saved & 0x7f); 235 /* Map all memory for video modes */ 236 bus_space_write_1(*iot, *ioh, 0x3ce, 0x06); 237 bus_space_write_1(*iot, *ioh, 0x3cf, 0x01); 238 } 239 240 static void 241 et_stop(iot, ioh, vgabase, saved) 242 bus_space_tag_t *iot; 243 bus_space_handle_t *ioh; 244 int *vgabase; 245 u_char *saved; 246 { 247 /* Restore writes to CRTC[0..7] */ 248 bus_space_write_1(*iot, *ioh, *vgabase + 0x04, 0x11); 249 *saved = bus_space_read_1(*iot, *ioh, *vgabase + 0x05); 250 bus_space_write_1(*iot, *ioh, *vgabase + 0x05, *saved | 0x80); 251 /* Disable 'Tseng Extensions' */ 252 bus_space_write_1(*iot, *ioh, *vgabase + 0x08, 0x00); 253 bus_space_write_1(*iot, *ioh, GREG_DISPMODECONTROL, 0x29); 254 bus_space_write_1(*iot, *ioh, GREG_HERCULESCOMPAT, 0x01); 255 } 256 257 static int 258 et_detect(iot, memt, ioh, memh, memsize) 259 bus_space_tag_t *iot, *memt; 260 bus_space_handle_t *ioh, *memh; 261 u_int memsize; 262 { 263 u_char orig, new, saved; 264 int vgabase; 265 266 /* Test accessibility of registers and memory */ 267 if(!bus_space_peek_1(*iot, *ioh, GREG_STATUS1_R)) 268 return(0); 269 if(!bus_space_peek_1(*memt, *memh, 0)) 270 return(0); 271 272 et_start(iot, ioh, &vgabase, &saved); 273 274 /* Is the card a Tseng card? Check read/write of ATC[16] */ 275 (void)bus_space_read_1(*iot, *ioh, vgabase + 0x0a); 276 bus_space_write_1(*iot, *ioh, ACT_ADDRESS, 0x16 | 0x20); 277 orig = bus_space_read_1(*iot, *ioh, ACT_ADDRESS_R); 278 bus_space_write_1(*iot, *ioh, ACT_ADDRESS_W, (orig ^ 0x10)); 279 bus_space_write_1(*iot, *ioh, ACT_ADDRESS, 0x16 | 0x20); 280 new = bus_space_read_1(*iot, *ioh, ACT_ADDRESS_R); 281 bus_space_write_1(*iot, *ioh, ACT_ADDRESS, orig); 282 if (new != (orig ^ 0x10)) { 283 #ifdef DEBUG_ET4000 284 printf("et4000: ATC[16] failed (%x != %x)\n", 285 new, (orig ^ 0x10)); 286 #else 287 et_stop(iot, ioh, &vgabase, &saved); 288 return(0); 289 #endif 290 } 291 /* Is the card and ET4000? Check read/write of CRTC[33] */ 292 bus_space_write_1(*iot, *ioh, vgabase + 0x04, 0x33); 293 orig = bus_space_read_1(*iot, *ioh, vgabase + 0x05); 294 bus_space_write_1(*iot, *ioh, vgabase + 0x05, (orig ^ 0x0f)); 295 new = bus_space_read_1(*iot, *ioh, vgabase + 0x05); 296 bus_space_write_1(*iot, *ioh, vgabase + 0x05, orig); 297 if (new != (orig ^ 0x0f)) { 298 #ifdef DEBUG_ET4000 299 printf("et4000: CRTC[33] failed (%x != %x)\n", 300 new, (orig ^ 0x0f)); 301 #else 302 et_stop(iot, ioh, &vgabase, &saved); 303 return(0); 304 #endif 305 } 306 307 /* Set up video memory so we can read & write it */ 308 bus_space_write_1(*iot, *ioh, 0x3c4, 0x04); 309 bus_space_write_1(*iot, *ioh, 0x3c5, 0x06); 310 bus_space_write_1(*iot, *ioh, 0x3c4, 0x07); 311 bus_space_write_1(*iot, *ioh, 0x3c5, 0xa8); 312 bus_space_write_1(*iot, *ioh, 0x3ce, 0x01); 313 bus_space_write_1(*iot, *ioh, 0x3cf, 0x00); 314 bus_space_write_1(*iot, *ioh, 0x3ce, 0x03); 315 bus_space_write_1(*iot, *ioh, 0x3cf, 0x00); 316 bus_space_write_1(*iot, *ioh, 0x3ce, 0x05); 317 bus_space_write_1(*iot, *ioh, 0x3cf, 0x40); 318 319 #define TEST_PATTERN 0xa5a5a5a5 320 321 bus_space_write_4(*memt, *memh, 0x0, TEST_PATTERN); 322 if (bus_space_read_4(*memt, *memh, 0x0) != TEST_PATTERN) 323 { 324 #ifdef DEBUG_ET4000 325 printf("et4000: Video base write/read failed\n"); 326 #else 327 et_stop(iot, ioh, &vgabase, &saved); 328 return(0); 329 #endif 330 } 331 bus_space_write_4(*memt, *memh, memsize - 4, TEST_PATTERN); 332 if (bus_space_read_4(*memt, *memh, memsize - 4) != TEST_PATTERN) 333 { 334 #ifdef DEBUG_ET4000 335 printf("et4000: Video top write/read failed\n"); 336 #else 337 et_stop(iot, ioh, &vgabase, &saved); 338 return(0); 339 #endif 340 } 341 342 et_stop(iot, ioh, &vgabase, &saved); 343 return(1); 344 } 345 346 static void 347 et_vme_attach(parent, self, aux) 348 struct device *parent, *self; 349 void *aux; 350 { 351 struct et_softc *sc = (struct et_softc *)self; 352 struct vme_attach_args *va = aux; 353 bus_space_handle_t ioh; 354 bus_space_handle_t memh; 355 356 printf("\n"); 357 358 if (bus_space_map(va->va_iot, va->va_iobase, va->va_iosize, 0, &ioh)) 359 panic("et attach: cannot map io area\n"); 360 if (bus_space_map(va->va_memt, va->va_maddr, va->va_msize, 0, &memh)) 361 panic("et attach: cannot map mem area\n"); 362 363 sc->sc_iot = va->va_iot; 364 sc->sc_ioh = ioh; 365 sc->sc_memt = va->va_memt; 366 sc->sc_memh = memh; 367 sc->sc_flags = 0; 368 sc->sc_iobase = va->va_iobase; 369 sc->sc_maddr = va->va_maddr; 370 sc->sc_iosize = va->va_iosize; 371 sc->sc_msize = va->va_msize; 372 373 et_priv.regkva = (volatile caddr_t)ioh; 374 et_priv.memkva = (volatile caddr_t)memh; 375 et_priv.regsz = va->va_iosize; 376 et_priv.memsz = va->va_msize; 377 } 378 379 int 380 etopen(dev, flags, devtype, p) 381 dev_t dev; 382 int flags, devtype; 383 struct proc *p; 384 { 385 struct et_softc *sc; 386 387 if (minor(dev) >= et_cd.cd_ndevs) 388 return(ENXIO); 389 sc = et_cd.cd_devs[minor(dev)]; 390 if (sc->sc_flags & ET_SC_FLAGS_INUSE) 391 return(EBUSY); 392 sc->sc_flags |= ET_SC_FLAGS_INUSE; 393 return(0); 394 } 395 396 int 397 etclose(dev, flags, devtype, p) 398 dev_t dev; 399 int flags, devtype; 400 struct proc *p; 401 { 402 struct et_softc *sc; 403 404 /* 405 * XXX: Should we reset to a default mode? 406 */ 407 sc = et_cd.cd_devs[minor(dev)]; 408 sc->sc_flags &= ~ET_SC_FLAGS_INUSE; 409 return(0); 410 } 411 412 int 413 etread(dev, uio, flags) 414 dev_t dev; 415 struct uio *uio; 416 int flags; 417 { 418 return(EINVAL); 419 } 420 421 int 422 etwrite(dev, uio, flags) 423 dev_t dev; 424 struct uio *uio; 425 int flags; 426 { 427 return(EINVAL); 428 } 429 430 int 431 etioctl(dev, cmd, data, flags, p) 432 dev_t dev; 433 u_long cmd; 434 caddr_t data; 435 int flags; 436 struct proc *p; 437 { 438 struct grfinfo g_display; 439 struct et_softc *sc; 440 441 sc = et_cd.cd_devs[minor(dev)]; 442 switch (cmd) { 443 case GRFIOCON: 444 return(0); 445 break; 446 case GRFIOCOFF: 447 return(0); 448 break; 449 case GRFIOCGINFO: 450 g_display.gd_fbaddr = (caddr_t) (sc->sc_maddr); 451 g_display.gd_fbsize = sc->sc_msize; 452 g_display.gd_linbase = FRAME_BASE; 453 g_display.gd_regaddr = (caddr_t) (sc->sc_iobase); 454 g_display.gd_regsize = sc->sc_iosize; 455 g_display.gd_vgaaddr = (caddr_t) (sc->sc_maddr); 456 g_display.gd_vgasize = VGA_MAPPABLE; 457 g_display.gd_vgabase = VGA_BASE; 458 g_display.gd_colors = 16; 459 g_display.gd_planes = 4; 460 g_display.gd_fbwidth = 640; /* XXX: should be 'unknown' */ 461 g_display.gd_fbheight = 400; /* XXX: should be 'unknown' */ 462 g_display.gd_fbx = 0; 463 g_display.gd_fby = 0; 464 g_display.gd_dwidth = 0; 465 g_display.gd_dheight = 0; 466 g_display.gd_dx = 0; 467 g_display.gd_dy = 0; 468 g_display.gd_bank_size = 0; 469 bcopy((caddr_t)&g_display, data, sizeof(struct grfinfo)); 470 break; 471 case GRFIOCMAP: 472 return(EINVAL); 473 break; 474 case GRFIOCUNMAP: 475 return(EINVAL); 476 break; 477 default: 478 return(EINVAL); 479 break; 480 } 481 return(0); 482 } 483 484 int 485 etmmap(dev, offset, prot) 486 dev_t dev; 487 int offset, prot; 488 { 489 struct et_softc *sc; 490 491 sc = et_cd.cd_devs[minor(dev)]; 492 493 /* 494 * control registers 495 * mapped from offset 0x0 to REG_MAPPABLE 496 */ 497 if (offset >= 0 && offset <= sc->sc_iosize) 498 return(m68k_btop(sc->sc_iobase + offset)); 499 500 /* 501 * VGA memory 502 * mapped from offset 0xa0000 to 0xc0000 503 */ 504 if (offset >= VGA_BASE && offset < (VGA_MAPPABLE + VGA_BASE)) 505 return(m68k_btop(sc->sc_maddr + offset - VGA_BASE)); 506 507 /* 508 * frame buffer 509 * mapped from offset 0x400000 to 0x4fffff 510 */ 511 if (offset >= FRAME_BASE && offset < sc->sc_msize + FRAME_BASE) 512 return(m68k_btop(sc->sc_maddr + offset - FRAME_BASE)); 513 514 return(-1); 515 } 516 517 int 518 eton(dev) 519 dev_t dev; 520 { 521 struct et_softc *sc; 522 523 if (minor(dev) >= et_cd.cd_ndevs) 524 return(ENXIO); 525 sc = et_cd.cd_devs[minor(dev)]; 526 if (!sc) 527 return(ENXIO); 528 return(0); 529 } 530 531 int 532 etoff(dev) 533 dev_t dev; 534 { 535 return(0); 536 } 537 538
Indexes created Mon Sep 29 21:09:56 GMT 2025