et4000.c revision 1.9
1 /* $NetBSD: et4000.c,v 1.9 2002/10/02 05:04:27 thorpej Exp $ */ 2 /*- 3 * Copyright (c) 1998 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Julian Coleman. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the NetBSD 20 * Foundation, Inc. and its contributors. 21 * 4. Neither the name of The NetBSD Foundation nor the names of its 22 * contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 26 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Thanks to: 40 * Leo Weppelman 41 * 'Maximum Entropy' 42 * Thomas Gerner 43 * Juergen Orscheidt 44 * for their help and for code that I could refer to when writing this driver. 45 * 46 * Defining DEBUG_ET4000 will cause the driver to *always* attach. Use for 47 * debugging register settings. 48 */ 49 50 /* 51 #define DEBUG_ET4000 52 */ 53 54 #include <sys/param.h> 55 #include <sys/ioctl.h> 56 #include <sys/queue.h> 57 #include <sys/malloc.h> 58 #include <sys/device.h> 59 #include <sys/systm.h> 60 #include <sys/conf.h> 61 #include <atari/vme/vmevar.h> 62 63 #include <machine/iomap.h> 64 #include <machine/video.h> 65 #include <machine/mfp.h> 66 #include <machine/cpu.h> 67 #include <atari/atari/device.h> 68 #include <atari/dev/grfioctl.h> 69 #include <atari/dev/grf_etreg.h> 70 71 /* 72 * Allow a 8Kb io-region and a 1MB frame buffer to be mapped. This 73 * is more or less required by the XFree server. The X server also 74 * requires that the frame buffer be mapped above 0x3fffff. 75 */ 76 #define REG_MAPPABLE (8 * 1024) /* 0x2000 */ 77 #define FRAME_MAPPABLE (1 * 1024 * 1024) /* 0x100000 */ 78 #define FRAME_BASE (4 * 1024 * 1024) /* 0x400000 */ 79 #define VGA_MAPPABLE (128 * 1024) /* 0x20000 */ 80 #define VGA_BASE 0xa0000 81 82 static int et_vme_match __P((struct device *, struct cfdata *, void *)); 83 static void et_vme_attach __P((struct device *, struct device *, void *)); 84 static int et_probe_addresses __P((struct vme_attach_args *)); 85 static void et_start __P((bus_space_tag_t *, bus_space_handle_t *, int *, 86 u_char *)); 87 static void et_stop __P((bus_space_tag_t *, bus_space_handle_t *, int *, 88 u_char *)); 89 static int et_detect __P((bus_space_tag_t *, bus_space_tag_t *, 90 bus_space_handle_t *, bus_space_handle_t *, u_int)); 91 92 int eton __P((dev_t)); 93 int etoff __P((dev_t)); 94 95 /* Register and screen memory addresses for ET4000 based VME cards */ 96 static struct et_addresses { 97 u_long io_addr; 98 u_long io_size; 99 u_long mem_addr; 100 u_long mem_size; 101 } etstd[] = { 102 { 0xfebf0000, REG_MAPPABLE, 0xfec00000, FRAME_MAPPABLE }, /* Crazy Dots VME & II */ 103 { 0xfed00000, REG_MAPPABLE, 0xfec00000, FRAME_MAPPABLE }, /* Spektrum I & HC */ 104 { 0xfed80000, REG_MAPPABLE, 0xfec00000, FRAME_MAPPABLE } /* Spektrum TC */ 105 }; 106 107 #define NETSTD (sizeof(etstd) / sizeof(etstd[0])) 108 109 struct grfabs_et_priv { 110 volatile caddr_t regkva; 111 volatile caddr_t memkva; 112 int regsz; 113 int memsz; 114 } et_priv; 115 116 struct et_softc { 117 struct device sc_dev; 118 bus_space_tag_t sc_iot; 119 bus_space_tag_t sc_memt; 120 bus_space_handle_t sc_ioh; 121 bus_space_handle_t sc_memh; 122 int sc_flags; 123 int sc_iobase; 124 int sc_maddr; 125 int sc_iosize; 126 int sc_msize; 127 }; 128 129 #define ET_SC_FLAGS_INUSE 1 130 131 CFATTACH_DECL(et, sizeof(struct et_softc), 132 et_vme_match, et_vme_attach, NULL, NULL); 133 134 extern struct cfdriver et_cd; 135 136 dev_type_open(etopen); 137 dev_type_close(etclose); 138 dev_type_read(etread); 139 dev_type_write(etwrite); 140 dev_type_ioctl(etioctl); 141 dev_type_mmap(etmmap); 142 143 const struct cdevsw et_cdevsw = { 144 etopen, etclose, etread, etwrite, etioctl, 145 nostop, notty, nopoll, etmmap, 146 }; 147 148 /* 149 * Look for a ET4000 (Crazy Dots) card on the VME bus. We might 150 * match Spektrum cards too (untested). 151 */ 152 int 153 et_vme_match(pdp, cfp, auxp) 154 struct device *pdp; 155 struct cfdata *cfp; 156 void *auxp; 157 { 158 struct vme_attach_args *va = auxp; 159 160 return(et_probe_addresses(va)); 161 } 162 163 static int 164 et_probe_addresses(va) 165 struct vme_attach_args *va; 166 { 167 int i, found = 0; 168 bus_space_tag_t iot; 169 bus_space_tag_t memt; 170 bus_space_handle_t ioh; 171 bus_space_handle_t memh; 172 173 iot = va->va_iot; 174 memt = va->va_memt; 175 176 /* Loop around our possible addresses looking for a match */ 177 for (i = 0; i < NETSTD; i++) { 178 struct et_addresses *et_ap = &etstd[i]; 179 struct vme_attach_args vat = *va; 180 181 if (vat.va_irq != VMECF_IRQ_DEFAULT) { 182 printf("et probe: config error: no irq support\n"); 183 return(0); 184 } 185 if (vat.va_iobase == VMECF_IOPORT_DEFAULT) 186 vat.va_iobase = et_ap->io_addr; 187 if (vat.va_maddr == VMECF_MEM_DEFAULT) 188 vat.va_maddr = et_ap->mem_addr; 189 if (vat.va_iosize == VMECF_IOSIZE_DEFAULT) 190 vat.va_iosize = et_ap->io_size; 191 if (vat.va_msize == VMECF_MEMSIZ_DEFAULT) 192 vat.va_msize = et_ap->mem_size; 193 if (bus_space_map(iot, vat.va_iobase, vat.va_iosize, 0, 194 &ioh)) { 195 printf("et probe: cannot map io area\n"); 196 return(0); 197 } 198 if (bus_space_map(memt, vat.va_maddr, vat.va_msize, 199 BUS_SPACE_MAP_LINEAR|BUS_SPACE_MAP_CACHEABLE, 200 &memh)) { 201 bus_space_unmap(iot, ioh, vat.va_iosize); 202 printf("et probe: cannot map memory area\n"); 203 return(0); 204 } 205 found = et_detect(&iot, &memt, &ioh, &memh, vat.va_msize); 206 bus_space_unmap(iot, ioh, vat.va_iosize); 207 bus_space_unmap(memt, memh, vat.va_msize); 208 if (found) { 209 *va = vat; 210 return(1); 211 } 212 } 213 return(0); 214 } 215 216 static void 217 et_start(iot, ioh, vgabase, saved) 218 bus_space_tag_t *iot; 219 bus_space_handle_t *ioh; 220 int *vgabase; 221 u_char *saved; 222 { 223 /* Enable VGA */ 224 bus_space_write_1(*iot, *ioh, GREG_VIDEOSYSENABLE, 0x01); 225 /* Check whether colour (base = 3d0) or mono (base = 3b0) mode */ 226 *vgabase = (bus_space_read_1(*iot, *ioh, GREG_MISC_OUTPUT_R) & 0x01) 227 ? 0x3d0 : 0x3b0; 228 /* Enable 'Tseng Extensions' - writes to CRTC and ATC[16] */ 229 bus_space_write_1(*iot, *ioh, GREG_HERCULESCOMPAT, 0x03); 230 bus_space_write_1(*iot, *ioh, *vgabase + 0x08, 0xa0); 231 /* Set up 16 bit I/O, memory, Tseng addressing and linear mapping */ 232 bus_space_write_1(*iot, *ioh, *vgabase + 0x04, 0x36); 233 bus_space_write_1(*iot, *ioh, *vgabase + 0x05, 0xf0); 234 /* Enable writes to CRTC[0..7] */ 235 bus_space_write_1(*iot, *ioh, *vgabase + 0x04, 0x11); 236 *saved = bus_space_read_1(*iot, *ioh, *vgabase + 0x05); 237 bus_space_write_1(*iot, *ioh, *vgabase + 0x05, *saved & 0x7f); 238 /* Map all memory for video modes */ 239 bus_space_write_1(*iot, *ioh, 0x3ce, 0x06); 240 bus_space_write_1(*iot, *ioh, 0x3cf, 0x01); 241 } 242 243 static void 244 et_stop(iot, ioh, vgabase, saved) 245 bus_space_tag_t *iot; 246 bus_space_handle_t *ioh; 247 int *vgabase; 248 u_char *saved; 249 { 250 /* Restore writes to CRTC[0..7] */ 251 bus_space_write_1(*iot, *ioh, *vgabase + 0x04, 0x11); 252 *saved = bus_space_read_1(*iot, *ioh, *vgabase + 0x05); 253 bus_space_write_1(*iot, *ioh, *vgabase + 0x05, *saved | 0x80); 254 /* Disable 'Tseng Extensions' */ 255 bus_space_write_1(*iot, *ioh, *vgabase + 0x08, 0x00); 256 bus_space_write_1(*iot, *ioh, GREG_DISPMODECONTROL, 0x29); 257 bus_space_write_1(*iot, *ioh, GREG_HERCULESCOMPAT, 0x01); 258 } 259 260 static int 261 et_detect(iot, memt, ioh, memh, memsize) 262 bus_space_tag_t *iot, *memt; 263 bus_space_handle_t *ioh, *memh; 264 u_int memsize; 265 { 266 u_char orig, new, saved; 267 int vgabase; 268 269 /* Test accessibility of registers and memory */ 270 if(!bus_space_peek_1(*iot, *ioh, GREG_STATUS1_R)) 271 return(0); 272 if(!bus_space_peek_1(*memt, *memh, 0)) 273 return(0); 274 275 et_start(iot, ioh, &vgabase, &saved); 276 277 /* Is the card a Tseng card? Check read/write of ATC[16] */ 278 (void)bus_space_read_1(*iot, *ioh, vgabase + 0x0a); 279 bus_space_write_1(*iot, *ioh, ACT_ADDRESS, 0x16 | 0x20); 280 orig = bus_space_read_1(*iot, *ioh, ACT_ADDRESS_R); 281 bus_space_write_1(*iot, *ioh, ACT_ADDRESS_W, (orig ^ 0x10)); 282 bus_space_write_1(*iot, *ioh, ACT_ADDRESS, 0x16 | 0x20); 283 new = bus_space_read_1(*iot, *ioh, ACT_ADDRESS_R); 284 bus_space_write_1(*iot, *ioh, ACT_ADDRESS, orig); 285 if (new != (orig ^ 0x10)) { 286 #ifdef DEBUG_ET4000 287 printf("et4000: ATC[16] failed (%x != %x)\n", 288 new, (orig ^ 0x10)); 289 #else 290 et_stop(iot, ioh, &vgabase, &saved); 291 return(0); 292 #endif 293 } 294 /* Is the card and ET4000? Check read/write of CRTC[33] */ 295 bus_space_write_1(*iot, *ioh, vgabase + 0x04, 0x33); 296 orig = bus_space_read_1(*iot, *ioh, vgabase + 0x05); 297 bus_space_write_1(*iot, *ioh, vgabase + 0x05, (orig ^ 0x0f)); 298 new = bus_space_read_1(*iot, *ioh, vgabase + 0x05); 299 bus_space_write_1(*iot, *ioh, vgabase + 0x05, orig); 300 if (new != (orig ^ 0x0f)) { 301 #ifdef DEBUG_ET4000 302 printf("et4000: CRTC[33] failed (%x != %x)\n", 303 new, (orig ^ 0x0f)); 304 #else 305 et_stop(iot, ioh, &vgabase, &saved); 306 return(0); 307 #endif 308 } 309 310 /* Set up video memory so we can read & write it */ 311 bus_space_write_1(*iot, *ioh, 0x3c4, 0x04); 312 bus_space_write_1(*iot, *ioh, 0x3c5, 0x06); 313 bus_space_write_1(*iot, *ioh, 0x3c4, 0x07); 314 bus_space_write_1(*iot, *ioh, 0x3c5, 0xa8); 315 bus_space_write_1(*iot, *ioh, 0x3ce, 0x01); 316 bus_space_write_1(*iot, *ioh, 0x3cf, 0x00); 317 bus_space_write_1(*iot, *ioh, 0x3ce, 0x03); 318 bus_space_write_1(*iot, *ioh, 0x3cf, 0x00); 319 bus_space_write_1(*iot, *ioh, 0x3ce, 0x05); 320 bus_space_write_1(*iot, *ioh, 0x3cf, 0x40); 321 322 #define TEST_PATTERN 0xa5a5a5a5 323 324 bus_space_write_4(*memt, *memh, 0x0, TEST_PATTERN); 325 if (bus_space_read_4(*memt, *memh, 0x0) != TEST_PATTERN) 326 { 327 #ifdef DEBUG_ET4000 328 printf("et4000: Video base write/read failed\n"); 329 #else 330 et_stop(iot, ioh, &vgabase, &saved); 331 return(0); 332 #endif 333 } 334 bus_space_write_4(*memt, *memh, memsize - 4, TEST_PATTERN); 335 if (bus_space_read_4(*memt, *memh, memsize - 4) != TEST_PATTERN) 336 { 337 #ifdef DEBUG_ET4000 338 printf("et4000: Video top write/read failed\n"); 339 #else 340 et_stop(iot, ioh, &vgabase, &saved); 341 return(0); 342 #endif 343 } 344 345 et_stop(iot, ioh, &vgabase, &saved); 346 return(1); 347 } 348 349 static void 350 et_vme_attach(parent, self, aux) 351 struct device *parent, *self; 352 void *aux; 353 { 354 struct et_softc *sc = (struct et_softc *)self; 355 struct vme_attach_args *va = aux; 356 bus_space_handle_t ioh; 357 bus_space_handle_t memh; 358 359 printf("\n"); 360 361 if (bus_space_map(va->va_iot, va->va_iobase, va->va_iosize, 0, &ioh)) 362 panic("et attach: cannot map io area"); 363 if (bus_space_map(va->va_memt, va->va_maddr, va->va_msize, 0, &memh)) 364 panic("et attach: cannot map mem area"); 365 366 sc->sc_iot = va->va_iot; 367 sc->sc_ioh = ioh; 368 sc->sc_memt = va->va_memt; 369 sc->sc_memh = memh; 370 sc->sc_flags = 0; 371 sc->sc_iobase = va->va_iobase; 372 sc->sc_maddr = va->va_maddr; 373 sc->sc_iosize = va->va_iosize; 374 sc->sc_msize = va->va_msize; 375 376 et_priv.regkva = (volatile caddr_t)ioh; 377 et_priv.memkva = (volatile caddr_t)memh; 378 et_priv.regsz = va->va_iosize; 379 et_priv.memsz = va->va_msize; 380 } 381 382 int 383 etopen(dev, flags, devtype, p) 384 dev_t dev; 385 int flags, devtype; 386 struct proc *p; 387 { 388 struct et_softc *sc; 389 390 if (minor(dev) >= et_cd.cd_ndevs) 391 return(ENXIO); 392 sc = et_cd.cd_devs[minor(dev)]; 393 if (sc->sc_flags & ET_SC_FLAGS_INUSE) 394 return(EBUSY); 395 sc->sc_flags |= ET_SC_FLAGS_INUSE; 396 return(0); 397 } 398 399 int 400 etclose(dev, flags, devtype, p) 401 dev_t dev; 402 int flags, devtype; 403 struct proc *p; 404 { 405 struct et_softc *sc; 406 407 /* 408 * XXX: Should we reset to a default mode? 409 */ 410 sc = et_cd.cd_devs[minor(dev)]; 411 sc->sc_flags &= ~ET_SC_FLAGS_INUSE; 412 return(0); 413 } 414 415 int 416 etread(dev, uio, flags) 417 dev_t dev; 418 struct uio *uio; 419 int flags; 420 { 421 return(EINVAL); 422 } 423 424 int 425 etwrite(dev, uio, flags) 426 dev_t dev; 427 struct uio *uio; 428 int flags; 429 { 430 return(EINVAL); 431 } 432 433 int 434 etioctl(dev, cmd, data, flags, p) 435 dev_t dev; 436 u_long cmd; 437 caddr_t data; 438 int flags; 439 struct proc *p; 440 { 441 struct grfinfo g_display; 442 struct et_softc *sc; 443 444 sc = et_cd.cd_devs[minor(dev)]; 445 switch (cmd) { 446 case GRFIOCON: 447 return(0); 448 break; 449 case GRFIOCOFF: 450 return(0); 451 break; 452 case GRFIOCGINFO: 453 g_display.gd_fbaddr = (caddr_t) (sc->sc_maddr); 454 g_display.gd_fbsize = sc->sc_msize; 455 g_display.gd_linbase = FRAME_BASE; 456 g_display.gd_regaddr = (caddr_t) (sc->sc_iobase); 457 g_display.gd_regsize = sc->sc_iosize; 458 g_display.gd_vgaaddr = (caddr_t) (sc->sc_maddr); 459 g_display.gd_vgasize = VGA_MAPPABLE; 460 g_display.gd_vgabase = VGA_BASE; 461 g_display.gd_colors = 16; 462 g_display.gd_planes = 4; 463 g_display.gd_fbwidth = 640; /* XXX: should be 'unknown' */ 464 g_display.gd_fbheight = 400; /* XXX: should be 'unknown' */ 465 g_display.gd_fbx = 0; 466 g_display.gd_fby = 0; 467 g_display.gd_dwidth = 0; 468 g_display.gd_dheight = 0; 469 g_display.gd_dx = 0; 470 g_display.gd_dy = 0; 471 g_display.gd_bank_size = 0; 472 bcopy((caddr_t)&g_display, data, sizeof(struct grfinfo)); 473 break; 474 case GRFIOCMAP: 475 return(EINVAL); 476 break; 477 case GRFIOCUNMAP: 478 return(EINVAL); 479 break; 480 default: 481 return(EINVAL); 482 break; 483 } 484 return(0); 485 } 486 487 paddr_t 488 etmmap(dev, offset, prot) 489 dev_t dev; 490 off_t offset; 491 int prot; 492 { 493 struct et_softc *sc; 494 495 sc = et_cd.cd_devs[minor(dev)]; 496 497 /* 498 * control registers 499 * mapped from offset 0x0 to REG_MAPPABLE 500 */ 501 if (offset >= 0 && offset <= sc->sc_iosize) 502 return(m68k_btop(sc->sc_iobase + offset)); 503 504 /* 505 * VGA memory 506 * mapped from offset 0xa0000 to 0xc0000 507 */ 508 if (offset >= VGA_BASE && offset < (VGA_MAPPABLE + VGA_BASE)) 509 return(m68k_btop(sc->sc_maddr + offset - VGA_BASE)); 510 511 /* 512 * frame buffer 513 * mapped from offset 0x400000 to 0x4fffff 514 */ 515 if (offset >= FRAME_BASE && offset < sc->sc_msize + FRAME_BASE) 516 return(m68k_btop(sc->sc_maddr + offset - FRAME_BASE)); 517 518 return(-1); 519 } 520 521 int 522 eton(dev) 523 dev_t dev; 524 { 525 struct et_softc *sc; 526 527 if (minor(dev) >= et_cd.cd_ndevs) 528 return(ENXIO); 529 sc = et_cd.cd_devs[minor(dev)]; 530 if (!sc) 531 return(ENXIO); 532 return(0); 533 } 534 535 int 536 etoff(dev) 537 dev_t dev; 538 { 539 return(0); 540 } 541 542
Indexes created Mon Sep 29 21:09:56 GMT 2025