if_le_vme.c revision 1.7
1 /* $NetBSD: if_le_vme.c,v 1.7 1998/12/09 07:33:59 leo Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 Leo Weppelman. All rights reserved. 5 * Copyright (c) 1995 Charles M. Hannum. All rights reserved. 6 * Copyright (c) 1992, 1993 7 * The Regents of the University of California. All rights reserved. 8 * 9 * This code is derived from software contributed to Berkeley by 10 * Ralph Campbell and Rick Macklem. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the University of 23 * California, Berkeley and its contributors. 24 * 4. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * @(#)if_le.c 8.2 (Berkeley) 11/16/93 41 */ 42 43 #include "opt_inet.h" 44 #include "bpfilter.h" 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/mbuf.h> 49 #include <sys/syslog.h> 50 #include <sys/socket.h> 51 #include <sys/device.h> 52 53 #include <net/if.h> 54 #include <net/if_media.h> 55 #include <net/if_ether.h> 56 57 #ifdef INET 58 #include <netinet/in.h> 59 #include <netinet/if_inarp.h> 60 #endif 61 62 #include <machine/cpu.h> 63 #include <machine/bus.h> 64 #include <machine/iomap.h> 65 #include <machine/scu.h> 66 67 #include <atari/atari/device.h> 68 #include <atari/atari/intr.h> 69 70 #include <dev/ic/lancereg.h> 71 #include <dev/ic/lancevar.h> 72 #include <dev/ic/am7990reg.h> 73 #include <dev/ic/am7990var.h> 74 75 #include <atari/vme/vmevar.h> 76 #include <atari/vme/if_levar.h> 77 78 /* 79 * All cards except BVME410 have 64KB RAM. However.... On the Riebl cards the 80 * area between the offsets 0xee70-0xeec0 is used to store config data. 81 */ 82 struct le_addresses { 83 u_long reg_addr; 84 u_long mem_addr; 85 int irq; 86 int reg_size; 87 int mem_size; 88 } lestd[] = { 89 { 0xfe00fff0, 0xfe010000, IRQUNK, 16, 64*1024 }, /* Riebl */ 90 { 0xffcffff0, 0xffcf0000, 5, 16, 64*1024 }, /* PAM */ 91 { 0xfecffff0, 0xfecf0000, 5, 16, 64*1024 }, /* Rhotron */ 92 { 0xfeff4100, 0xfe000000, 4, 8, VMECF_MEMSIZ_DEFAULT } /*BVME410*/ 93 }; 94 95 #define NLESTD (sizeof(lestd) / sizeof(lestd[0])) 96 97 /* 98 * Default mac for RIEBL cards without a (working) battery. The first 4 bytes 99 * are the manufacturer id. 100 */ 101 static u_char riebl_def_mac[] = { 102 0x00, 0x00, 0x36, 0x04, 0x00, 0x00 103 }; 104 105 static int le_intr __P((struct le_softc *, int)); 106 static void lepseudointr __P((struct le_softc *, void *)); 107 static int le_vme_match __P((struct device *, struct cfdata *, void *)); 108 static void le_vme_attach __P((struct device *, struct device *, void *)); 109 static int probe_addresses __P((bus_space_tag_t *, bus_space_tag_t *, 110 bus_space_handle_t *, bus_space_handle_t *)); 111 static void riebl_skip_reserved_area __P((struct lance_softc *)); 112 static int nm93c06_read __P((bus_space_tag_t, bus_space_handle_t, int)); 113 static int bvme410_mem_size __P((bus_space_tag_t, u_long)); 114 static void bvme410_copytobuf __P((struct lance_softc *, void *, int, int)); 115 static void bvme410_zerobuf __P((struct lance_softc *, int, int)); 116 117 struct cfattach le_vme_ca = { 118 sizeof(struct le_softc), le_vme_match, le_vme_attach 119 }; 120 121 #if defined(_KERNEL) && !defined(_LKM) 122 #include "opt_ddb.h" 123 #endif 124 125 #ifdef DDB 126 #define integrate 127 #define hide 128 #else 129 #define integrate static __inline 130 #define hide static 131 #endif 132 133 hide void lewrcsr __P((struct lance_softc *, u_int16_t, u_int16_t)); 134 hide u_int16_t lerdcsr __P((struct lance_softc *, u_int16_t)); 135 136 hide void 137 lewrcsr(sc, port, val) 138 struct lance_softc *sc; 139 u_int16_t port, val; 140 { 141 struct le_softc *lesc = (struct le_softc *)sc; 142 int s; 143 144 s = splhigh(); 145 bus_space_write_2(lesc->sc_iot, lesc->sc_ioh, LER_RAP, port); 146 bus_space_write_2(lesc->sc_iot, lesc->sc_ioh, LER_RDP, val); 147 splx(s); 148 } 149 150 hide u_int16_t 151 lerdcsr(sc, port) 152 struct lance_softc *sc; 153 u_int16_t port; 154 { 155 struct le_softc *lesc = (struct le_softc *)sc; 156 u_int16_t val; 157 int s; 158 159 s = splhigh(); 160 bus_space_write_2(lesc->sc_iot, lesc->sc_ioh, LER_RAP, port); 161 val = bus_space_read_2(lesc->sc_iot, lesc->sc_ioh, LER_RDP); 162 splx(s); 163 164 return (val); 165 } 166 167 static int 168 le_vme_match(parent, cfp, aux) 169 struct device *parent; 170 struct cfdata *cfp; 171 void *aux; 172 { 173 struct vme_attach_args *va = aux; 174 int i; 175 bus_space_tag_t iot; 176 bus_space_tag_t memt; 177 bus_space_handle_t ioh; 178 bus_space_handle_t memh; 179 180 iot = va->va_iot; 181 memt = va->va_memt; 182 183 for (i = 0; i < NLESTD; i++) { 184 struct le_addresses *le_ap = &lestd[i]; 185 int found = 0; 186 187 if ((va->va_iobase != IOBASEUNK) 188 && (va->va_iobase != le_ap->reg_addr)) 189 continue; 190 191 if ((va->va_maddr != MADDRUNK) 192 && (va->va_maddr != le_ap->mem_addr)) 193 continue; 194 195 if ((le_ap->irq != IRQUNK) && (va->va_irq != le_ap->irq)) 196 continue; 197 198 if (bus_space_map(iot, le_ap->reg_addr, le_ap->reg_size, 0, &ioh)) { 199 printf("leprobe: cannot map io-area\n"); 200 return (0); 201 } 202 if (le_ap->mem_size == VMECF_MEMSIZ_DEFAULT) { 203 if (bus_space_peek_2(iot, ioh, BVME410_IVEC)) { 204 bus_space_write_2(iot, ioh, BVME410_BAR, 0x1); /* XXX */ 205 le_ap->mem_size = bvme410_mem_size(memt, le_ap->mem_addr); 206 } 207 } 208 if (le_ap->mem_size == VMECF_MEMSIZ_DEFAULT) { 209 bus_space_unmap(iot, (caddr_t)le_ap->reg_addr, le_ap->reg_size); 210 continue; 211 } 212 213 if (bus_space_map(memt, le_ap->mem_addr, le_ap->mem_size, 0, &memh)) { 214 bus_space_unmap(iot, (caddr_t)le_ap->reg_addr, le_ap->reg_size); 215 printf("leprobe: cannot map memory-area\n"); 216 return (0); 217 } 218 found = probe_addresses(&iot, &memt, &ioh, &memh); 219 bus_space_unmap(iot, (caddr_t)le_ap->reg_addr, le_ap->reg_size); 220 bus_space_unmap(memt, (caddr_t)le_ap->mem_addr, le_ap->mem_size); 221 222 if (found) { 223 va->va_iobase = le_ap->reg_addr; 224 va->va_iosize = le_ap->reg_size; 225 va->va_maddr = le_ap->mem_addr; 226 va->va_msize = le_ap->mem_size; 227 if (va->va_irq == IRQUNK) 228 va->va_irq = le_ap->irq; 229 return 1; 230 } 231 } 232 return (0); 233 } 234 235 static int 236 probe_addresses(iot, memt, ioh, memh) 237 bus_space_tag_t *iot; 238 bus_space_tag_t *memt; 239 bus_space_handle_t *ioh; 240 bus_space_handle_t *memh; 241 { 242 /* 243 * Test accesibility of register and memory area 244 */ 245 if(!bus_space_peek_2(*iot, *ioh, LER_RDP)) 246 return 0; 247 if(!bus_space_peek_1(*memt, *memh, 0)) 248 return 0; 249 250 /* 251 * Test for writable memory 252 */ 253 bus_space_write_2(*memt, *memh, 0, 0xa5a5); 254 if (bus_space_read_2(*memt, *memh, 0) != 0xa5a5) 255 return 0; 256 257 /* 258 * Test writability of selector port. 259 */ 260 bus_space_write_2(*iot, *ioh, LER_RAP, LE_CSR1); 261 if (bus_space_read_2(*iot, *ioh, LER_RAP) != LE_CSR1) 262 return 0; 263 264 /* 265 * Do a small register test 266 */ 267 bus_space_write_2(*iot, *ioh, LER_RAP, LE_CSR0); 268 bus_space_write_2(*iot, *ioh, LER_RDP, LE_C0_INIT | LE_C0_STOP); 269 if (bus_space_read_2(*iot, *ioh, LER_RDP) != LE_C0_STOP) 270 return 0; 271 272 bus_space_write_2(*iot, *ioh, LER_RDP, LE_C0_STOP); 273 if (bus_space_read_2(*iot, *ioh, LER_RDP) != LE_C0_STOP) 274 return 0; 275 276 return 1; 277 } 278 279 /* 280 * Interrupt mess. Because the card's interrupt is hardwired to either 281 * ipl5 or ipl3 (mostly on ipl5) and raising splnet to spl5() just won't do 282 * (it kills the serial at the least), we use a 2-level interrupt sceme. The 283 * card interrupt is routed to 'le_intr'. If the previous ipl was below 284 * splnet, just call the mi-function. If not, save the interrupt status, 285 * turn off card interrupts (the card is *very* persistent) and arrange 286 * for a softint 'callback' through 'lepseudointr'. 287 */ 288 static int 289 le_intr(lesc, sr) 290 struct le_softc *lesc; 291 int sr; 292 { 293 struct lance_softc *sc = &lesc->sc_am7990.lsc; 294 u_int16_t csr0; 295 296 if ((sr & PSL_IPL) < IPL_NET) 297 am7990_intr(sc); 298 else { 299 sc->sc_saved_csr0 = csr0 = lerdcsr(sc, LE_CSR0); 300 lewrcsr(sc, LE_CSR0, csr0 & ~LE_C0_INEA); 301 add_sicallback((si_farg)lepseudointr, lesc, sc); 302 } 303 return 1; 304 } 305 306 307 static void 308 lepseudointr(lesc, sc) 309 struct le_softc *lesc; 310 void *sc; 311 { 312 int s; 313 314 s = splx(lesc->sc_splval); 315 am7990_intr(sc); 316 splx(s); 317 } 318 319 static void 320 le_vme_attach(parent, self, aux) 321 struct device *parent, *self; 322 void *aux; 323 { 324 struct le_softc *lesc = (struct le_softc *)self; 325 struct lance_softc *sc = &lesc->sc_am7990.lsc; 326 struct vme_attach_args *va = aux; 327 bus_space_handle_t ioh; 328 bus_space_handle_t memh; 329 int i; 330 331 printf("\n%s: ", sc->sc_dev.dv_xname); 332 333 if (bus_space_map(va->va_iot, va->va_iobase, va->va_iosize, 0, &ioh)) 334 panic("leattach: cannot map io-area\n"); 335 if (bus_space_map(va->va_memt, va->va_maddr, va->va_msize, 0, &memh)) 336 panic("leattach: cannot map mem-area\n"); 337 338 lesc->sc_iot = va->va_iot; 339 lesc->sc_ioh = ioh; 340 lesc->sc_memt = va->va_memt; 341 lesc->sc_memh = memh; 342 lesc->sc_splval = (va->va_irq << 8) | PSL_S; /* XXX */ 343 344 /* 345 * Go on to find board type 346 */ 347 if (bus_space_peek_1(va->va_iot, ioh, LER_EEPROM)) { 348 printf("PAM card"); 349 lesc->sc_type = LE_PAM; 350 bus_space_read_1(va->va_iot, ioh, LER_MEME); 351 } 352 else if (bus_space_peek_2(va->va_iot, ioh, BVME410_IVEC)) { 353 printf("BVME410"); 354 lesc->sc_type = LE_BVME410; 355 } 356 else { 357 printf("Riebl card"); 358 if(bus_space_read_4(va->va_memt, memh, RIEBL_MAGIC_ADDR) 359 == RIEBL_MAGIC) 360 lesc->sc_type = LE_NEW_RIEBL; 361 else { 362 printf("(without battery) "); 363 lesc->sc_type = LE_OLD_RIEBL; 364 } 365 } 366 367 switch (lesc->sc_type) { 368 case LE_BVME410: 369 sc->sc_copytodesc = bvme410_copytobuf; 370 sc->sc_copyfromdesc = lance_copyfrombuf_contig; 371 sc->sc_copytobuf = bvme410_copytobuf; 372 sc->sc_copyfrombuf = lance_copyfrombuf_contig; 373 sc->sc_zerobuf = bvme410_zerobuf; 374 break; 375 default: 376 sc->sc_copytodesc = lance_copytobuf_contig; 377 sc->sc_copyfromdesc = lance_copyfrombuf_contig; 378 sc->sc_copytobuf = lance_copytobuf_contig; 379 sc->sc_copyfrombuf = lance_copyfrombuf_contig; 380 sc->sc_zerobuf = lance_zerobuf_contig; 381 break; 382 } 383 384 sc->sc_rdcsr = lerdcsr; 385 sc->sc_wrcsr = lewrcsr; 386 sc->sc_hwinit = NULL; 387 sc->sc_conf3 = LE_C3_BSWP; 388 sc->sc_addr = 0; 389 sc->sc_memsize = va->va_msize; 390 sc->sc_mem = (void *)memh; /* XXX */ 391 392 /* 393 * Get MAC address 394 */ 395 switch (lesc->sc_type) { 396 case LE_OLD_RIEBL: 397 bcopy(riebl_def_mac, sc->sc_enaddr, 398 sizeof(sc->sc_enaddr)); 399 break; 400 case LE_NEW_RIEBL: 401 for (i = 0; i < sizeof(sc->sc_enaddr); i++) 402 sc->sc_enaddr[i] = 403 bus_space_read_1(va->va_memt, memh, i + RIEBL_MAC_ADDR); 404 break; 405 case LE_PAM: 406 i = bus_space_read_1(va->va_iot, ioh, LER_EEPROM); 407 for (i = 0; i < sizeof(sc->sc_enaddr); i++) { 408 sc->sc_enaddr[i] = 409 (bus_space_read_2(va->va_memt, memh, 2 * i) << 4) | 410 (bus_space_read_2(va->va_memt, memh, 2 * i + 1) & 0xf); 411 } 412 i = bus_space_read_1(va->va_iot, ioh, LER_MEME); 413 break; 414 case LE_BVME410: 415 for (i = 0; i < (sizeof(sc->sc_enaddr) >> 1); i++) { 416 u_int16_t tmp; 417 418 tmp = nm93c06_read(va->va_iot, ioh, i); 419 sc->sc_enaddr[2 * i] = (tmp >> 8) & 0xff; 420 sc->sc_enaddr[2 * i + 1] = tmp & 0xff; 421 } 422 bus_space_write_2(va->va_iot, ioh, BVME410_BAR, 0x1); /* XXX */ 423 } 424 425 am7990_config(&lesc->sc_am7990); 426 427 if ((lesc->sc_type == LE_OLD_RIEBL) || (lesc->sc_type == LE_NEW_RIEBL)) 428 riebl_skip_reserved_area(sc); 429 430 /* 431 * XXX: We always use uservector 64.... 432 */ 433 if ((lesc->sc_intr = intr_establish(64, USER_VEC, 0, 434 (hw_ifun_t)le_intr, lesc)) == NULL) { 435 printf("le_vme_attach: Can't establish interrupt\n"); 436 return; 437 } 438 439 /* 440 * Notify the card of the vector 441 */ 442 switch (lesc->sc_type) { 443 case LE_OLD_RIEBL: 444 case LE_NEW_RIEBL: 445 bus_space_write_2(va->va_memt, memh, RIEBL_IVEC_ADDR, 446 64 + 64); 447 break; 448 case LE_PAM: 449 bus_space_write_1(va->va_iot, ioh, LER_IVEC, 64 + 64); 450 break; 451 case LE_BVME410: 452 bus_space_write_2(va->va_iot, ioh, BVME410_IVEC, 64 + 64); 453 break; 454 } 455 456 /* 457 * Unmask the VME-interrupt we're on 458 */ 459 if (machineid & ATARI_TT) 460 SCU->vme_mask |= 1 << va->va_irq; 461 } 462 463 /* 464 * True if 'addr' containe within [start,len] 465 */ 466 #define WITHIN(start, len, addr) \ 467 ((addr >= start) && ((addr) <= ((start) + (len)))) 468 static void 469 riebl_skip_reserved_area(sc) 470 struct lance_softc *sc; 471 { 472 int offset = 0; 473 int i; 474 475 for(i = 0; i < sc->sc_nrbuf; i++) { 476 if (WITHIN(sc->sc_rbufaddr[i], LEBLEN, RIEBL_RES_START) 477 || WITHIN(sc->sc_rbufaddr[i], LEBLEN, RIEBL_RES_END)) { 478 offset = RIEBL_RES_END - sc->sc_rbufaddr[i]; 479 } 480 sc->sc_rbufaddr[i] += offset; 481 } 482 483 for(i = 0; i < sc->sc_ntbuf; i++) { 484 if (WITHIN(sc->sc_tbufaddr[i], LEBLEN, RIEBL_RES_START) 485 || WITHIN(sc->sc_tbufaddr[i], LEBLEN, RIEBL_RES_END)) { 486 offset = RIEBL_RES_END - sc->sc_tbufaddr[i]; 487 } 488 sc->sc_tbufaddr[i] += offset; 489 } 490 } 491 492 static int 493 nm93c06_read(iot, ioh, nm93c06reg) 494 bus_space_tag_t iot; 495 bus_space_handle_t ioh; 496 int nm93c06reg; 497 { 498 int bar; 499 int shift; 500 int bits = 0x180 | (nm93c06reg & 0xf); 501 int data = 0; 502 503 bar = 1<<BVME410_CS_SHIFT; 504 bus_space_write_2(iot, ioh, BVME410_BAR, bar); 505 delay(1); /* tCSS = 1 us */ 506 for (shift = 9; shift >= 0; shift--) { 507 if (((bits >> shift) & 1) == 1) 508 bar |= 1<<BVME410_DIN_SHIFT; 509 else 510 bar &= ~(1<<BVME410_DIN_SHIFT); 511 bus_space_write_2(iot, ioh, BVME410_BAR, bar); 512 delay(1); /* tDIS = 0.4 us */ 513 bar |= 1<<BVME410_CLK_SHIFT; 514 bus_space_write_2(iot, ioh, BVME410_BAR, bar); 515 delay(2); /* tSKH = 1 us, tSKH + tSKL >= 4 us */ 516 bar &= ~(1<<BVME410_CLK_SHIFT); 517 bus_space_write_2(iot, ioh, BVME410_BAR, bar); 518 delay(2); /* tSKL = 1 us, tSKH + tSKL >= 4 us */ 519 } 520 bar &= ~(1<<BVME410_DIN_SHIFT); 521 for (shift = 15; shift >= 0; shift--) { 522 delay(1); /* tDIS = 100 ns, BVM manual says 0.4 us */ 523 bar |= 1<<BVME410_CLK_SHIFT; 524 bus_space_write_2(iot, ioh, BVME410_BAR, bar); 525 delay(2); /* tSKH = 1 us, tSKH + tSKL >= 4 us */ 526 data |= (bus_space_read_2(iot, ioh, BVME410_BAR) & 1) << shift; 527 bar &= ~(1<<BVME410_CLK_SHIFT); 528 bus_space_write_2(iot, ioh, BVME410_BAR, bar); 529 delay(2); /* tSKL = 1 us, tSKH + tSKL >= 4 us */ 530 } 531 bar &= ~(1<<BVME410_CS_SHIFT); 532 bus_space_write_2(iot, ioh, BVME410_BAR, bar); 533 delay(1); /* tCS = 1 us */ 534 return data; 535 } 536 537 static int 538 bvme410_mem_size(memt, mem_addr) 539 bus_space_tag_t memt; 540 u_long mem_addr; 541 { 542 bus_space_handle_t memh; 543 int r; 544 545 if (bus_space_map(memt, mem_addr, 256*1024, 0, &memh)) 546 return VMECF_MEMSIZ_DEFAULT; 547 if (!bus_space_peek_1(memt, memh, 0)) { 548 bus_space_unmap(memt, (caddr_t)mem_addr, 256*1024); 549 return VMECF_MEMSIZ_DEFAULT; 550 } 551 bus_space_write_1(memt, memh, 0, 128); 552 bus_space_write_1(memt, memh, 64*1024, 32); 553 bus_space_write_1(memt, memh, 32*1024, 8); 554 r = (int)(bus_space_read_1(memt, memh, 0) * 2048); 555 bus_space_unmap(memt, (caddr_t)mem_addr, 256*1024); 556 return r; 557 } 558 559 /* 560 * Need to be careful when writing to the bvme410 dual port memory. 561 * Continue writing each byte until it reads back the same. 562 */ 563 564 static void 565 bvme410_copytobuf(sc, from, boff, len) 566 struct lance_softc *sc; 567 void *from; 568 int boff, len; 569 { 570 volatile char *buf = (volatile char *) sc->sc_mem; 571 char *f = (char *) from; 572 573 for (buf += boff; len; buf++,f++,len--) 574 while (*buf != *f) 575 *buf = *f; 576 } 577 578 static void 579 bvme410_zerobuf(sc, boff, len) 580 struct lance_softc *sc; 581 int boff, len; 582 { 583 volatile char *buf = (volatile char *)sc->sc_mem; 584 585 for (buf += boff; len; buf++,len--) 586 while (*buf != '\0') 587 *buf = '\0'; 588 } 589 590
Indexes created Wed Oct 01 07:09:59 GMT 2025