if_le_vme.c revision 1.8
1 /* $NetBSD: if_le_vme.c,v 1.8 1998/12/09 08:51:12 leo Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 Leo Weppelman. All rights reserved. 5 * Copyright (c) 1995 Charles M. Hannum. All rights reserved. 6 * Copyright (c) 1992, 1993 7 * The Regents of the University of California. All rights reserved. 8 * 9 * This code is derived from software contributed to Berkeley by 10 * Ralph Campbell and Rick Macklem. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the University of 23 * California, Berkeley and its contributors. 24 * 4. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * @(#)if_le.c 8.2 (Berkeley) 11/16/93 41 */ 42 43 #include "opt_inet.h" 44 #include "bpfilter.h" 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/mbuf.h> 49 #include <sys/syslog.h> 50 #include <sys/socket.h> 51 #include <sys/device.h> 52 53 #include <net/if.h> 54 #include <net/if_media.h> 55 #include <net/if_ether.h> 56 57 #ifdef INET 58 #include <netinet/in.h> 59 #include <netinet/if_inarp.h> 60 #endif 61 62 #include <machine/cpu.h> 63 #include <machine/bus.h> 64 #include <machine/iomap.h> 65 #include <machine/scu.h> 66 67 #include <atari/atari/device.h> 68 #include <atari/atari/intr.h> 69 70 #include <dev/ic/lancereg.h> 71 #include <dev/ic/lancevar.h> 72 #include <dev/ic/am7990reg.h> 73 #include <dev/ic/am7990var.h> 74 75 #include <atari/vme/vmevar.h> 76 #include <atari/vme/if_levar.h> 77 78 /* 79 * All cards except BVME410 have 64KB RAM. However.... On the Riebl cards the 80 * area between the offsets 0xee70-0xeec0 is used to store config data. 81 */ 82 struct le_addresses { 83 u_long reg_addr; 84 u_long mem_addr; 85 int irq; 86 int reg_size; 87 int mem_size; 88 int type_hint; 89 } lestd[] = { 90 { 0xfe00fff0, 0xfe010000, IRQUNK, 16, 64*1024, 91 LE_OLD_RIEBL|LE_NEW_RIEBL }, /* Riebl */ 92 { 0xffcffff0, 0xffcf0000, 5, 16, 64*1024, 93 LE_PAM }, /* PAM */ 94 { 0xfecffff0, 0xfecf0000, 5, 16, 64*1024, 95 LE_ROTHRON }, /* Rhotron */ 96 { 0xfeff4100, 0xfe000000, 4, 8, VMECF_MEMSIZ_DEFAULT, 97 LE_BVME410 } /* BVME410 */ 98 }; 99 100 #define NLESTD (sizeof(lestd) / sizeof(lestd[0])) 101 102 /* 103 * Default mac for RIEBL cards without a (working) battery. The first 4 bytes 104 * are the manufacturer id. 105 */ 106 static u_char riebl_def_mac[] = { 107 0x00, 0x00, 0x36, 0x04, 0x00, 0x00 108 }; 109 110 static int le_intr __P((struct le_softc *, int)); 111 static void lepseudointr __P((struct le_softc *, void *)); 112 static int le_vme_match __P((struct device *, struct cfdata *, void *)); 113 static void le_vme_attach __P((struct device *, struct device *, void *)); 114 static int probe_addresses __P((bus_space_tag_t *, bus_space_tag_t *, 115 bus_space_handle_t *, bus_space_handle_t *)); 116 static void riebl_skip_reserved_area __P((struct lance_softc *)); 117 static int nm93c06_read __P((bus_space_tag_t, bus_space_handle_t, int)); 118 static int bvme410_mem_size __P((bus_space_tag_t, u_long)); 119 static void bvme410_copytobuf __P((struct lance_softc *, void *, int, int)); 120 static void bvme410_zerobuf __P((struct lance_softc *, int, int)); 121 122 struct cfattach le_vme_ca = { 123 sizeof(struct le_softc), le_vme_match, le_vme_attach 124 }; 125 126 #if defined(_KERNEL) && !defined(_LKM) 127 #include "opt_ddb.h" 128 #endif 129 130 #ifdef DDB 131 #define integrate 132 #define hide 133 #else 134 #define integrate static __inline 135 #define hide static 136 #endif 137 138 hide void lewrcsr __P((struct lance_softc *, u_int16_t, u_int16_t)); 139 hide u_int16_t lerdcsr __P((struct lance_softc *, u_int16_t)); 140 141 hide void 142 lewrcsr(sc, port, val) 143 struct lance_softc *sc; 144 u_int16_t port, val; 145 { 146 struct le_softc *lesc = (struct le_softc *)sc; 147 int s; 148 149 s = splhigh(); 150 bus_space_write_2(lesc->sc_iot, lesc->sc_ioh, LER_RAP, port); 151 bus_space_write_2(lesc->sc_iot, lesc->sc_ioh, LER_RDP, val); 152 splx(s); 153 } 154 155 hide u_int16_t 156 lerdcsr(sc, port) 157 struct lance_softc *sc; 158 u_int16_t port; 159 { 160 struct le_softc *lesc = (struct le_softc *)sc; 161 u_int16_t val; 162 int s; 163 164 s = splhigh(); 165 bus_space_write_2(lesc->sc_iot, lesc->sc_ioh, LER_RAP, port); 166 val = bus_space_read_2(lesc->sc_iot, lesc->sc_ioh, LER_RDP); 167 splx(s); 168 169 return (val); 170 } 171 172 static int 173 le_vme_match(parent, cfp, aux) 174 struct device *parent; 175 struct cfdata *cfp; 176 void *aux; 177 { 178 struct vme_attach_args *va = aux; 179 int i; 180 bus_space_tag_t iot; 181 bus_space_tag_t memt; 182 bus_space_handle_t ioh; 183 bus_space_handle_t memh; 184 185 iot = va->va_iot; 186 memt = va->va_memt; 187 188 for (i = 0; i < NLESTD; i++) { 189 struct le_addresses *le_ap = &lestd[i]; 190 int found = 0; 191 192 if ((va->va_iobase != IOBASEUNK) 193 && (va->va_iobase != le_ap->reg_addr)) 194 continue; 195 196 if ((va->va_maddr != MADDRUNK) 197 && (va->va_maddr != le_ap->mem_addr)) 198 continue; 199 200 if ((le_ap->irq != IRQUNK) && (va->va_irq != le_ap->irq)) 201 continue; 202 203 if (bus_space_map(iot, le_ap->reg_addr, le_ap->reg_size, 0, &ioh)) { 204 printf("leprobe: cannot map io-area\n"); 205 return (0); 206 } 207 if (le_ap->mem_size == VMECF_MEMSIZ_DEFAULT) { 208 if (bus_space_peek_2(iot, ioh, BVME410_IVEC)) { 209 bus_space_write_2(iot, ioh, BVME410_BAR, 0x1); /* XXX */ 210 le_ap->mem_size = bvme410_mem_size(memt, le_ap->mem_addr); 211 } 212 } 213 if (le_ap->mem_size == VMECF_MEMSIZ_DEFAULT) { 214 bus_space_unmap(iot, (caddr_t)le_ap->reg_addr, le_ap->reg_size); 215 continue; 216 } 217 218 if (bus_space_map(memt, le_ap->mem_addr, le_ap->mem_size, 0, &memh)) { 219 bus_space_unmap(iot, (caddr_t)le_ap->reg_addr, le_ap->reg_size); 220 printf("leprobe: cannot map memory-area\n"); 221 return (0); 222 } 223 found = probe_addresses(&iot, &memt, &ioh, &memh); 224 bus_space_unmap(iot, (caddr_t)le_ap->reg_addr, le_ap->reg_size); 225 bus_space_unmap(memt, (caddr_t)le_ap->mem_addr, le_ap->mem_size); 226 227 if (found) { 228 va->va_iobase = le_ap->reg_addr; 229 va->va_iosize = le_ap->reg_size; 230 va->va_maddr = le_ap->mem_addr; 231 va->va_msize = le_ap->mem_size; 232 va->va_aux = le_ap; 233 if (va->va_irq == IRQUNK) 234 va->va_irq = le_ap->irq; 235 return 1; 236 } 237 } 238 return (0); 239 } 240 241 static int 242 probe_addresses(iot, memt, ioh, memh) 243 bus_space_tag_t *iot; 244 bus_space_tag_t *memt; 245 bus_space_handle_t *ioh; 246 bus_space_handle_t *memh; 247 { 248 /* 249 * Test accesibility of register and memory area 250 */ 251 if(!bus_space_peek_2(*iot, *ioh, LER_RDP)) 252 return 0; 253 if(!bus_space_peek_1(*memt, *memh, 0)) 254 return 0; 255 256 /* 257 * Test for writable memory 258 */ 259 bus_space_write_2(*memt, *memh, 0, 0xa5a5); 260 if (bus_space_read_2(*memt, *memh, 0) != 0xa5a5) 261 return 0; 262 263 /* 264 * Test writability of selector port. 265 */ 266 bus_space_write_2(*iot, *ioh, LER_RAP, LE_CSR1); 267 if (bus_space_read_2(*iot, *ioh, LER_RAP) != LE_CSR1) 268 return 0; 269 270 /* 271 * Do a small register test 272 */ 273 bus_space_write_2(*iot, *ioh, LER_RAP, LE_CSR0); 274 bus_space_write_2(*iot, *ioh, LER_RDP, LE_C0_INIT | LE_C0_STOP); 275 if (bus_space_read_2(*iot, *ioh, LER_RDP) != LE_C0_STOP) 276 return 0; 277 278 bus_space_write_2(*iot, *ioh, LER_RDP, LE_C0_STOP); 279 if (bus_space_read_2(*iot, *ioh, LER_RDP) != LE_C0_STOP) 280 return 0; 281 282 return 1; 283 } 284 285 /* 286 * Interrupt mess. Because the card's interrupt is hardwired to either 287 * ipl5 or ipl3 (mostly on ipl5) and raising splnet to spl5() just won't do 288 * (it kills the serial at the least), we use a 2-level interrupt sceme. The 289 * card interrupt is routed to 'le_intr'. If the previous ipl was below 290 * splnet, just call the mi-function. If not, save the interrupt status, 291 * turn off card interrupts (the card is *very* persistent) and arrange 292 * for a softint 'callback' through 'lepseudointr'. 293 */ 294 static int 295 le_intr(lesc, sr) 296 struct le_softc *lesc; 297 int sr; 298 { 299 struct lance_softc *sc = &lesc->sc_am7990.lsc; 300 u_int16_t csr0; 301 302 if ((sr & PSL_IPL) < IPL_NET) 303 am7990_intr(sc); 304 else { 305 sc->sc_saved_csr0 = csr0 = lerdcsr(sc, LE_CSR0); 306 lewrcsr(sc, LE_CSR0, csr0 & ~LE_C0_INEA); 307 add_sicallback((si_farg)lepseudointr, lesc, sc); 308 } 309 return 1; 310 } 311 312 313 static void 314 lepseudointr(lesc, sc) 315 struct le_softc *lesc; 316 void *sc; 317 { 318 int s; 319 320 s = splx(lesc->sc_splval); 321 am7990_intr(sc); 322 splx(s); 323 } 324 325 static void 326 le_vme_attach(parent, self, aux) 327 struct device *parent, *self; 328 void *aux; 329 { 330 struct le_softc *lesc = (struct le_softc *)self; 331 struct lance_softc *sc = &lesc->sc_am7990.lsc; 332 struct vme_attach_args *va = aux; 333 bus_space_handle_t ioh; 334 bus_space_handle_t memh; 335 struct le_addresses *le_ap; 336 int i; 337 338 printf("\n%s: ", sc->sc_dev.dv_xname); 339 340 if (bus_space_map(va->va_iot, va->va_iobase, va->va_iosize, 0, &ioh)) 341 panic("leattach: cannot map io-area\n"); 342 if (bus_space_map(va->va_memt, va->va_maddr, va->va_msize, 0, &memh)) 343 panic("leattach: cannot map mem-area\n"); 344 345 lesc->sc_iot = va->va_iot; 346 lesc->sc_ioh = ioh; 347 lesc->sc_memt = va->va_memt; 348 lesc->sc_memh = memh; 349 lesc->sc_splval = (va->va_irq << 8) | PSL_S; /* XXX */ 350 le_ap = (struct le_addresses *)va->va_aux; 351 352 /* 353 * Go on to find board type 354 */ 355 if ((le_ap->type_hint & LE_PAM) 356 && bus_space_peek_1(va->va_iot, ioh, LER_EEPROM)) { 357 printf("PAM card"); 358 lesc->sc_type = LE_PAM; 359 bus_space_read_1(va->va_iot, ioh, LER_MEME); 360 } 361 else if((le_ap->type_hint & LE_BVME410) 362 && bus_space_peek_2(va->va_iot, ioh, BVME410_IVEC)) { 363 printf("BVME410"); 364 lesc->sc_type = LE_BVME410; 365 } 366 else if (le_ap->type_hint & (LE_NEW_RIEBL|LE_OLD_RIEBL)) { 367 printf("Riebl card"); 368 if(bus_space_read_4(va->va_memt, memh, RIEBL_MAGIC_ADDR) 369 == RIEBL_MAGIC) 370 lesc->sc_type = LE_NEW_RIEBL; 371 else { 372 printf("(without battery) "); 373 lesc->sc_type = LE_OLD_RIEBL; 374 } 375 } 376 else printf("le_vme_attach: Unsupported card!"); 377 378 switch (lesc->sc_type) { 379 case LE_BVME410: 380 sc->sc_copytodesc = bvme410_copytobuf; 381 sc->sc_copyfromdesc = lance_copyfrombuf_contig; 382 sc->sc_copytobuf = bvme410_copytobuf; 383 sc->sc_copyfrombuf = lance_copyfrombuf_contig; 384 sc->sc_zerobuf = bvme410_zerobuf; 385 break; 386 default: 387 sc->sc_copytodesc = lance_copytobuf_contig; 388 sc->sc_copyfromdesc = lance_copyfrombuf_contig; 389 sc->sc_copytobuf = lance_copytobuf_contig; 390 sc->sc_copyfrombuf = lance_copyfrombuf_contig; 391 sc->sc_zerobuf = lance_zerobuf_contig; 392 break; 393 } 394 395 sc->sc_rdcsr = lerdcsr; 396 sc->sc_wrcsr = lewrcsr; 397 sc->sc_hwinit = NULL; 398 sc->sc_conf3 = LE_C3_BSWP; 399 sc->sc_addr = 0; 400 sc->sc_memsize = va->va_msize; 401 sc->sc_mem = (void *)memh; /* XXX */ 402 403 /* 404 * Get MAC address 405 */ 406 switch (lesc->sc_type) { 407 case LE_OLD_RIEBL: 408 bcopy(riebl_def_mac, sc->sc_enaddr, 409 sizeof(sc->sc_enaddr)); 410 break; 411 case LE_NEW_RIEBL: 412 for (i = 0; i < sizeof(sc->sc_enaddr); i++) 413 sc->sc_enaddr[i] = 414 bus_space_read_1(va->va_memt, memh, i + RIEBL_MAC_ADDR); 415 break; 416 case LE_PAM: 417 i = bus_space_read_1(va->va_iot, ioh, LER_EEPROM); 418 for (i = 0; i < sizeof(sc->sc_enaddr); i++) { 419 sc->sc_enaddr[i] = 420 (bus_space_read_2(va->va_memt, memh, 2 * i) << 4) | 421 (bus_space_read_2(va->va_memt, memh, 2 * i + 1) & 0xf); 422 } 423 i = bus_space_read_1(va->va_iot, ioh, LER_MEME); 424 break; 425 case LE_BVME410: 426 for (i = 0; i < (sizeof(sc->sc_enaddr) >> 1); i++) { 427 u_int16_t tmp; 428 429 tmp = nm93c06_read(va->va_iot, ioh, i); 430 sc->sc_enaddr[2 * i] = (tmp >> 8) & 0xff; 431 sc->sc_enaddr[2 * i + 1] = tmp & 0xff; 432 } 433 bus_space_write_2(va->va_iot, ioh, BVME410_BAR, 0x1); /* XXX */ 434 } 435 436 am7990_config(&lesc->sc_am7990); 437 438 if ((lesc->sc_type == LE_OLD_RIEBL) || (lesc->sc_type == LE_NEW_RIEBL)) 439 riebl_skip_reserved_area(sc); 440 441 /* 442 * XXX: We always use uservector 64.... 443 */ 444 if ((lesc->sc_intr = intr_establish(64, USER_VEC, 0, 445 (hw_ifun_t)le_intr, lesc)) == NULL) { 446 printf("le_vme_attach: Can't establish interrupt\n"); 447 return; 448 } 449 450 /* 451 * Notify the card of the vector 452 */ 453 switch (lesc->sc_type) { 454 case LE_OLD_RIEBL: 455 case LE_NEW_RIEBL: 456 bus_space_write_2(va->va_memt, memh, RIEBL_IVEC_ADDR, 457 64 + 64); 458 break; 459 case LE_PAM: 460 bus_space_write_1(va->va_iot, ioh, LER_IVEC, 64 + 64); 461 break; 462 case LE_BVME410: 463 bus_space_write_2(va->va_iot, ioh, BVME410_IVEC, 64 + 64); 464 break; 465 } 466 467 /* 468 * Unmask the VME-interrupt we're on 469 */ 470 if (machineid & ATARI_TT) 471 SCU->vme_mask |= 1 << va->va_irq; 472 } 473 474 /* 475 * True if 'addr' containe within [start,len] 476 */ 477 #define WITHIN(start, len, addr) \ 478 ((addr >= start) && ((addr) <= ((start) + (len)))) 479 static void 480 riebl_skip_reserved_area(sc) 481 struct lance_softc *sc; 482 { 483 int offset = 0; 484 int i; 485 486 for(i = 0; i < sc->sc_nrbuf; i++) { 487 if (WITHIN(sc->sc_rbufaddr[i], LEBLEN, RIEBL_RES_START) 488 || WITHIN(sc->sc_rbufaddr[i], LEBLEN, RIEBL_RES_END)) { 489 offset = RIEBL_RES_END - sc->sc_rbufaddr[i]; 490 } 491 sc->sc_rbufaddr[i] += offset; 492 } 493 494 for(i = 0; i < sc->sc_ntbuf; i++) { 495 if (WITHIN(sc->sc_tbufaddr[i], LEBLEN, RIEBL_RES_START) 496 || WITHIN(sc->sc_tbufaddr[i], LEBLEN, RIEBL_RES_END)) { 497 offset = RIEBL_RES_END - sc->sc_tbufaddr[i]; 498 } 499 sc->sc_tbufaddr[i] += offset; 500 } 501 } 502 503 static int 504 nm93c06_read(iot, ioh, nm93c06reg) 505 bus_space_tag_t iot; 506 bus_space_handle_t ioh; 507 int nm93c06reg; 508 { 509 int bar; 510 int shift; 511 int bits = 0x180 | (nm93c06reg & 0xf); 512 int data = 0; 513 514 bar = 1<<BVME410_CS_SHIFT; 515 bus_space_write_2(iot, ioh, BVME410_BAR, bar); 516 delay(1); /* tCSS = 1 us */ 517 for (shift = 9; shift >= 0; shift--) { 518 if (((bits >> shift) & 1) == 1) 519 bar |= 1<<BVME410_DIN_SHIFT; 520 else 521 bar &= ~(1<<BVME410_DIN_SHIFT); 522 bus_space_write_2(iot, ioh, BVME410_BAR, bar); 523 delay(1); /* tDIS = 0.4 us */ 524 bar |= 1<<BVME410_CLK_SHIFT; 525 bus_space_write_2(iot, ioh, BVME410_BAR, bar); 526 delay(2); /* tSKH = 1 us, tSKH + tSKL >= 4 us */ 527 bar &= ~(1<<BVME410_CLK_SHIFT); 528 bus_space_write_2(iot, ioh, BVME410_BAR, bar); 529 delay(2); /* tSKL = 1 us, tSKH + tSKL >= 4 us */ 530 } 531 bar &= ~(1<<BVME410_DIN_SHIFT); 532 for (shift = 15; shift >= 0; shift--) { 533 delay(1); /* tDIS = 100 ns, BVM manual says 0.4 us */ 534 bar |= 1<<BVME410_CLK_SHIFT; 535 bus_space_write_2(iot, ioh, BVME410_BAR, bar); 536 delay(2); /* tSKH = 1 us, tSKH + tSKL >= 4 us */ 537 data |= (bus_space_read_2(iot, ioh, BVME410_BAR) & 1) << shift; 538 bar &= ~(1<<BVME410_CLK_SHIFT); 539 bus_space_write_2(iot, ioh, BVME410_BAR, bar); 540 delay(2); /* tSKL = 1 us, tSKH + tSKL >= 4 us */ 541 } 542 bar &= ~(1<<BVME410_CS_SHIFT); 543 bus_space_write_2(iot, ioh, BVME410_BAR, bar); 544 delay(1); /* tCS = 1 us */ 545 return data; 546 } 547 548 static int 549 bvme410_mem_size(memt, mem_addr) 550 bus_space_tag_t memt; 551 u_long mem_addr; 552 { 553 bus_space_handle_t memh; 554 int r; 555 556 if (bus_space_map(memt, mem_addr, 256*1024, 0, &memh)) 557 return VMECF_MEMSIZ_DEFAULT; 558 if (!bus_space_peek_1(memt, memh, 0)) { 559 bus_space_unmap(memt, (caddr_t)mem_addr, 256*1024); 560 return VMECF_MEMSIZ_DEFAULT; 561 } 562 bus_space_write_1(memt, memh, 0, 128); 563 bus_space_write_1(memt, memh, 64*1024, 32); 564 bus_space_write_1(memt, memh, 32*1024, 8); 565 r = (int)(bus_space_read_1(memt, memh, 0) * 2048); 566 bus_space_unmap(memt, (caddr_t)mem_addr, 256*1024); 567 return r; 568 } 569 570 /* 571 * Need to be careful when writing to the bvme410 dual port memory. 572 * Continue writing each byte until it reads back the same. 573 */ 574 575 static void 576 bvme410_copytobuf(sc, from, boff, len) 577 struct lance_softc *sc; 578 void *from; 579 int boff, len; 580 { 581 volatile char *buf = (volatile char *) sc->sc_mem; 582 char *f = (char *) from; 583 584 for (buf += boff; len; buf++,f++,len--) 585 while (*buf != *f) 586 *buf = *f; 587 } 588 589 static void 590 bvme410_zerobuf(sc, boff, len) 591 struct lance_softc *sc; 592 int boff, len; 593 { 594 volatile char *buf = (volatile char *)sc->sc_mem; 595 596 for (buf += boff; len; buf++,len--) 597 while (*buf != '\0') 598 *buf = '\0'; 599 } 600 601
Indexes created Tue Sep 30 20:09:53 GMT 2025