intr.h revision 1.12
1/* $NetBSD: intr.h,v 1.12 2001/01/14 02:00:39 thorpej Exp $ */ 2 3/*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39#ifndef _BEBOX_INTR_H_ 40#define _BEBOX_INTR_H_ 41 42/* Interrupt priority `levels'. */ 43#define IPL_NONE 9 /* nothing */ 44#define IPL_SOFTCLOCK 8 /* software clock interrupt */ 45#define IPL_SOFTNET 7 /* software network interrupt */ 46#define IPL_BIO 6 /* block I/O */ 47#define IPL_NET 5 /* network */ 48#define IPL_SOFTSERIAL 4 /* software serial interrupt */ 49#define IPL_TTY 3 /* terminal */ 50#define IPL_IMP 3 /* memory allocation */ 51#define IPL_AUDIO 2 /* audio */ 52#define IPL_CLOCK 1 /* clock */ 53#define IPL_HIGH 1 /* everything */ 54#define IPL_SERIAL 0 /* serial */ 55#define NIPL 10 56 57/* Interrupt sharing types. */ 58#define IST_NONE 0 /* none */ 59#define IST_PULSE 1 /* pulsed */ 60#define IST_EDGE 2 /* edge-triggered */ 61#define IST_LEVEL 3 /* level-triggered */ 62 63#ifndef _LOCORE 64 65/* 66 * Interrupt handler chains. intr_establish() inserts a handler into 67 * the list. The handler is called with its (single) argument. 68 */ 69struct intrhand { 70 int (*ih_fun) __P((void *)); 71 void *ih_arg; 72 u_long ih_count; 73 struct intrhand *ih_next; 74 int ih_level; 75 int ih_irq; 76}; 77 78void setsoftclock __P((void)); 79void clearsoftclock __P((void)); 80int splsoftclock __P((void)); 81void setsoftnet __P((void)); 82void clearsoftnet __P((void)); 83int splsoftnet __P((void)); 84 85void do_pending_int __P((void)); 86 87static __inline int splraise __P((int)); 88static __inline int spllower __P((int)); 89static __inline void splx __P((int)); 90static __inline void set_sint __P((int)); 91 92extern volatile int cpl, ipending, astpending, tickspending; 93extern int imask[]; 94extern long intrcnt[]; 95 96/* 97 * Reorder protection in the following inline functions is 98 * achived with the "eieio" instruction which the assembler 99 * seems to detect and then doen't move instructions past.... 100 */ 101static __inline int 102splraise(newcpl) 103 int newcpl; 104{ 105 int oldcpl; 106 107 __asm__ volatile("sync; eieio\n"); /* don't reorder.... */ 108 oldcpl = cpl; 109 cpl = oldcpl | newcpl; 110 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 111 return(oldcpl); 112} 113 114static __inline void 115splx(newcpl) 116 int newcpl; 117{ 118 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 119 cpl = newcpl; 120 if(ipending & ~newcpl) 121 do_pending_int(); 122 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 123} 124 125static __inline int 126spllower(newcpl) 127 int newcpl; 128{ 129 int oldcpl; 130 131 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 132 oldcpl = cpl; 133 cpl = newcpl; 134 if(ipending & ~newcpl) 135 do_pending_int(); 136 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 137 return(oldcpl); 138} 139 140/* Following code should be implemented with lwarx/stwcx to avoid 141 * the disable/enable. i need to read the manual once more.... */ 142static __inline void 143set_sint(pending) 144 int pending; 145{ 146 int msrsave; 147 148 __asm__ ("mfmsr %0" : "=r"(msrsave)); 149 __asm__ volatile ("mtmsr %0" :: "r"(msrsave & ~PSL_EE)); 150 ipending |= pending; 151 __asm__ volatile ("mtmsr %0" :: "r"(msrsave)); 152} 153 154#define ICU_LEN 32 155#define IRQ_SLAVE 2 156#define LEGAL_IRQ(x) ((x) >= 0 && (x) < ICU_LEN && (x) != IRQ_SLAVE) 157 158#define MOTHER_BOARD_REG 0x7ffff000 159#define CPU0_INT_MASK 0x0f0 160#define CPU1_INT_MASK 0x1f0 161#define INT_STATE_REG 0x2f0 162 163#define SINT_CLOCK 0x20000000 164#define SINT_NET 0x40000000 165#define SINT_SERIAL 0x80000000 166#define SPL_CLOCK 0x00000001 167#define SINT_MASK (SINT_CLOCK|SINT_NET|SINT_SERIAL) 168 169#define CNT_SINT_NET 29 170#define CNT_SINT_CLOCK 30 171#define CNT_SINT_SERIAL 31 172#define CNT_CLOCK 0 173 174#define splbio() splraise(imask[IPL_BIO]) 175#define splnet() splraise(imask[IPL_NET]) 176#define spltty() splraise(imask[IPL_TTY]) 177#define splclock() splraise(imask[IPL_CLOCK]) 178#define splimp() splraise(imask[IPL_IMP]) 179#define splvm() splraise(imask[IPL_IMP]) 180#define splserial() splraise(imask[IPL_SERIAL]) 181#define splstatclock() splclock() 182#define spllowersoftclock() spllower(imask[IPL_SOFTCLOCK]) 183#define splsoftclock() splraise(imask[IPL_SOFTCLOCK]) 184#define splsoftnet() splraise(imask[IPL_SOFTNET]) 185#define splsoftserial() splraise(imask[IPL_SOFTSERIAL]) 186 187#define spllpt() spltty() 188 189#define setsoftclock() set_sint(SINT_CLOCK); 190#define setsoftnet() set_sint(SINT_NET); 191#define setsoftserial() set_sint(SINT_SERIAL); 192 193#define splhigh() splraise(imask[IPL_HIGH]) 194#define spl0() spllower(0) 195 196#define splsched() splhigh() 197#define spllock() splhigh() 198 199#endif /* !_LOCORE */ 200 201#endif /* !_BEBOX_INTR_H_ */ 202