intr.h revision 1.16
1/* $NetBSD: intr.h,v 1.16 2002/02/11 11:19:28 wiz Exp $ */ 2 3/*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39#ifndef _BEBOX_INTR_H_ 40#define _BEBOX_INTR_H_ 41 42/* Interrupt priority `levels'. */ 43#define IPL_NONE 9 /* nothing */ 44#define IPL_SOFTCLOCK 8 /* software clock interrupt */ 45#define IPL_SOFTNET 7 /* software network interrupt */ 46#define IPL_BIO 6 /* block I/O */ 47#define IPL_NET 5 /* network */ 48#define IPL_SOFTSERIAL 4 /* software serial interrupt */ 49#define IPL_TTY 3 /* terminal */ 50#define IPL_IMP 3 /* memory allocation */ 51#define IPL_AUDIO 2 /* audio */ 52#define IPL_CLOCK 1 /* clock */ 53#define IPL_HIGH 1 /* everything */ 54#define IPL_SERIAL 0 /* serial */ 55#define NIPL 10 56 57/* Interrupt sharing types. */ 58#define IST_NONE 0 /* none */ 59#define IST_PULSE 1 /* pulsed */ 60#define IST_EDGE 2 /* edge-triggered */ 61#define IST_LEVEL 3 /* level-triggered */ 62 63#ifndef _LOCORE 64 65/* 66 * Interrupt handler chains. intr_establish() inserts a handler into 67 * the list. The handler is called with its (single) argument. 68 */ 69struct intrhand { 70 int (*ih_fun) __P((void *)); 71 void *ih_arg; 72 u_long ih_count; 73 struct intrhand *ih_next; 74 int ih_level; 75 int ih_irq; 76}; 77 78void setsoftclock __P((void)); 79void clearsoftclock __P((void)); 80int splsoftclock __P((void)); 81void setsoftnet __P((void)); 82void clearsoftnet __P((void)); 83int splsoftnet __P((void)); 84 85void do_pending_int __P((void)); 86 87void ext_intr __P((void)); 88void *intr_establish __P((int, int, int, int (*)(void *), void *)); 89void intr_disestablish __P((void *)); 90void intr_calculatemasks __P((void)); 91int isa_intr __P((void)); 92void isa_intr_mask __P((int)); 93void isa_intr_clr __P((int)); 94 95void enable_intr __P((void)); 96void disable_intr __P((void)); 97 98static __inline int splraise __P((int)); 99static __inline int spllower __P((int)); 100static __inline void splx __P((int)); 101static __inline void set_sint __P((int)); 102 103extern volatile int cpl, ipending, astpending, tickspending; 104extern int imask[]; 105extern long intrcnt[]; 106 107/* 108 * Reorder protection in the following inline functions is 109 * achieved with the "eieio" instruction which the assembler 110 * seems to detect and then doesn't move instructions past.... 111 */ 112static __inline int 113splraise(newcpl) 114 int newcpl; 115{ 116 int oldcpl; 117 118 __asm__ volatile("sync; eieio\n"); /* don't reorder.... */ 119 oldcpl = cpl; 120 cpl = oldcpl | newcpl; 121 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 122 return(oldcpl); 123} 124 125static __inline void 126splx(newcpl) 127 int newcpl; 128{ 129 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 130 cpl = newcpl; 131 if(ipending & ~newcpl) 132 do_pending_int(); 133 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 134} 135 136static __inline int 137spllower(newcpl) 138 int newcpl; 139{ 140 int oldcpl; 141 142 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 143 oldcpl = cpl; 144 cpl = newcpl; 145 if(ipending & ~newcpl) 146 do_pending_int(); 147 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 148 return(oldcpl); 149} 150 151/* Following code should be implemented with lwarx/stwcx to avoid 152 * the disable/enable. i need to read the manual once more.... */ 153static __inline void 154set_sint(pending) 155 int pending; 156{ 157 int msrsave; 158 159 __asm__ ("mfmsr %0" : "=r"(msrsave)); 160 __asm__ volatile ("mtmsr %0" :: "r"(msrsave & ~PSL_EE)); 161 ipending |= pending; 162 __asm__ volatile ("mtmsr %0" :: "r"(msrsave)); 163} 164 165#define ICU_LEN 32 166#define IRQ_SLAVE 2 167#define LEGAL_IRQ(x) ((x) >= 0 && (x) < ICU_LEN && (x) != IRQ_SLAVE) 168 169#define MOTHER_BOARD_REG 0x7ffff000 170#define CPU0_INT_MASK 0x0f0 171#define CPU1_INT_MASK 0x1f0 172#define INT_STATE_REG 0x2f0 173 174#define SINT_CLOCK 0x20000000 175#define SINT_NET 0x40000000 176#define SINT_SERIAL 0x80000000 177#define SPL_CLOCK 0x00000001 178#define SINT_MASK (SINT_CLOCK|SINT_NET|SINT_SERIAL) 179 180#define CNT_SINT_NET 29 181#define CNT_SINT_CLOCK 30 182#define CNT_SINT_SERIAL 31 183#define CNT_CLOCK 0 184 185#define splbio() splraise(imask[IPL_BIO]) 186#define splnet() splraise(imask[IPL_NET]) 187#define spltty() splraise(imask[IPL_TTY]) 188#define splclock() splraise(imask[IPL_CLOCK]) 189#define splvm() splraise(imask[IPL_IMP]) 190#define splserial() splraise(imask[IPL_SERIAL]) 191#define splstatclock() splclock() 192#define spllowersoftclock() spllower(imask[IPL_SOFTCLOCK]) 193#define splsoftclock() splraise(imask[IPL_SOFTCLOCK]) 194#define splsoftnet() splraise(imask[IPL_SOFTNET]) 195#define splsoftserial() splraise(imask[IPL_SOFTSERIAL]) 196 197#define spllpt() spltty() 198 199#define setsoftclock() set_sint(SINT_CLOCK); 200#define setsoftnet() set_sint(SINT_NET); 201#define setsoftserial() set_sint(SINT_SERIAL); 202 203#define splhigh() splraise(imask[IPL_HIGH]) 204#define spl0() spllower(0) 205 206#define splsched() splhigh() 207#define spllock() splhigh() 208 209#endif /* !_LOCORE */ 210 211#endif /* !_BEBOX_INTR_H_ */ 212