intr.h revision 1.20
1/* $NetBSD: intr.h,v 1.20 2005/12/11 12:17:03 christos Exp $ */ 2 3/*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39#ifndef _BEBOX_INTR_H_ 40#define _BEBOX_INTR_H_ 41 42/* Interrupt priority `levels'. */ 43#define IPL_NONE 9 /* nothing */ 44#define IPL_SOFTCLOCK 8 /* software clock interrupt */ 45#define IPL_SOFTNET 7 /* software network interrupt */ 46#define IPL_BIO 6 /* block I/O */ 47#define IPL_NET 5 /* network */ 48#define IPL_SOFTSERIAL 4 /* software serial interrupt */ 49#define IPL_TTY 3 /* terminal */ 50#define IPL_VM 3 /* memory allocation */ 51#define IPL_AUDIO 2 /* audio */ 52#define IPL_CLOCK 1 /* clock */ 53#define IPL_HIGH 1 /* everything */ 54#define IPL_SERIAL 0 /* serial */ 55#define NIPL 10 56 57/* Interrupt sharing types. */ 58#define IST_NONE 0 /* none */ 59#define IST_PULSE 1 /* pulsed */ 60#define IST_EDGE 2 /* edge-triggered */ 61#define IST_LEVEL 3 /* level-triggered */ 62 63#ifndef _LOCORE 64 65#define CLKF_BASEPRI(frame) ((frame)->pri == 0) 66/* 67 * Interrupt handler chains. intr_establish() inserts a handler into 68 * the list. The handler is called with its (single) argument. 69 */ 70struct intrhand { 71 int (*ih_fun) __P((void *)); 72 void *ih_arg; 73 u_long ih_count; 74 struct intrhand *ih_next; 75 int ih_level; 76 int ih_irq; 77}; 78 79void do_pending_int __P((void)); 80 81void ext_intr __P((void)); 82void *intr_establish __P((int, int, int, int (*)(void *), void *)); 83void intr_disestablish __P((void *)); 84void intr_calculatemasks __P((void)); 85int isa_intr __P((void)); 86void isa_intr_mask __P((int)); 87void isa_intr_clr __P((int)); 88 89void enable_intr __P((void)); 90void disable_intr __P((void)); 91 92static __inline int splraise __P((int)); 93static __inline int spllower __P((int)); 94static __inline void splx __P((int)); 95static __inline void set_sint __P((int)); 96 97extern volatile int cpl, ipending, astpending, tickspending; 98extern int imask[]; 99extern long intrcnt[]; 100 101/* 102 * Reorder protection in the following inline functions is 103 * achieved with the "eieio" instruction which the assembler 104 * seems to detect and then doesn't move instructions past.... 105 */ 106static __inline int 107splraise(newcpl) 108 int newcpl; 109{ 110 int oldcpl; 111 112 __asm__ volatile("sync; eieio\n"); /* don't reorder.... */ 113 oldcpl = cpl; 114 cpl = oldcpl | newcpl; 115 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 116 return(oldcpl); 117} 118 119static __inline void 120splx(newcpl) 121 int newcpl; 122{ 123 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 124 cpl = newcpl; 125 if(ipending & ~newcpl) 126 do_pending_int(); 127 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 128} 129 130static __inline int 131spllower(newcpl) 132 int newcpl; 133{ 134 int oldcpl; 135 136 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 137 oldcpl = cpl; 138 cpl = newcpl; 139 if(ipending & ~newcpl) 140 do_pending_int(); 141 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 142 return(oldcpl); 143} 144 145/* Following code should be implemented with lwarx/stwcx to avoid 146 * the disable/enable. i need to read the manual once more.... */ 147static __inline void 148set_sint(pending) 149 int pending; 150{ 151 int msrsave; 152 153 __asm__ ("mfmsr %0" : "=r"(msrsave)); 154 __asm__ volatile ("mtmsr %0" :: "r"(msrsave & ~PSL_EE)); 155 ipending |= pending; 156 __asm__ volatile ("mtmsr %0" :: "r"(msrsave)); 157} 158 159#define ICU_LEN 32 160#define IRQ_SLAVE 2 161#define LEGAL_IRQ(x) ((x) >= 0 && (x) < ICU_LEN && (x) != IRQ_SLAVE) 162 163#define MOTHER_BOARD_REG 0x7ffff000 164#define CPU0_INT_MASK 0x0f0 165#define CPU1_INT_MASK 0x1f0 166#define INT_STATE_REG 0x2f0 167 168#define SINT_CLOCK 0x20000000 169#define SINT_NET 0x40000000 170#define SINT_SERIAL 0x80000000 171#define SPL_CLOCK 0x00000001 172#define SINT_MASK (SINT_CLOCK|SINT_NET|SINT_SERIAL) 173 174#define CNT_SINT_NET 29 175#define CNT_SINT_CLOCK 30 176#define CNT_SINT_SERIAL 31 177#define CNT_CLOCK 0 178 179#define splbio() splraise(imask[IPL_BIO]) 180#define splnet() splraise(imask[IPL_NET]) 181#define spltty() splraise(imask[IPL_TTY]) 182#define splclock() splraise(imask[IPL_CLOCK]) 183#define splvm() splraise(imask[IPL_VM]) 184#define splserial() splraise(imask[IPL_SERIAL]) 185#define splstatclock() splclock() 186#define spllowersoftclock() spllower(imask[IPL_SOFTCLOCK]) 187#define splsoftclock() splraise(imask[IPL_SOFTCLOCK]) 188#define splsoftnet() splraise(imask[IPL_SOFTNET]) 189#define splsoftserial() splraise(imask[IPL_SOFTSERIAL]) 190 191#define spllpt() spltty() 192 193#define setsoftclock() set_sint(SINT_CLOCK); 194#define setsoftnet() set_sint(SINT_NET); 195#define setsoftserial() set_sint(SINT_SERIAL); 196 197#define splhigh() splraise(imask[IPL_HIGH]) 198#define spl0() spllower(0) 199 200#define splsched() splhigh() 201#define spllock() splhigh() 202 203#endif /* !_LOCORE */ 204 205#endif /* !_BEBOX_INTR_H_ */ 206