zs.c revision 1.1.16.1
1 /* $NetBSD: zs.c,v 1.1.16.1 2002/05/19 08:14:15 gehenna Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 */ 45 46 #include "opt_ddb.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/conf.h> 51 #include <sys/device.h> 52 #include <sys/file.h> 53 #include <sys/ioctl.h> 54 #include <sys/kernel.h> 55 #include <sys/malloc.h> 56 #include <sys/proc.h> 57 #include <sys/tty.h> 58 #include <sys/time.h> 59 #include <sys/syslog.h> 60 61 #include <dev/cons.h> 62 #include <dev/ic/z8530reg.h> 63 64 #include <machine/cpu.h> 65 66 #include <machine/z8530var.h> 67 #include <cesfic/dev/zsvar.h> 68 69 int zs_getc __P((void*)); 70 void zs_putc __P((void*, int)); 71 72 static struct zs_chanstate zs_conschan_store; 73 static int zs_hwflags[2][2]; 74 int zssoftpending; 75 76 extern struct cfdriver zsc_cd; 77 78 u_char zs_init_reg[16] = { 79 0, /* 0: CMD (reset, etc.) */ 80 0, /* 1: No interrupts yet. */ 81 0x18 + ZSHARD_PRI, /* IVECT */ 82 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 83 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 84 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 85 0, /* 6: TXSYNC/SYNCLO */ 86 0, /* 7: RXSYNC/SYNCHI */ 87 0, /* 8: alias for data port */ 88 ZSWR9_MASTER_IE, 89 0, /*10: Misc. TX/RX control bits */ 90 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 91 11, /*12: BAUDLO (default=9600) */ 92 0, /*13: BAUDHI (default=9600) */ 93 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 94 ZSWR15_BREAK_IE | ZSWR15_DCD_IE, 95 }; 96 97 static int zsc_print __P((void *, const char *)); 98 int zscngetc __P((dev_t)); 99 void zscnputc __P((dev_t, int)); 100 101 static struct consdev zscons = { NULL, NULL, 102 zscngetc, zscnputc, nullcnpollc, 0, NODEV, 1 }; 103 104 void 105 zs_config(zsc, base) 106 struct zsc_softc *zsc; 107 char *base; 108 { 109 struct zsc_attach_args zsc_args; 110 struct zs_chanstate *cs; 111 int zsc_unit, channel, s; 112 113 zsc_unit = zsc->zsc_dev.dv_unit; 114 printf(": Zilog 8530 SCC\n"); 115 116 /* 117 * Initialize software state for each channel. 118 */ 119 for (channel = 0; channel < 2; channel++) { 120 zsc_args.channel = channel; 121 zsc_args.hwflags = zs_hwflags[zsc_unit][channel]; 122 123 /* 124 * If we're the console, copy the channel state, and 125 * adjust the console channel pointer. 126 */ 127 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) { 128 cs = &zs_conschan_store; 129 } else { 130 cs = malloc(sizeof(struct zs_chanstate), 131 M_DEVBUF, M_NOWAIT); 132 if(channel==0){ 133 cs->cs_reg_csr = base+7; 134 cs->cs_reg_data = base+15; 135 } else { 136 cs->cs_reg_csr = base+3; 137 cs->cs_reg_data = base+11; 138 } 139 bcopy(zs_init_reg, cs->cs_creg, 16); 140 bcopy(zs_init_reg, cs->cs_preg, 16); 141 cs->cs_defspeed = 9600; 142 } 143 zsc->zsc_cs[channel] = cs; 144 145 cs->cs_defcflag = CREAD | CS8 | HUPCL; 146 147 /* Make these correspond to cs_defcflag (-crtscts) */ 148 cs->cs_rr0_dcd = ZSRR0_DCD; 149 cs->cs_rr0_cts = 0; 150 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 151 cs->cs_wr5_rts = 0; 152 153 cs->cs_channel = channel; 154 cs->cs_private = NULL; 155 cs->cs_ops = &zsops_null; 156 cs->cs_brg_clk = 4000000 / 16; 157 158 /* 159 * Clear the master interrupt enable. 160 * The INTENA is common to both channels, 161 * so just do it on the A channel. 162 */ 163 if (channel == 0) { 164 zs_write_reg(cs, 9, 0); 165 } 166 167 /* 168 * Look for a child driver for this channel. 169 * The child attach will setup the hardware. 170 */ 171 if (!config_found(&zsc->zsc_dev, (void *)&zsc_args, zsc_print)) { 172 /* No sub-driver. Just reset it. */ 173 u_char reset = (channel == 0) ? 174 ZSWR9_A_RESET : ZSWR9_B_RESET; 175 s = splzs(); 176 zs_write_reg(cs, 9, reset); 177 splx(s); 178 } 179 } 180 } 181 182 static int 183 zsc_print(aux, name) 184 void *aux; 185 const char *name; 186 { 187 struct zsc_attach_args *args = aux; 188 189 if (name != NULL) 190 printf("%s: ", name); 191 192 if (args->channel != -1) 193 printf(" channel %d", args->channel); 194 195 return UNCONF; 196 } 197 198 int 199 zshard(arg) 200 void *arg; 201 { 202 register struct zsc_softc *zsc; 203 register int unit, rval; 204 205 rval = 0; 206 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 207 zsc = zsc_cd.cd_devs[unit]; 208 if (zsc == NULL) 209 continue; 210 rval |= zsc_intr_hard(zsc); 211 if ((zsc->zsc_cs[0]->cs_softreq) || 212 (zsc->zsc_cs[1]->cs_softreq)) 213 { 214 /* zsc_req_softint(zsc); */ 215 /* We are at splzs here, so no need to lock. */ 216 if (zssoftpending == 0) { 217 zssoftpending = 1; 218 setsoftzs(); 219 } 220 } 221 } 222 return (rval); 223 } 224 225 void 226 softzs() 227 { 228 register struct zsc_softc *zsc; 229 register int unit; 230 231 /* This is not the only ISR on this IPL. */ 232 if (zssoftpending == 0) 233 return; 234 235 /* 236 * The soft intr. bit will be set by zshard only if 237 * the variable zssoftpending is zero. 238 */ 239 zssoftpending = 0; 240 241 for (unit = 0; unit < zsc_cd.cd_ndevs; ++unit) { 242 zsc = zsc_cd.cd_devs[unit]; 243 if (zsc == NULL) 244 continue; 245 (void) zsc_intr_soft(zsc); 246 } 247 return; 248 } 249 250 u_char 251 zs_read_reg(cs, reg) 252 struct zs_chanstate *cs; 253 u_char reg; 254 { 255 u_char val; 256 257 *cs->cs_reg_csr = reg; 258 ZS_DELAY(); 259 val = *cs->cs_reg_csr; 260 ZS_DELAY(); 261 return val; 262 } 263 264 void 265 zs_write_reg(cs, reg, val) 266 struct zs_chanstate *cs; 267 u_char reg, val; 268 { 269 *cs->cs_reg_csr = reg; 270 ZS_DELAY(); 271 *cs->cs_reg_csr = val; 272 ZS_DELAY(); 273 } 274 275 u_char zs_read_csr(cs) 276 struct zs_chanstate *cs; 277 { 278 register u_char val; 279 280 val = *cs->cs_reg_csr; 281 ZS_DELAY(); 282 return val; 283 } 284 285 void zs_write_csr(cs, val) 286 struct zs_chanstate *cs; 287 u_char val; 288 { 289 *cs->cs_reg_csr = val; 290 ZS_DELAY(); 291 } 292 293 u_char zs_read_data(cs) 294 struct zs_chanstate *cs; 295 { 296 register u_char val; 297 298 val = *cs->cs_reg_data; 299 ZS_DELAY(); 300 return val; 301 } 302 303 void zs_write_data(cs, val) 304 struct zs_chanstate *cs; 305 u_char val; 306 { 307 *cs->cs_reg_data = val; 308 ZS_DELAY(); 309 } 310 311 int 312 zs_set_speed(cs, bps) 313 struct zs_chanstate *cs; 314 int bps; /* bits per second */ 315 { 316 int tconst, real_bps; 317 318 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 319 320 if (tconst < 0) 321 return (EINVAL); 322 323 /* Convert back to make sure we can do it. */ 324 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 325 #if 0 326 /* XXX - Allow some tolerance here? */ 327 if (real_bps != bps) 328 return (EINVAL); 329 #endif 330 cs->cs_preg[12] = tconst; 331 cs->cs_preg[13] = tconst >> 8; 332 333 return (0); 334 } 335 336 int 337 zs_set_modes(cs, cflag) 338 struct zs_chanstate *cs; 339 int cflag; /* bits per second */ 340 { 341 int s; 342 343 /* 344 * Output hardware flow control on the chip is horrendous: 345 * if carrier detect drops, the receiver is disabled, and if 346 * CTS drops, the transmitter is stoped IN MID CHARACTER! 347 * Therefore, NEVER set the HFC bit, and instead use the 348 * status interrupt to detect CTS changes. 349 */ 350 s = splzs(); 351 #if 0 /* XXX - See below. */ 352 if (cflag & CLOCAL) { 353 cs->cs_rr0_dcd = 0; 354 cs->cs_preg[15] &= ~ZSWR15_DCD_IE; 355 } else { 356 /* XXX - Need to notice DCD change here... */ 357 cs->cs_rr0_dcd = ZSRR0_DCD; 358 cs->cs_preg[15] |= ZSWR15_DCD_IE; 359 } 360 #endif /* XXX */ 361 if (cflag & CRTSCTS) { 362 cs->cs_wr5_dtr = ZSWR5_DTR; 363 cs->cs_wr5_rts = ZSWR5_RTS; 364 cs->cs_rr0_cts = ZSRR0_CTS; 365 cs->cs_preg[15] |= ZSWR15_CTS_IE; 366 } else { 367 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 368 cs->cs_wr5_rts = 0; 369 cs->cs_rr0_cts = 0; 370 cs->cs_preg[15] &= ~ZSWR15_CTS_IE; 371 } 372 splx(s); 373 374 /* Caller will stuff the pending registers. */ 375 return (0); 376 } 377 378 /* 379 * Handle user request to enter kernel debugger. 380 */ 381 void 382 zs_abort(cs) 383 struct zs_chanstate *cs; 384 { 385 int rr0; 386 387 /* Wait for end of break to avoid PROM abort. */ 388 /* XXX - Limit the wait? */ 389 do { 390 rr0 = *cs->cs_reg_csr; 391 ZS_DELAY(); 392 } while (rr0 & ZSRR0_BREAK); 393 #ifdef DDB 394 console_debugger(); 395 #endif 396 } 397 398 /* 399 * Polled input char. 400 */ 401 int 402 zs_getc(arg) 403 void *arg; 404 { 405 register struct zs_chanstate *cs = arg; 406 register int s, c, rr0, stat; 407 408 s = splhigh(); 409 top: 410 /* Wait for a character to arrive. */ 411 do { 412 rr0 = *cs->cs_reg_csr; 413 ZS_DELAY(); 414 } while ((rr0 & ZSRR0_RX_READY) == 0); 415 416 /* Read error register. */ 417 stat = zs_read_reg(cs, 1) & (ZSRR1_FE | ZSRR1_DO | ZSRR1_PE); 418 if (stat) { 419 zs_write_csr(cs, ZSM_RESET_ERR); 420 goto top; 421 } 422 423 /* Read character. */ 424 c = *cs->cs_reg_data; 425 ZS_DELAY(); 426 splx(s); 427 428 return (c); 429 } 430 431 /* 432 * Polled output char. 433 */ 434 void 435 zs_putc(arg, c) 436 void *arg; 437 int c; 438 { 439 register struct zs_chanstate *cs = arg; 440 register int s, rr0; 441 442 s = splhigh(); 443 /* Wait for transmitter to become ready. */ 444 do { 445 rr0 = *cs->cs_reg_csr; 446 ZS_DELAY(); 447 } while ((rr0 & ZSRR0_TX_READY) == 0); 448 449 *cs->cs_reg_data = c; 450 ZS_DELAY(); 451 splx(s); 452 } 453 454 int zscngetc(dev) 455 dev_t dev; 456 { 457 register struct zs_chanstate *cs = &zs_conschan_store; 458 register int c; 459 460 c = zs_getc(cs); 461 return (c); 462 } 463 464 void zscnputc(dev, c) 465 dev_t dev; 466 int c; 467 { 468 register struct zs_chanstate *cs = &zs_conschan_store; 469 470 zs_putc(cs, c); 471 } 472 473 /* 474 * Common parts of console init. 475 */ 476 void 477 zs_cninit(base) 478 void *base; 479 { 480 struct zs_chanstate *cs; 481 /* 482 * Pointer to channel state. Later, the console channel 483 * state is copied into the softc, and the console channel 484 * pointer adjusted to point to the new copy. 485 */ 486 cs = &zs_conschan_store; 487 zs_hwflags[0][0] = ZS_HWFLAG_CONSOLE; 488 489 /* Setup temporary chanstate. */ 490 cs->cs_reg_csr = base+7; 491 cs->cs_reg_data = base+15; 492 493 /* Initialize the pending registers. */ 494 bcopy(zs_init_reg, cs->cs_preg, 16); 495 cs->cs_preg[5] |= (ZSWR5_DTR | ZSWR5_RTS); 496 497 /* XXX: Preserve BAUD rate from boot loader. */ 498 /* XXX: Also, why reset the chip here? -gwr */ 499 /* cs->cs_defspeed = zs_get_speed(cs); */ 500 cs->cs_defspeed = 9600; /* XXX */ 501 502 /* Clear the master interrupt enable. */ 503 zs_write_reg(cs, 9, 0); 504 505 /* Reset the whole SCC chip. */ 506 zs_write_reg(cs, 9, ZSWR9_HARD_RESET); 507 508 /* Copy "pending" to "current" and H/W. */ 509 zs_loadchannelregs(cs); 510 511 /* Point the console at the SCC. */ 512 cn_tab = &zscons; 513 } 514
Indexes created Wed Oct 22 13:09:56 GMT 2025