interrupt.c revision 1.3
1 /* $NetBSD: interrupt.c,v 1.3 2008/05/14 13:29:27 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Izumi Tsutsui. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 2001 The NetBSD Foundation, Inc. 29 * All rights reserved. 30 * 31 * This code is derived from software contributed to The NetBSD Foundation 32 * by Jason R. Thorpe. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 44 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 45 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 46 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 47 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 48 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 49 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 50 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 51 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 53 * POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 /* 57 * Copyright (c) 2000 Soren S. Jorvang. All rights reserved. 58 * 59 * Redistribution and use in source and binary forms, with or without 60 * modification, are permitted provided that the following conditions 61 * are met: 62 * 1. Redistributions of source code must retain the above copyright 63 * notice, this list of conditions, and the following disclaimer. 64 * 2. Redistributions in binary form must reproduce the above copyright 65 * notice, this list of conditions and the following disclaimer in the 66 * documentation and/or other materials provided with the distribution. 67 * 68 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 69 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 70 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 71 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 72 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 73 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 74 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 75 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 76 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 77 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 78 * SUCH DAMAGE. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.3 2008/05/14 13:29:27 tsutsui Exp $"); 83 84 #include <sys/param.h> 85 #include <sys/malloc.h> 86 #include <sys/cpu.h> 87 #include <sys/intr.h> 88 89 #include <uvm/uvm_extern.h> 90 91 #include <mips/mips3_clock.h> 92 #include <machine/bus.h> 93 94 #include <dev/ic/i8259reg.h> 95 #include <dev/isa/isareg.h> 96 97 #include <cobalt/dev/gtreg.h> 98 99 #define ICU_LEVEL 4 100 #define IRQ_SLAVE 2 101 102 #define IO_ELCR 0x4d0 103 #define IO_ELCRSIZE 2 104 #define ELCR0 0 105 #define ELCR1 1 106 107 #define ICU1_READ(reg) \ 108 bus_space_read_1(icu_bst, icu1_bsh, (reg)) 109 #define ICU1_WRITE(reg, val) \ 110 bus_space_write_1(icu_bst, icu1_bsh, (reg), (val)) 111 #define ICU2_READ(reg) \ 112 bus_space_read_1(icu_bst, icu2_bsh, (reg)) 113 #define ICU2_WRITE(reg, val) \ 114 bus_space_write_1(icu_bst, icu2_bsh, (reg), (val)) 115 #define ELCR_READ(reg) \ 116 bus_space_read_1(icu_bst, elcr_bsh, (reg)) 117 #define ELCR_WRITE(reg, val) \ 118 bus_space_write_1(icu_bst, elcr_bsh, (reg), (val)) 119 120 static u_int icu_imask, icu_elcr; 121 static bus_space_tag_t icu_bst; 122 static bus_space_handle_t icu1_bsh, icu2_bsh, elcr_bsh; 123 124 struct icu_intrhead { 125 LIST_HEAD(, cobalt_intrhand) intr_q; 126 int intr_type; 127 struct evcnt intr_evcnt; 128 char intr_evname[32]; 129 }; 130 static struct icu_intrhead icu_intrtab[NICU_INT]; 131 132 struct cpu_intrhead { 133 struct cobalt_intrhand intr_ih; 134 struct evcnt intr_evcnt; 135 char intr_evname[32]; 136 }; 137 static struct cpu_intrhead cpu_intrtab[NCPU_INT]; 138 139 static int icu_intr(void *); 140 static void icu_set(void); 141 142 void 143 intr_init(void) 144 { 145 int i; 146 147 /* 148 * Initialize CPU interrupts. 149 */ 150 for (i = 0; i < NCPU_INT; i++) { 151 snprintf(cpu_intrtab[i].intr_evname, 152 sizeof(cpu_intrtab[i].intr_evname), "int %d", i); 153 evcnt_attach_dynamic(&cpu_intrtab[i].intr_evcnt, 154 EVCNT_TYPE_INTR, NULL, "mips", cpu_intrtab[i].intr_evname); 155 } 156 157 /* 158 * Initialize ICU interrupts. 159 */ 160 icu_bst = 0; /* XXX unused on cobalt */ 161 bus_space_map(icu_bst, PCIB_BASE + IO_ICU1, IO_ICUSIZE, 0, &icu1_bsh); 162 bus_space_map(icu_bst, PCIB_BASE + IO_ICU2, IO_ICUSIZE, 0, &icu2_bsh); 163 bus_space_map(icu_bst, PCIB_BASE + IO_ELCR, IO_ELCRSIZE, 0, &elcr_bsh); 164 165 /* All interrupts default to "masked off". */ 166 icu_imask = 0xffff; 167 168 /* All interrupts default to edge-triggered. */ 169 icu_elcr = 0; 170 171 /* Initialize master PIC */ 172 173 /* reset; program device, four bytes */ 174 ICU1_WRITE(PIC_ICW1, ICW1_SELECT | ICW1_IC4); 175 /* starting at this vector index */ 176 ICU1_WRITE(PIC_ICW2, 0); /* XXX */ 177 /* slave on line 2 */ 178 ICU1_WRITE(PIC_ICW3, ICW3_CASCADE(IRQ_SLAVE)); 179 /* special fully nested mode, 8086 mode */ 180 ICU1_WRITE(PIC_ICW4, ICW4_SFNM | ICW4_8086); 181 /* mask all interrupts */ 182 ICU1_WRITE(PIC_OCW1, icu_imask & 0xff); 183 /* special mask mode */ 184 ICU1_WRITE(PIC_OCW3, OCW3_SELECT | OCW3_SSMM | OCW3_SMM); 185 /* read IRR by default */ 186 ICU1_WRITE(PIC_OCW3, OCW3_SELECT | OCW3_RR); 187 188 /* Initialize slave PIC */ 189 190 /* reset; program device, four bytes */ 191 ICU2_WRITE(PIC_ICW1, ICW1_SELECT | ICW1_IC4); 192 /* starting at this vector index */ 193 ICU2_WRITE(PIC_ICW2, 8); /* XXX */ 194 /* slave connected to line 2 of master */ 195 ICU2_WRITE(PIC_ICW3, ICW3_SIC(IRQ_SLAVE)); 196 /* special fully nested mode, 8086 mode */ 197 ICU2_WRITE(PIC_ICW4, ICW4_SFNM | ICW4_8086); 198 /* mask all interrupts */ 199 ICU1_WRITE(PIC_OCW1, (icu_imask >> 8) & 0xff); 200 /* special mask mode */ 201 ICU2_WRITE(PIC_OCW3, OCW3_SELECT | OCW3_SSMM | OCW3_SMM); 202 /* read IRR by default */ 203 ICU2_WRITE(PIC_OCW3, OCW3_SELECT | OCW3_RR); 204 205 /* default to edge-triggered */ 206 ELCR_WRITE(ELCR0, icu_elcr & 0xff); 207 ELCR_WRITE(ELCR1, (icu_elcr >> 8) & 0xff); 208 209 wbflush(); 210 211 /* Initialize our interrupt table. */ 212 for (i = 0; i < NICU_INT; i++) { 213 LIST_INIT(&icu_intrtab[i].intr_q); 214 snprintf(icu_intrtab[i].intr_evname, 215 sizeof(icu_intrtab[i].intr_evname), "irq %d", i); 216 evcnt_attach_dynamic(&icu_intrtab[i].intr_evcnt, 217 EVCNT_TYPE_INTR, &cpu_intrtab[ICU_LEVEL].intr_evcnt, 218 "icu", icu_intrtab[i].intr_evname); 219 icu_intrtab[i].intr_type = IST_NONE; 220 } 221 222 cpu_intr_establish(ICU_LEVEL, IPL_NONE, icu_intr, NULL); 223 } 224 225 void * 226 icu_intr_establish(int irq, int type, int ipl, int (*func)(void *), void *arg) 227 { 228 struct cobalt_intrhand *ih; 229 int s; 230 231 if (irq >= NICU_INT || irq == IRQ_SLAVE || type == IST_NONE) 232 panic("%s: bad irq or type", __func__); 233 234 switch (icu_intrtab[irq].intr_type) { 235 case IST_NONE: 236 icu_intrtab[irq].intr_type = type; 237 break; 238 239 case IST_EDGE: 240 case IST_LEVEL: 241 if (type == icu_intrtab[irq].intr_type) 242 break; 243 /* FALLTHROUGH */ 244 case IST_PULSE: 245 /* 246 * We can't share interrupts in this case. 247 */ 248 return NULL; 249 } 250 251 ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT); 252 if (ih == NULL) 253 return NULL; 254 255 ih->ih_func = func; 256 ih->ih_arg = arg; 257 ih->ih_irq = irq; 258 ih->ih_cookie_type = COBALT_COOKIE_TYPE_ICU; 259 260 s = splhigh(); 261 262 /* Insert the handler into the table. */ 263 LIST_INSERT_HEAD(&icu_intrtab[irq].intr_q, ih, ih_q); 264 265 /* Enable it, set trigger mode. */ 266 icu_imask &= ~(1U << irq); 267 if (icu_intrtab[irq].intr_type == IST_LEVEL) 268 icu_elcr |= (1U << irq); 269 else 270 icu_elcr &= ~(1U << irq); 271 272 icu_set(); 273 274 splx(s); 275 276 return ih; 277 } 278 279 void 280 icu_intr_disestablish(void *cookie) 281 { 282 struct cobalt_intrhand *ih = cookie; 283 int s; 284 285 if (ih->ih_cookie_type == COBALT_COOKIE_TYPE_ICU) { 286 s = splhigh(); 287 288 LIST_REMOVE(ih, ih_q); 289 290 if (LIST_FIRST(&icu_intrtab[ih->ih_irq].intr_q) == NULL) { 291 icu_imask |= (1U << ih->ih_irq); 292 icu_set(); 293 } 294 splx(s); 295 free(ih, M_DEVBUF); 296 } 297 } 298 299 void 300 icu_set(void) 301 { 302 303 if ((icu_imask & 0xff00) != 0xff00) 304 icu_imask &= ~(1U << IRQ_SLAVE); 305 else 306 icu_imask |= (1U << IRQ_SLAVE); 307 308 ICU1_WRITE(PIC_OCW1, icu_imask); 309 ICU2_WRITE(PIC_OCW1, icu_imask >> 8); 310 311 ELCR_WRITE(ELCR0, icu_elcr); 312 ELCR_WRITE(ELCR1, icu_elcr >> 8); 313 } 314 315 int 316 icu_intr(void *arg) 317 { 318 struct cobalt_intrhand *ih; 319 int irq, handled; 320 321 handled = 0; 322 323 for (;;) { 324 /* check requested irq */ 325 ICU1_WRITE(PIC_OCW3, OCW3_SELECT | OCW3_POLL); 326 irq = ICU1_READ(PIC_OCW3); 327 if ((irq & OCW3_POLL_PENDING) == 0) 328 return handled; 329 330 irq = OCW3_POLL_IRQ(irq); 331 if (irq == IRQ_SLAVE) { 332 ICU2_WRITE(PIC_OCW3, OCW3_SELECT | OCW3_POLL); 333 irq = OCW3_POLL_IRQ(ICU2_READ(PIC_OCW3)) + 8; 334 } 335 336 icu_intrtab[irq].intr_evcnt.ev_count++; 337 LIST_FOREACH(ih, &icu_intrtab[irq].intr_q, ih_q) { 338 if (__predict_false(ih->ih_func == NULL)) 339 printf("%s: spurious interrupt (irq = %d)\n", 340 __func__, irq); 341 else if (__predict_true((*ih->ih_func)(ih->ih_arg))) { 342 handled = 1; 343 } 344 } 345 346 /* issue EOI to ack */ 347 if (irq >= 8) { 348 ICU2_WRITE(PIC_OCW2, 349 OCW2_SELECT | OCW2_SL | OCW2_EOI | 350 OCW2_ILS(irq - 8)); 351 irq = IRQ_SLAVE; 352 } 353 ICU1_WRITE(PIC_OCW2, 354 OCW2_SELECT | OCW2_SL | OCW2_EOI | OCW2_ILS(irq)); 355 } 356 } 357 358 void * 359 cpu_intr_establish(int level, int ipl, int (*func)(void *), void *arg) 360 { 361 struct cobalt_intrhand *ih; 362 363 if (level < 0 || level >= NCPU_INT) 364 panic("invalid interrupt level"); 365 366 ih = &cpu_intrtab[level].intr_ih; 367 368 if (ih->ih_func != NULL) 369 panic("cannot share CPU interrupts"); 370 371 ih->ih_cookie_type = COBALT_COOKIE_TYPE_CPU; 372 ih->ih_func = func; 373 ih->ih_arg = arg; 374 ih->ih_irq = NICU_INT + level; 375 376 return ih; 377 } 378 379 void 380 cpu_intr_disestablish(void *cookie) 381 { 382 struct cobalt_intrhand *ih = cookie; 383 384 if (ih->ih_cookie_type == COBALT_COOKIE_TYPE_CPU) { 385 ih->ih_func = NULL; 386 ih->ih_arg = NULL; 387 ih->ih_cookie_type = 0; 388 } 389 } 390 391 void 392 cpu_intr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending) 393 { 394 struct clockframe cf; 395 struct cobalt_intrhand *ih; 396 struct cpu_info *ci; 397 uint32_t handled; 398 399 handled = 0; 400 ci = curcpu(); 401 ci->ci_idepth++; 402 uvmexp.intrs++; 403 404 if (ipending & MIPS_INT_MASK_5) { 405 /* call the common MIPS3 clock interrupt handler */ 406 cf.pc = pc; 407 cf.sr = status; 408 mips3_clockintr(&cf); 409 410 handled |= MIPS_INT_MASK_5; 411 } 412 _splset((status & handled) | MIPS_SR_INT_IE); 413 414 if (__predict_false(ipending & MIPS_INT_MASK_0)) { 415 /* GT64x11 timer0 */ 416 volatile uint32_t *irq_src = 417 (uint32_t *)MIPS_PHYS_TO_KSEG1(GT_BASE + GT_INTR_CAUSE); 418 419 if (__predict_true((*irq_src & T0EXP) != 0)) { 420 /* GT64x11 timer is no longer used for hardclock(9) */ 421 *irq_src = 0; 422 } 423 handled |= MIPS_INT_MASK_0; 424 } 425 426 if (ipending & MIPS_INT_MASK_3) { 427 /* 16650 serial */ 428 ih = &cpu_intrtab[3].intr_ih; 429 if (__predict_true(ih->ih_func != NULL)) { 430 if (__predict_true((*ih->ih_func)(ih->ih_arg))) { 431 cpu_intrtab[3].intr_evcnt.ev_count++; 432 } 433 } 434 handled |= MIPS_INT_MASK_3; 435 } 436 _splset((status & handled) | MIPS_SR_INT_IE); 437 438 if (ipending & MIPS_INT_MASK_1) { 439 /* tulip primary */ 440 ih = &cpu_intrtab[1].intr_ih; 441 if (__predict_true(ih->ih_func != NULL)) { 442 if (__predict_true((*ih->ih_func)(ih->ih_arg))) { 443 cpu_intrtab[1].intr_evcnt.ev_count++; 444 } 445 } 446 handled |= MIPS_INT_MASK_1; 447 } 448 if (ipending & MIPS_INT_MASK_2) { 449 /* tulip secondary */ 450 ih = &cpu_intrtab[2].intr_ih; 451 if (__predict_true(ih->ih_func != NULL)) { 452 if (__predict_true((*ih->ih_func)(ih->ih_arg))) { 453 cpu_intrtab[2].intr_evcnt.ev_count++; 454 } 455 } 456 handled |= MIPS_INT_MASK_2; 457 } 458 459 if (ipending & MIPS_INT_MASK_4) { 460 /* ICU interrupts */ 461 ih = &cpu_intrtab[4].intr_ih; 462 if (__predict_true(ih->ih_func != NULL)) { 463 if (__predict_true((*ih->ih_func)(ih->ih_arg))) { 464 cpu_intrtab[4].intr_evcnt.ev_count++; 465 } 466 } 467 handled |= MIPS_INT_MASK_4; 468 } 469 cause &= ~handled; 470 _splset((status & ~cause & MIPS_HARD_INT_MASK) | MIPS_SR_INT_IE); 471 ci->ci_idepth--; 472 473 #ifdef __HAVE_FAST_SOFTINTS 474 /* software interrupt */ 475 ipending &= (MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0); 476 if (ipending == 0) 477 return; 478 _clrsoftintr(ipending); 479 softintr_dispatch(ipending); 480 #endif 481 } 482 483 484 static const int ipl2spl_table[] = { 485 [IPL_NONE] = 0, 486 [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0, 487 [IPL_SOFTNET] = MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1, 488 [IPL_VM] = SPLVM, 489 [IPL_SCHED] = SPLSCHED, 490 }; 491 492 ipl_cookie_t 493 makeiplcookie(ipl_t ipl) 494 { 495 496 return (ipl_cookie_t){._spl = ipl2spl_table[ipl]}; 497 } 498
Indexes created Tue Sep 23 14:10:03 GMT 2025