gt.c revision 1.27.6.1
1 /* $NetBSD: gt.c,v 1.27.6.1 2012/02/18 07:31:43 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Soren S. Jorvang. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: gt.c,v 1.27.6.1 2012/02/18 07:31:43 mrg Exp $"); 30 31 #include "opt_pci.h" 32 #include "pci.h" 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/conf.h> 37 #include <sys/device.h> 38 #include <sys/extent.h> 39 #include <sys/file.h> 40 #include <sys/intr.h> 41 #include <sys/ioctl.h> 42 #include <sys/kernel.h> 43 #include <sys/malloc.h> 44 #include <sys/proc.h> 45 #include <sys/select.h> 46 #include <sys/syslog.h> 47 #include <sys/systm.h> 48 #include <sys/tty.h> 49 #include <sys/uio.h> 50 51 #include <machine/autoconf.h> 52 53 #include <mips/cache.h> 54 55 #include <dev/pci/pcivar.h> 56 #ifdef PCI_NETBSD_CONFIGURE 57 #include <dev/pci/pciconf.h> 58 #endif 59 60 #include <cobalt/dev/gtreg.h> 61 62 struct gt_softc { 63 device_t sc_dev; 64 65 bus_space_tag_t sc_bst; 66 bus_space_handle_t sc_bsh; 67 struct cobalt_pci_chipset sc_pc; 68 }; 69 70 static int gt_match(device_t, cfdata_t, void *); 71 static void gt_attach(device_t, device_t, void *); 72 static int gt_print(void *aux, const char *pnp); 73 74 static void gt_timer_init(struct gt_softc *sc); 75 #if 0 /* unused */ 76 static void gt_timer0_init(void *); 77 static long gt_timer0_read(void *); 78 #endif 79 80 CFATTACH_DECL_NEW(gt, sizeof(struct gt_softc), 81 gt_match, gt_attach, NULL, NULL); 82 83 static int 84 gt_match(device_t parent, cfdata_t cf, void *aux) 85 { 86 87 return 1; 88 } 89 90 #define GT_REG_REGION 0x1000 91 92 static void 93 gt_attach(device_t parent, device_t self, void *aux) 94 { 95 struct gt_softc *sc = device_private(self); 96 struct mainbus_attach_args *ma = aux; 97 #if NPCI > 0 98 pci_chipset_tag_t pc; 99 struct pcibus_attach_args pba; 100 #endif 101 102 sc->sc_dev = self; 103 sc->sc_bst = ma->ma_iot; 104 if (bus_space_map(sc->sc_bst, ma->ma_addr, GT_REG_REGION, 105 0, &sc->sc_bsh)) { 106 aprint_error(": unable to map GT64111 registers\n"); 107 return; 108 } 109 110 aprint_normal("\n"); 111 112 gt_timer_init(sc); 113 114 bus_space_write_4(sc->sc_bst, sc->sc_bsh, GT_PCI_COMMAND, 115 (bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_PCI_COMMAND) & 116 ~PCI_SYNCMODE) | PCI_PCLK_HIGH); 117 118 (void)bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_PCI_TIMEOUT_RETRY); 119 bus_space_write_4(sc->sc_bst, sc->sc_bsh, GT_PCI_TIMEOUT_RETRY, 120 0x00 << PCI_RETRYCTR_SHIFT | 0xff << PCI_TIMEOUT1_SHIFT | 0xff); 121 122 #if NPCI > 0 123 pc = &sc->sc_pc; 124 pc->pc_bst = sc->sc_bst; 125 pc->pc_bsh = sc->sc_bsh; 126 127 #ifdef PCI_NETBSD_CONFIGURE 128 pc->pc_ioext = extent_create("pciio", 0x10001000, 0x11ffffff, 129 NULL, 0, EX_NOWAIT); 130 pc->pc_memext = extent_create("pcimem", 0x12000000, 0x13ffffff, 131 NULL, 0, EX_NOWAIT); 132 pci_configure_bus(pc, pc->pc_ioext, pc->pc_memext, NULL, 0, 133 mips_cache_info.mci_dcache_align); 134 #endif 135 pba.pba_dmat = &pci_bus_dma_tag; 136 pba.pba_dmat64 = NULL; 137 pba.pba_bus = 0; 138 pba.pba_bridgetag = NULL; 139 pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY | 140 PCI_FLAGS_MRL_OKAY | /*PCI_FLAGS_MRM_OKAY|*/ PCI_FLAGS_MWI_OKAY; 141 pba.pba_pc = pc; 142 config_found_ia(self, "pcibus", &pba, gt_print); 143 #endif 144 } 145 146 static int 147 gt_print(void *aux, const char *pnp) 148 { 149 150 /* XXX */ 151 return 0; 152 } 153 154 static void 155 gt_timer_init(struct gt_softc *sc) 156 { 157 158 /* stop timer0 */ 159 bus_space_write_4(sc->sc_bst, sc->sc_bsh, GT_TIMER_CTRL, 160 bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_TIMER_CTRL) & ~ENTC0); 161 /* mask timer0 interrupt */ 162 bus_space_write_4(sc->sc_bst, sc->sc_bsh, GT_MASTER_MASK, 163 bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_MASTER_MASK) & ~T0EXP); 164 } 165 166 #if 0 /* unused; now NetBSD/cobalt uses CPU INT5 for hardclock(9) */ 167 #define TIMER0_INIT_VALUE 500000 168 169 static void 170 gt_timer0_init(void *cookie) 171 { 172 struct gt_softc *sc = cookie; 173 174 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 175 GT_TIMER_COUNTER0, TIMER0_INIT_VALUE); 176 /* start timer0 */ 177 bus_space_write_4(sc->sc_bst, sc->sc_bsh, GT_TIMER_CTRL, 178 bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_TIMER_CTRL) | ENTC0); 179 /* unmask timer0 interrupt */ 180 bus_space_write_4(sc->sc_bst, sc->sc_bsh, GT_MASTER_MASK, 181 bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_MASTER_MASK) | T0EXP); 182 } 183 184 static long 185 gt_timer0_read(void *cookie) 186 { 187 struct gt_softc *sc = cookie; 188 uint32_t counter0; 189 190 counter0 = bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_TIMER_COUNTER0); 191 counter0 = TIMER0_INIT_VALUE - counter0; 192 #if 0 193 counter /= 50; 194 #else 195 /* 196 * From pmax/pmax/dec_3min.c: 197 * 1/64 + 1/256 + 1/2048 = 41/2048 = 1/49.9512... 198 */ 199 counter0 = (counter0 >> 6) + (counter0 >> 8) + (counter0 >> 11); 200 #endif 201 return counter0; 202 } 203 #endif 204
Indexes created Thu Oct 02 01:09:59 GMT 2025