gt.c revision 1.31
1 /* $NetBSD: gt.c,v 1.31 2020/06/14 01:40:03 chs Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Soren S. Jorvang. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: gt.c,v 1.31 2020/06/14 01:40:03 chs Exp $"); 30 31 #include "opt_pci.h" 32 #include "pci.h" 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/conf.h> 37 #include <sys/device.h> 38 #include <sys/extent.h> 39 #include <sys/file.h> 40 #include <sys/intr.h> 41 #include <sys/ioctl.h> 42 #include <sys/kernel.h> 43 #include <sys/malloc.h> 44 #include <sys/proc.h> 45 #include <sys/select.h> 46 #include <sys/syslog.h> 47 #include <sys/systm.h> 48 #include <sys/tty.h> 49 #include <sys/uio.h> 50 51 #include <machine/autoconf.h> 52 53 #include <mips/cache.h> 54 55 #include <dev/pci/pcivar.h> 56 #ifdef PCI_NETBSD_CONFIGURE 57 #include <dev/pci/pciconf.h> 58 #endif 59 60 #include <cobalt/dev/gtvar.h> 61 #include <cobalt/dev/gtreg.h> 62 63 struct gt_softc { 64 device_t sc_dev; 65 66 bus_space_tag_t sc_bst; 67 bus_space_handle_t sc_bsh; 68 struct cobalt_pci_chipset sc_pc; 69 }; 70 71 static int gt_match(device_t, cfdata_t, void *); 72 static void gt_attach(device_t, device_t, void *); 73 static int gt_print(void *aux, const char *pnp); 74 75 static void gt_timer_init(struct gt_softc *sc); 76 #if 0 /* unused */ 77 static void gt_timer0_init(void *); 78 static long gt_timer0_read(void *); 79 #endif 80 81 struct mips_bus_space gt_iot; 82 struct mips_bus_space gt_memt; 83 84 CFATTACH_DECL_NEW(gt, sizeof(struct gt_softc), 85 gt_match, gt_attach, NULL, NULL); 86 87 static int 88 gt_match(device_t parent, cfdata_t cf, void *aux) 89 { 90 91 return 1; 92 } 93 94 #define GT_REG_REGION 0x1000 95 96 static void 97 gt_attach(device_t parent, device_t self, void *aux) 98 { 99 struct gt_softc *sc = device_private(self); 100 struct mainbus_attach_args *ma = aux; 101 #if NPCI > 0 102 pci_chipset_tag_t pc; 103 struct pcibus_attach_args pba; 104 #endif 105 106 sc->sc_dev = self; 107 sc->sc_bst = ma->ma_iot; 108 if (bus_space_map(sc->sc_bst, ma->ma_addr, GT_REG_REGION, 109 0, &sc->sc_bsh)) { 110 aprint_error(": unable to map GT64111 registers\n"); 111 return; 112 } 113 114 aprint_normal("\n"); 115 116 gt_timer_init(sc); 117 118 bus_space_write_4(sc->sc_bst, sc->sc_bsh, GT_PCI_COMMAND, 119 (bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_PCI_COMMAND) & 120 ~PCI_SYNCMODE) | PCI_PCLK_HIGH); 121 122 (void)bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_PCI_TIMEOUT_RETRY); 123 bus_space_write_4(sc->sc_bst, sc->sc_bsh, GT_PCI_TIMEOUT_RETRY, 124 0x00 << PCI_RETRYCTR_SHIFT | 0xff << PCI_TIMEOUT1_SHIFT | 0xff); 125 126 gt_bus_mem_init(>_memt, NULL); 127 gt_bus_io_init(>_iot, NULL); 128 129 #if NPCI > 0 130 pc = &sc->sc_pc; 131 pc->pc_bst = sc->sc_bst; 132 pc->pc_bsh = sc->sc_bsh; 133 134 #ifdef PCI_NETBSD_CONFIGURE 135 pc->pc_ioext = extent_create("pciio", 0x00001000, 0x01ffffff, 136 NULL, 0, EX_WAITOK); 137 pc->pc_memext = extent_create("pcimem", 0x12000000, 0x13ffffff, 138 NULL, 0, EX_WAITOK); 139 pci_configure_bus(pc, pc->pc_ioext, pc->pc_memext, NULL, 0, 140 mips_cache_info.mci_dcache_align); 141 #endif 142 memset(&pba, 0, sizeof(pba)); 143 pba.pba_memt = >_memt; 144 pba.pba_iot = >_iot; 145 pba.pba_dmat = &pci_bus_dma_tag; 146 pba.pba_dmat64 = NULL; 147 pba.pba_bus = 0; 148 pba.pba_bridgetag = NULL; 149 pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY | 150 PCI_FLAGS_MRL_OKAY | /*PCI_FLAGS_MRM_OKAY|*/ PCI_FLAGS_MWI_OKAY; 151 pba.pba_pc = pc; 152 config_found_ia(self, "pcibus", &pba, gt_print); 153 #endif 154 } 155 156 static int 157 gt_print(void *aux, const char *pnp) 158 { 159 160 /* XXX */ 161 return 0; 162 } 163 164 static void 165 gt_timer_init(struct gt_softc *sc) 166 { 167 168 /* stop timer0 */ 169 bus_space_write_4(sc->sc_bst, sc->sc_bsh, GT_TIMER_CTRL, 170 bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_TIMER_CTRL) & ~ENTC0); 171 /* mask timer0 interrupt */ 172 bus_space_write_4(sc->sc_bst, sc->sc_bsh, GT_MASTER_MASK, 173 bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_MASTER_MASK) & ~T0EXP); 174 } 175 176 #if 0 /* unused; now NetBSD/cobalt uses CPU INT5 for hardclock(9) */ 177 #define TIMER0_INIT_VALUE 500000 178 179 static void 180 gt_timer0_init(void *cookie) 181 { 182 struct gt_softc *sc = cookie; 183 184 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 185 GT_TIMER_COUNTER0, TIMER0_INIT_VALUE); 186 /* start timer0 */ 187 bus_space_write_4(sc->sc_bst, sc->sc_bsh, GT_TIMER_CTRL, 188 bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_TIMER_CTRL) | ENTC0); 189 /* unmask timer0 interrupt */ 190 bus_space_write_4(sc->sc_bst, sc->sc_bsh, GT_MASTER_MASK, 191 bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_MASTER_MASK) | T0EXP); 192 } 193 194 static long 195 gt_timer0_read(void *cookie) 196 { 197 struct gt_softc *sc = cookie; 198 uint32_t counter0; 199 200 counter0 = bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_TIMER_COUNTER0); 201 counter0 = TIMER0_INIT_VALUE - counter0; 202 #if 0 203 counter /= 50; 204 #else 205 /* 206 * From pmax/pmax/dec_3min.c: 207 * 1/64 + 1/256 + 1/2048 = 41/2048 = 1/49.9512... 208 */ 209 counter0 = (counter0 >> 6) + (counter0 >> 8) + (counter0 >> 11); 210 #endif 211 return counter0; 212 } 213 #endif 214
Indexes created Thu Oct 02 01:09:59 GMT 2025