zs.c revision 1.1 1 1.1 tsutsui /* $NetBSD: zs.c,v 1.1 2008/03/27 15:21:46 tsutsui Exp $ */
2 1.1 tsutsui
3 1.1 tsutsui /*-
4 1.1 tsutsui * Copyright (c) 1996 The NetBSD Foundation, Inc.
5 1.1 tsutsui * All rights reserved.
6 1.1 tsutsui *
7 1.1 tsutsui * This code is derived from software contributed to The NetBSD Foundation
8 1.1 tsutsui * by Gordon W. Ross.
9 1.1 tsutsui *
10 1.1 tsutsui * Redistribution and use in source and binary forms, with or without
11 1.1 tsutsui * modification, are permitted provided that the following conditions
12 1.1 tsutsui * are met:
13 1.1 tsutsui * 1. Redistributions of source code must retain the above copyright
14 1.1 tsutsui * notice, this list of conditions and the following disclaimer.
15 1.1 tsutsui * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 tsutsui * notice, this list of conditions and the following disclaimer in the
17 1.1 tsutsui * documentation and/or other materials provided with the distribution.
18 1.1 tsutsui * 3. All advertising materials mentioning features or use of this software
19 1.1 tsutsui * must display the following acknowledgement:
20 1.1 tsutsui * This product includes software developed by the NetBSD
21 1.1 tsutsui * Foundation, Inc. and its contributors.
22 1.1 tsutsui * 4. Neither the name of The NetBSD Foundation nor the names of its
23 1.1 tsutsui * contributors may be used to endorse or promote products derived
24 1.1 tsutsui * from this software without specific prior written permission.
25 1.1 tsutsui *
26 1.1 tsutsui * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 1.1 tsutsui * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 1.1 tsutsui * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 1.1 tsutsui * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 1.1 tsutsui * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 1.1 tsutsui * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 1.1 tsutsui * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 1.1 tsutsui * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 1.1 tsutsui * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 1.1 tsutsui * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 1.1 tsutsui * POSSIBILITY OF SUCH DAMAGE.
37 1.1 tsutsui */
38 1.1 tsutsui
39 1.1 tsutsui /*
40 1.1 tsutsui * Zilog Z8530 Dual UART driver (machine-dependent part)
41 1.1 tsutsui *
42 1.1 tsutsui * Runs two serial lines per chip using slave drivers.
43 1.1 tsutsui * Plain tty/async lines use the zs_async slave.
44 1.1 tsutsui */
45 1.1 tsutsui
46 1.1 tsutsui #include <sys/cdefs.h>
47 1.1 tsutsui __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.1 2008/03/27 15:21:46 tsutsui Exp $");
48 1.1 tsutsui
49 1.1 tsutsui #include "opt_ddb.h"
50 1.1 tsutsui
51 1.1 tsutsui #include <sys/param.h>
52 1.1 tsutsui #include <sys/systm.h>
53 1.1 tsutsui #include <sys/conf.h>
54 1.1 tsutsui #include <sys/device.h>
55 1.1 tsutsui #include <sys/tty.h>
56 1.1 tsutsui #include <sys/intr.h>
57 1.1 tsutsui
58 1.1 tsutsui #include <dev/cons.h>
59 1.1 tsutsui #include <dev/ic/z8530reg.h>
60 1.1 tsutsui
61 1.1 tsutsui #include <machine/autoconf.h>
62 1.1 tsutsui #include <machine/z8530var.h>
63 1.1 tsutsui
64 1.1 tsutsui #include <cobalt/cobalt/console.h>
65 1.1 tsutsui
66 1.1 tsutsui #include "ioconf.h"
67 1.1 tsutsui
68 1.1 tsutsui /*
69 1.1 tsutsui * Some warts needed by z8530tty.c -
70 1.1 tsutsui * The default parity REALLY needs to be the same as the PROM uses,
71 1.1 tsutsui * or you can not see messages done with printf during boot-up...
72 1.1 tsutsui */
73 1.1 tsutsui int zs_def_cflag = (CREAD | CS8 | HUPCL);
74 1.1 tsutsui
75 1.1 tsutsui #define ZS_DEFSPEED 115200
76 1.1 tsutsui #define PCLK (115200 * 96) /* 11.0592MHz */
77 1.1 tsutsui
78 1.1 tsutsui #define ZS_DELAY() delay(2)
79 1.1 tsutsui
80 1.1 tsutsui /* The layout of this is hardware-dependent (padding, order). */
81 1.1 tsutsui /* A/~B (Channel A/Channel B) pin is connected to DAdr0 */
82 1.1 tsutsui #define ZS_CHAN_A 0x01
83 1.1 tsutsui #define ZS_CHAN_B 0x00
84 1.1 tsutsui
85 1.1 tsutsui /* D/~C (Data/Control) pin is connected to DAdr1 */
86 1.1 tsutsui #define ZS_CSR 0x00 /* ctrl, status, and indirect access */
87 1.1 tsutsui #define ZS_DATA 0x02 /* data */
88 1.1 tsutsui
89 1.1 tsutsui
90 1.1 tsutsui /* Definition of the driver for autoconfig. */
91 1.1 tsutsui static int zs_match(struct device *, struct cfdata *, void *);
92 1.1 tsutsui static void zs_attach(struct device *, struct device *, void *);
93 1.1 tsutsui static int zs_print(void *, const char *name);
94 1.1 tsutsui
95 1.1 tsutsui CFATTACH_DECL(zsc, sizeof(struct zsc_softc),
96 1.1 tsutsui zs_match, zs_attach, NULL, NULL);
97 1.1 tsutsui
98 1.1 tsutsui static int zshard(void *);
99 1.1 tsutsui #if 0
100 1.1 tsutsui static int zs_get_speed(struct zs_chanstate *);
101 1.1 tsutsui #endif
102 1.1 tsutsui static int zs_getc(void *);
103 1.1 tsutsui static void zs_putc(void *, int);
104 1.1 tsutsui
105 1.1 tsutsui /* console status from cninit */
106 1.1 tsutsui static struct zs_chanstate zs_conschan_store;
107 1.1 tsutsui static struct zs_chanstate *zs_conschan;
108 1.1 tsutsui static uint8_t *zs_cons;
109 1.1 tsutsui
110 1.1 tsutsui /* default speed for all channels */
111 1.1 tsutsui static int zs_defspeed = ZS_DEFSPEED;
112 1.1 tsutsui
113 1.1 tsutsui static u_char zs_init_reg[16] = {
114 1.1 tsutsui 0, /* 0: CMD (reset, etc.) */
115 1.1 tsutsui 0, /* 1: No interrupts yet. */
116 1.1 tsutsui 0, /* 2: no IVECT */
117 1.1 tsutsui ZSWR3_RX_8 | ZSWR3_RX_ENABLE, /* 3: RX params and ctrl */
118 1.1 tsutsui ZSWR4_CLK_X16 | ZSWR4_ONESB, /* 4: TX/RX misc params */
119 1.1 tsutsui ZSWR5_TX_8 | ZSWR5_TX_ENABLE, /* 5: TX params and ctrl */
120 1.1 tsutsui 0, /* 6: TXSYNC/SYNCLO */
121 1.1 tsutsui 0, /* 7: RXSYNC/SYNCHI */
122 1.1 tsutsui 0, /* 8: alias for data port */
123 1.1 tsutsui ZSWR9_MASTER_IE, /* 9: Master interrupt ctrl */
124 1.1 tsutsui 0, /*10: Misc TX/RX ctrl */
125 1.1 tsutsui ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, /*11: Clock Mode ctrl */
126 1.1 tsutsui BPS_TO_TCONST((PCLK/16), ZS_DEFSPEED), /*12: BAUDLO */
127 1.1 tsutsui 0, /*13: BAUDHI */
128 1.1 tsutsui ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, /*14: Misc ctrl */
129 1.1 tsutsui ZSWR15_BREAK_IE, /*15: Ext/Status intr ctrl */
130 1.1 tsutsui };
131 1.1 tsutsui
132 1.1 tsutsui /* register address offset for each channel */
133 1.1 tsutsui static const int chanoff[] = { ZS_CHAN_A, ZS_CHAN_B };
134 1.1 tsutsui
135 1.1 tsutsui
136 1.1 tsutsui static int
137 1.1 tsutsui zs_match(struct device *parent, struct cfdata *cf, void *aux)
138 1.1 tsutsui {
139 1.1 tsutsui static int matched;
140 1.1 tsutsui
141 1.1 tsutsui /* only one zs */
142 1.1 tsutsui if (matched)
143 1.1 tsutsui return 0;
144 1.1 tsutsui
145 1.1 tsutsui /* only Qube 2700 could have Z85C30 serial */
146 1.1 tsutsui if (cobalt_id != COBALT_ID_QUBE2700)
147 1.1 tsutsui return 0;
148 1.1 tsutsui
149 1.1 tsutsui if (!console_present)
150 1.1 tsutsui return 0;
151 1.1 tsutsui
152 1.1 tsutsui matched = 1;
153 1.1 tsutsui return 1;
154 1.1 tsutsui }
155 1.1 tsutsui
156 1.1 tsutsui /*
157 1.1 tsutsui * Attach a found zs.
158 1.1 tsutsui */
159 1.1 tsutsui static void
160 1.1 tsutsui zs_attach(struct device *parent, struct device *self, void *aux)
161 1.1 tsutsui {
162 1.1 tsutsui struct zsc_softc *zsc = device_private(self);
163 1.1 tsutsui struct mainbus_attach_args *maa = aux;
164 1.1 tsutsui struct zsc_attach_args zsc_args;
165 1.1 tsutsui uint8_t *zs_base;
166 1.1 tsutsui struct zs_chanstate *cs;
167 1.1 tsutsui int s, channel;
168 1.1 tsutsui
169 1.1 tsutsui /* XXX: MI z8530 doesn't use bus_space(9) yet */
170 1.1 tsutsui zs_base = (void *)MIPS_PHYS_TO_KSEG1(maa->ma_addr);
171 1.1 tsutsui
172 1.1 tsutsui aprint_normal(": optional Z85C30 serial port\n");
173 1.1 tsutsui
174 1.1 tsutsui /*
175 1.1 tsutsui * Initialize software state for each channel.
176 1.1 tsutsui */
177 1.1 tsutsui for (channel = 0; channel < 2; channel++) {
178 1.1 tsutsui zsc_args.channel = channel;
179 1.1 tsutsui cs = &zsc->zsc_cs_store[channel];
180 1.1 tsutsui
181 1.1 tsutsui zsc->zsc_cs[channel] = cs;
182 1.1 tsutsui
183 1.1 tsutsui zs_init_reg[2] = 0;
184 1.1 tsutsui
185 1.1 tsutsui if ((zs_base + chanoff[channel]) == zs_cons) {
186 1.1 tsutsui memcpy(cs, zs_conschan, sizeof(struct zs_chanstate));
187 1.1 tsutsui zs_conschan = cs;
188 1.1 tsutsui zsc_args.hwflags = ZS_HWFLAG_CONSOLE;
189 1.1 tsutsui } else {
190 1.1 tsutsui cs->cs_reg_csr = zs_base + chanoff[channel] + ZS_CSR;
191 1.1 tsutsui cs->cs_reg_data = zs_base + chanoff[channel] + ZS_DATA;
192 1.1 tsutsui memcpy(cs->cs_creg, zs_init_reg, 16);
193 1.1 tsutsui memcpy(cs->cs_preg, zs_init_reg, 16);
194 1.1 tsutsui cs->cs_defspeed = zs_defspeed;
195 1.1 tsutsui zsc_args.hwflags = 0;
196 1.1 tsutsui }
197 1.1 tsutsui
198 1.1 tsutsui zs_lock_init(cs);
199 1.1 tsutsui cs->cs_defcflag = zs_def_cflag;
200 1.1 tsutsui
201 1.1 tsutsui cs->cs_channel = channel;
202 1.1 tsutsui cs->cs_private = NULL;
203 1.1 tsutsui cs->cs_ops = &zsops_null;
204 1.1 tsutsui cs->cs_brg_clk = PCLK / 16;
205 1.1 tsutsui
206 1.1 tsutsui /* Make these correspond to cs_defcflag (-crtscts) */
207 1.1 tsutsui cs->cs_rr0_dcd = ZSRR0_DCD;
208 1.1 tsutsui cs->cs_rr0_cts = 0;
209 1.1 tsutsui cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
210 1.1 tsutsui cs->cs_wr5_rts = 0;
211 1.1 tsutsui
212 1.1 tsutsui /*
213 1.1 tsutsui * Clear the master interrupt enable.
214 1.1 tsutsui * The INTENA is common to both channels,
215 1.1 tsutsui * so just do it on the A channel.
216 1.1 tsutsui */
217 1.1 tsutsui if (channel == 0) {
218 1.1 tsutsui s = splhigh();
219 1.1 tsutsui zs_write_reg(cs, 9, 0);
220 1.1 tsutsui splx(s);
221 1.1 tsutsui }
222 1.1 tsutsui
223 1.1 tsutsui /*
224 1.1 tsutsui * Look for a child driver for this channel.
225 1.1 tsutsui * The child attach will setup the hardware.
226 1.1 tsutsui */
227 1.1 tsutsui if (!config_found(self, (void *)&zsc_args, zs_print)) {
228 1.1 tsutsui /* No sub-driver. Just reset it. */
229 1.1 tsutsui uint8_t reset = (channel == 0) ?
230 1.1 tsutsui ZSWR9_A_RESET : ZSWR9_B_RESET;
231 1.1 tsutsui s = splhigh();
232 1.1 tsutsui zs_write_reg(cs, 9, reset);
233 1.1 tsutsui splx(s);
234 1.1 tsutsui }
235 1.1 tsutsui }
236 1.1 tsutsui
237 1.1 tsutsui /*
238 1.1 tsutsui * Now safe to install interrupt handlers.
239 1.1 tsutsui */
240 1.1 tsutsui icu_intr_establish(maa->ma_irq, IST_EDGE, IPL_SERIAL, zshard, zsc);
241 1.1 tsutsui zsc->zsc_softintr_cookie = softint_establish(SOFTINT_SERIAL,
242 1.1 tsutsui (void (*)(void *))zsc_intr_soft, zsc);
243 1.1 tsutsui
244 1.1 tsutsui /*
245 1.1 tsutsui * Set the master interrupt enable and interrupt vector.
246 1.1 tsutsui * (common to both channels, do it on A)
247 1.1 tsutsui */
248 1.1 tsutsui cs = zsc->zsc_cs[0];
249 1.1 tsutsui s = splhigh();
250 1.1 tsutsui /* interrupt vector */
251 1.1 tsutsui zs_write_reg(cs, 2, 0);
252 1.1 tsutsui /* master interrupt control (enable) */
253 1.1 tsutsui zs_write_reg(cs, 9, zs_init_reg[9]);
254 1.1 tsutsui splx(s);
255 1.1 tsutsui }
256 1.1 tsutsui
257 1.1 tsutsui static int
258 1.1 tsutsui zs_print(void *aux, const char *name)
259 1.1 tsutsui {
260 1.1 tsutsui struct zsc_attach_args *args = aux;
261 1.1 tsutsui
262 1.1 tsutsui if (name != NULL)
263 1.1 tsutsui aprint_normal("%s: ", name);
264 1.1 tsutsui
265 1.1 tsutsui if (args->channel != -1)
266 1.1 tsutsui aprint_normal(" channel %d", args->channel);
267 1.1 tsutsui
268 1.1 tsutsui return UNCONF;
269 1.1 tsutsui }
270 1.1 tsutsui
271 1.1 tsutsui static int
272 1.1 tsutsui zshard(void *arg)
273 1.1 tsutsui {
274 1.1 tsutsui struct zsc_softc *zsc = arg;
275 1.1 tsutsui int rval;
276 1.1 tsutsui
277 1.1 tsutsui rval = zsc_intr_hard(zsc);
278 1.1 tsutsui
279 1.1 tsutsui #if 1
280 1.1 tsutsui /* XXX: there is some race condition? */
281 1.1 tsutsui if (rval)
282 1.1 tsutsui while (zsc_intr_hard(zsc))
283 1.1 tsutsui ;
284 1.1 tsutsui #endif
285 1.1 tsutsui
286 1.1 tsutsui /* We are at splzs here, so no need to lock. */
287 1.1 tsutsui if (zsc->zsc_cs[0]->cs_softreq || zsc->zsc_cs[1]->cs_softreq)
288 1.1 tsutsui softint_schedule(zsc->zsc_softintr_cookie);
289 1.1 tsutsui
290 1.1 tsutsui return rval;
291 1.1 tsutsui }
292 1.1 tsutsui
293 1.1 tsutsui /*
294 1.1 tsutsui * Compute the current baud rate given a ZS channel.
295 1.1 tsutsui */
296 1.1 tsutsui #if 0
297 1.1 tsutsui static int
298 1.1 tsutsui zs_get_speed(struct zs_chanstate *cs)
299 1.1 tsutsui {
300 1.1 tsutsui int tconst;
301 1.1 tsutsui
302 1.1 tsutsui tconst = zs_read_reg(cs, 12);
303 1.1 tsutsui tconst |= zs_read_reg(cs, 13) << 8;
304 1.1 tsutsui return TCONST_TO_BPS(cs->cs_brg_clk, tconst);
305 1.1 tsutsui }
306 1.1 tsutsui #endif
307 1.1 tsutsui
308 1.1 tsutsui /*
309 1.1 tsutsui * MD functions for setting the baud rate and control modes.
310 1.1 tsutsui */
311 1.1 tsutsui int
312 1.1 tsutsui zs_set_speed(struct zs_chanstate *cs, int bps)
313 1.1 tsutsui {
314 1.1 tsutsui int tconst, real_bps;
315 1.1 tsutsui
316 1.1 tsutsui if (bps == 0)
317 1.1 tsutsui return 0;
318 1.1 tsutsui
319 1.1 tsutsui #ifdef DIAGNOSTIC
320 1.1 tsutsui if (cs->cs_brg_clk == 0)
321 1.1 tsutsui panic("zs_set_speed");
322 1.1 tsutsui #endif
323 1.1 tsutsui
324 1.1 tsutsui tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps);
325 1.1 tsutsui if (tconst < 0)
326 1.1 tsutsui return EINVAL;
327 1.1 tsutsui
328 1.1 tsutsui /* Convert back to make sure we can do it. */
329 1.1 tsutsui real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst);
330 1.1 tsutsui
331 1.1 tsutsui /* Allow ~4% tolerance here */
332 1.1 tsutsui if (abs(real_bps - bps) >= bps * 4 / 100)
333 1.1 tsutsui return EINVAL;
334 1.1 tsutsui
335 1.1 tsutsui cs->cs_preg[12] = tconst;
336 1.1 tsutsui cs->cs_preg[13] = tconst >> 8;
337 1.1 tsutsui
338 1.1 tsutsui /* Caller will stuff the pending registers. */
339 1.1 tsutsui return 0;
340 1.1 tsutsui }
341 1.1 tsutsui
342 1.1 tsutsui int
343 1.1 tsutsui zs_set_modes(struct zs_chanstate *cs, int cflag)
344 1.1 tsutsui {
345 1.1 tsutsui int s;
346 1.1 tsutsui
347 1.1 tsutsui /*
348 1.1 tsutsui * Output hardware flow control on the chip is horrendous:
349 1.1 tsutsui * if carrier detect drops, the receiver is disabled, and if
350 1.1 tsutsui * CTS drops, the transmitter is stoped IN MID CHARACTER!
351 1.1 tsutsui * Therefore, NEVER set the HFC bit, and instead use the
352 1.1 tsutsui * status interrupt to detect CTS changes.
353 1.1 tsutsui */
354 1.1 tsutsui s = splzs();
355 1.1 tsutsui cs->cs_rr0_pps = 0;
356 1.1 tsutsui if ((cflag & (CLOCAL | MDMBUF)) != 0) {
357 1.1 tsutsui cs->cs_rr0_dcd = 0;
358 1.1 tsutsui if ((cflag & MDMBUF) == 0)
359 1.1 tsutsui cs->cs_rr0_pps = ZSRR0_DCD;
360 1.1 tsutsui } else
361 1.1 tsutsui cs->cs_rr0_dcd = ZSRR0_DCD;
362 1.1 tsutsui if ((cflag & CRTSCTS) != 0) {
363 1.1 tsutsui cs->cs_wr5_dtr = ZSWR5_DTR;
364 1.1 tsutsui cs->cs_wr5_rts = ZSWR5_RTS;
365 1.1 tsutsui cs->cs_rr0_cts = ZSRR0_CTS;
366 1.1 tsutsui } else if ((cflag & MDMBUF) != 0) {
367 1.1 tsutsui cs->cs_wr5_dtr = 0;
368 1.1 tsutsui cs->cs_wr5_rts = ZSWR5_DTR;
369 1.1 tsutsui cs->cs_rr0_cts = ZSRR0_DCD;
370 1.1 tsutsui } else {
371 1.1 tsutsui cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
372 1.1 tsutsui cs->cs_wr5_rts = 0;
373 1.1 tsutsui cs->cs_rr0_cts = 0;
374 1.1 tsutsui }
375 1.1 tsutsui splx(s);
376 1.1 tsutsui
377 1.1 tsutsui /* Caller will stuff the pending registers. */
378 1.1 tsutsui return 0;
379 1.1 tsutsui }
380 1.1 tsutsui
381 1.1 tsutsui
382 1.1 tsutsui /*
383 1.1 tsutsui * Read or write the chip with suitable delays.
384 1.1 tsutsui */
385 1.1 tsutsui
386 1.1 tsutsui u_char
387 1.1 tsutsui zs_read_reg(struct zs_chanstate *cs, uint8_t reg)
388 1.1 tsutsui {
389 1.1 tsutsui uint8_t val;
390 1.1 tsutsui
391 1.1 tsutsui *cs->cs_reg_csr = reg;
392 1.1 tsutsui ZS_DELAY();
393 1.1 tsutsui val = *cs->cs_reg_csr;
394 1.1 tsutsui ZS_DELAY();
395 1.1 tsutsui return val;
396 1.1 tsutsui }
397 1.1 tsutsui
398 1.1 tsutsui void
399 1.1 tsutsui zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val)
400 1.1 tsutsui {
401 1.1 tsutsui
402 1.1 tsutsui *cs->cs_reg_csr = reg;
403 1.1 tsutsui ZS_DELAY();
404 1.1 tsutsui *cs->cs_reg_csr = val;
405 1.1 tsutsui ZS_DELAY();
406 1.1 tsutsui }
407 1.1 tsutsui
408 1.1 tsutsui u_char
409 1.1 tsutsui zs_read_csr(struct zs_chanstate *cs)
410 1.1 tsutsui {
411 1.1 tsutsui uint8_t val;
412 1.1 tsutsui
413 1.1 tsutsui val = *cs->cs_reg_csr;
414 1.1 tsutsui ZS_DELAY();
415 1.1 tsutsui return val;
416 1.1 tsutsui }
417 1.1 tsutsui
418 1.1 tsutsui void
419 1.1 tsutsui zs_write_csr(struct zs_chanstate *cs, uint8_t val)
420 1.1 tsutsui {
421 1.1 tsutsui
422 1.1 tsutsui *cs->cs_reg_csr = val;
423 1.1 tsutsui ZS_DELAY();
424 1.1 tsutsui }
425 1.1 tsutsui
426 1.1 tsutsui uint8_t
427 1.1 tsutsui zs_read_data(struct zs_chanstate *cs)
428 1.1 tsutsui {
429 1.1 tsutsui uint8_t val;
430 1.1 tsutsui
431 1.1 tsutsui val = *cs->cs_reg_data;
432 1.1 tsutsui ZS_DELAY();
433 1.1 tsutsui return val;
434 1.1 tsutsui }
435 1.1 tsutsui
436 1.1 tsutsui void
437 1.1 tsutsui zs_write_data(struct zs_chanstate *cs, uint8_t val)
438 1.1 tsutsui {
439 1.1 tsutsui
440 1.1 tsutsui *cs->cs_reg_data = val;
441 1.1 tsutsui ZS_DELAY();
442 1.1 tsutsui }
443 1.1 tsutsui
444 1.1 tsutsui void
445 1.1 tsutsui zs_abort(struct zs_chanstate *cs)
446 1.1 tsutsui {
447 1.1 tsutsui
448 1.1 tsutsui #ifdef DDB
449 1.1 tsutsui Debugger();
450 1.1 tsutsui #endif
451 1.1 tsutsui }
452 1.1 tsutsui
453 1.1 tsutsui /*
454 1.1 tsutsui * Polled input char.
455 1.1 tsutsui */
456 1.1 tsutsui int
457 1.1 tsutsui zs_getc(void *arg)
458 1.1 tsutsui {
459 1.1 tsutsui struct zs_chanstate *cs = arg;
460 1.1 tsutsui int s, c;
461 1.1 tsutsui uint8_t rr0;
462 1.1 tsutsui
463 1.1 tsutsui s = splhigh();
464 1.1 tsutsui /* Wait for a character to arrive. */
465 1.1 tsutsui do {
466 1.1 tsutsui rr0 = *cs->cs_reg_csr;
467 1.1 tsutsui ZS_DELAY();
468 1.1 tsutsui } while ((rr0 & ZSRR0_RX_READY) == 0);
469 1.1 tsutsui
470 1.1 tsutsui c = *cs->cs_reg_data;
471 1.1 tsutsui ZS_DELAY();
472 1.1 tsutsui splx(s);
473 1.1 tsutsui
474 1.1 tsutsui return c;
475 1.1 tsutsui }
476 1.1 tsutsui
477 1.1 tsutsui /*
478 1.1 tsutsui * Polled output char.
479 1.1 tsutsui */
480 1.1 tsutsui void
481 1.1 tsutsui zs_putc(void *arg, int c)
482 1.1 tsutsui {
483 1.1 tsutsui struct zs_chanstate *cs = arg;
484 1.1 tsutsui int s;
485 1.1 tsutsui uint8_t rr0;
486 1.1 tsutsui
487 1.1 tsutsui s = splhigh();
488 1.1 tsutsui /* Wait for transmitter to become ready. */
489 1.1 tsutsui do {
490 1.1 tsutsui rr0 = *cs->cs_reg_csr;
491 1.1 tsutsui ZS_DELAY();
492 1.1 tsutsui } while ((rr0 & ZSRR0_TX_READY) == 0);
493 1.1 tsutsui
494 1.1 tsutsui *cs->cs_reg_data = c;
495 1.1 tsutsui ZS_DELAY();
496 1.1 tsutsui splx(s);
497 1.1 tsutsui }
498 1.1 tsutsui
499 1.1 tsutsui void
500 1.1 tsutsui zscnprobe(struct consdev *cn)
501 1.1 tsutsui {
502 1.1 tsutsui
503 1.1 tsutsui cn->cn_pri = (console_present != 0 && cobalt_id == COBALT_ID_QUBE2700)
504 1.1 tsutsui ? CN_NORMAL : CN_DEAD;
505 1.1 tsutsui }
506 1.1 tsutsui
507 1.1 tsutsui void
508 1.1 tsutsui zscninit(struct consdev *cn)
509 1.1 tsutsui {
510 1.1 tsutsui struct zs_chanstate *cs;
511 1.1 tsutsui
512 1.1 tsutsui extern const struct cdevsw zstty_cdevsw;
513 1.1 tsutsui
514 1.1 tsutsui cn->cn_dev = makedev(cdevsw_lookup_major(&zstty_cdevsw), 0);
515 1.1 tsutsui
516 1.1 tsutsui zs_cons = (uint8_t *)MIPS_PHYS_TO_KSEG1(ZS_BASE) + ZS_CHAN_A; /* XXX */
517 1.1 tsutsui
518 1.1 tsutsui zs_conschan = cs = &zs_conschan_store;
519 1.1 tsutsui
520 1.1 tsutsui /* Setup temporary chanstate. */
521 1.1 tsutsui cs->cs_reg_csr = zs_cons + ZS_CSR;
522 1.1 tsutsui cs->cs_reg_data = zs_cons + ZS_DATA;
523 1.1 tsutsui
524 1.1 tsutsui /* Initialize the pending registers. */
525 1.1 tsutsui memcpy(cs->cs_preg, zs_init_reg, 16);
526 1.1 tsutsui cs->cs_preg[5] |= ZSWR5_DTR | ZSWR5_RTS;
527 1.1 tsutsui
528 1.1 tsutsui cs->cs_preg[12] = BPS_TO_TCONST(PCLK / 16, ZS_DEFSPEED);
529 1.1 tsutsui cs->cs_preg[13] = 0;
530 1.1 tsutsui cs->cs_defspeed = ZS_DEFSPEED;
531 1.1 tsutsui
532 1.1 tsutsui /* Clear the master interrupt enable. */
533 1.1 tsutsui zs_write_reg(cs, 9, 0);
534 1.1 tsutsui
535 1.1 tsutsui /* Reset the whole SCC chip. */
536 1.1 tsutsui zs_write_reg(cs, 9, ZSWR9_HARD_RESET);
537 1.1 tsutsui
538 1.1 tsutsui /* Copy "pending" to "current" and H/W */
539 1.1 tsutsui zs_loadchannelregs(cs);
540 1.1 tsutsui }
541 1.1 tsutsui
542 1.1 tsutsui int
543 1.1 tsutsui zscngetc(dev_t dev)
544 1.1 tsutsui {
545 1.1 tsutsui
546 1.1 tsutsui return zs_getc((void *)zs_conschan);
547 1.1 tsutsui }
548 1.1 tsutsui
549 1.1 tsutsui void
550 1.1 tsutsui zscnputc(dev_t dev, int c)
551 1.1 tsutsui {
552 1.1 tsutsui
553 1.1 tsutsui zs_putc((void *)zs_conschan, c);
554 1.1 tsutsui }
555