zs.c revision 1.2.2.3
1 1.2.2.2 mjf /* $NetBSD: zs.c,v 1.2.2.3 2008/06/02 13:21:59 mjf Exp $ */ 2 1.2.2.2 mjf 3 1.2.2.2 mjf /*- 4 1.2.2.2 mjf * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 1.2.2.2 mjf * All rights reserved. 6 1.2.2.2 mjf * 7 1.2.2.2 mjf * This code is derived from software contributed to The NetBSD Foundation 8 1.2.2.2 mjf * by Gordon W. Ross. 9 1.2.2.2 mjf * 10 1.2.2.2 mjf * Redistribution and use in source and binary forms, with or without 11 1.2.2.2 mjf * modification, are permitted provided that the following conditions 12 1.2.2.2 mjf * are met: 13 1.2.2.2 mjf * 1. Redistributions of source code must retain the above copyright 14 1.2.2.2 mjf * notice, this list of conditions and the following disclaimer. 15 1.2.2.2 mjf * 2. Redistributions in binary form must reproduce the above copyright 16 1.2.2.2 mjf * notice, this list of conditions and the following disclaimer in the 17 1.2.2.2 mjf * documentation and/or other materials provided with the distribution. 18 1.2.2.2 mjf * 19 1.2.2.2 mjf * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 1.2.2.2 mjf * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 1.2.2.2 mjf * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 1.2.2.2 mjf * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 1.2.2.2 mjf * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 1.2.2.2 mjf * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 1.2.2.2 mjf * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 1.2.2.2 mjf * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 1.2.2.2 mjf * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 1.2.2.2 mjf * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 1.2.2.2 mjf * POSSIBILITY OF SUCH DAMAGE. 30 1.2.2.2 mjf */ 31 1.2.2.2 mjf 32 1.2.2.2 mjf /* 33 1.2.2.2 mjf * Zilog Z8530 Dual UART driver (machine-dependent part) 34 1.2.2.2 mjf * 35 1.2.2.2 mjf * Runs two serial lines per chip using slave drivers. 36 1.2.2.2 mjf * Plain tty/async lines use the zs_async slave. 37 1.2.2.2 mjf */ 38 1.2.2.2 mjf 39 1.2.2.2 mjf #include <sys/cdefs.h> 40 1.2.2.2 mjf __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.2.2.3 2008/06/02 13:21:59 mjf Exp $"); 41 1.2.2.2 mjf 42 1.2.2.2 mjf #include "opt_ddb.h" 43 1.2.2.2 mjf 44 1.2.2.2 mjf #include <sys/param.h> 45 1.2.2.2 mjf #include <sys/systm.h> 46 1.2.2.2 mjf #include <sys/conf.h> 47 1.2.2.2 mjf #include <sys/device.h> 48 1.2.2.2 mjf #include <sys/tty.h> 49 1.2.2.2 mjf #include <sys/intr.h> 50 1.2.2.2 mjf 51 1.2.2.2 mjf #include <dev/cons.h> 52 1.2.2.2 mjf #include <dev/ic/z8530reg.h> 53 1.2.2.2 mjf 54 1.2.2.2 mjf #include <machine/autoconf.h> 55 1.2.2.2 mjf #include <machine/z8530var.h> 56 1.2.2.2 mjf 57 1.2.2.2 mjf #include <cobalt/cobalt/console.h> 58 1.2.2.2 mjf 59 1.2.2.2 mjf #include "ioconf.h" 60 1.2.2.2 mjf 61 1.2.2.2 mjf /* 62 1.2.2.2 mjf * Some warts needed by z8530tty.c - 63 1.2.2.2 mjf * The default parity REALLY needs to be the same as the PROM uses, 64 1.2.2.2 mjf * or you can not see messages done with printf during boot-up... 65 1.2.2.2 mjf */ 66 1.2.2.2 mjf int zs_def_cflag = (CREAD | CS8 | HUPCL); 67 1.2.2.2 mjf 68 1.2.2.2 mjf #define ZS_DEFSPEED 115200 69 1.2.2.2 mjf #define PCLK (115200 * 96) /* 11.0592MHz */ 70 1.2.2.2 mjf 71 1.2.2.2 mjf #define ZS_DELAY() delay(2) 72 1.2.2.2 mjf 73 1.2.2.2 mjf /* The layout of this is hardware-dependent (padding, order). */ 74 1.2.2.2 mjf /* A/~B (Channel A/Channel B) pin is connected to DAdr0 */ 75 1.2.2.2 mjf #define ZS_CHAN_A 0x01 76 1.2.2.2 mjf #define ZS_CHAN_B 0x00 77 1.2.2.2 mjf 78 1.2.2.2 mjf /* D/~C (Data/Control) pin is connected to DAdr1 */ 79 1.2.2.2 mjf #define ZS_CSR 0x00 /* ctrl, status, and indirect access */ 80 1.2.2.2 mjf #define ZS_DATA 0x02 /* data */ 81 1.2.2.2 mjf 82 1.2.2.2 mjf 83 1.2.2.2 mjf /* Definition of the driver for autoconfig. */ 84 1.2.2.2 mjf static int zs_match(device_t, cfdata_t, void *); 85 1.2.2.2 mjf static void zs_attach(device_t, device_t, void *); 86 1.2.2.2 mjf static int zs_print(void *, const char *name); 87 1.2.2.2 mjf 88 1.2.2.2 mjf CFATTACH_DECL_NEW(zsc, sizeof(struct zsc_softc), 89 1.2.2.2 mjf zs_match, zs_attach, NULL, NULL); 90 1.2.2.2 mjf 91 1.2.2.2 mjf static int zshard(void *); 92 1.2.2.2 mjf #if 0 93 1.2.2.2 mjf static int zs_get_speed(struct zs_chanstate *); 94 1.2.2.2 mjf #endif 95 1.2.2.2 mjf static int zs_getc(void *); 96 1.2.2.2 mjf static void zs_putc(void *, int); 97 1.2.2.2 mjf 98 1.2.2.2 mjf /* console status from cninit */ 99 1.2.2.2 mjf static struct zs_chanstate zs_conschan_store; 100 1.2.2.2 mjf static struct zs_chanstate *zs_conschan; 101 1.2.2.2 mjf static uint8_t *zs_cons; 102 1.2.2.2 mjf 103 1.2.2.2 mjf /* default speed for all channels */ 104 1.2.2.2 mjf static int zs_defspeed = ZS_DEFSPEED; 105 1.2.2.2 mjf 106 1.2.2.2 mjf static uint8_t zs_init_reg[16] = { 107 1.2.2.2 mjf 0, /* 0: CMD (reset, etc.) */ 108 1.2.2.2 mjf 0, /* 1: No interrupts yet. */ 109 1.2.2.2 mjf 0, /* 2: no IVECT */ 110 1.2.2.2 mjf ZSWR3_RX_8 | ZSWR3_RX_ENABLE, /* 3: RX params and ctrl */ 111 1.2.2.2 mjf ZSWR4_CLK_X16 | ZSWR4_ONESB, /* 4: TX/RX misc params */ 112 1.2.2.2 mjf ZSWR5_TX_8 | ZSWR5_TX_ENABLE, /* 5: TX params and ctrl */ 113 1.2.2.2 mjf 0, /* 6: TXSYNC/SYNCLO */ 114 1.2.2.2 mjf 0, /* 7: RXSYNC/SYNCHI */ 115 1.2.2.2 mjf 0, /* 8: alias for data port */ 116 1.2.2.2 mjf ZSWR9_MASTER_IE, /* 9: Master interrupt ctrl */ 117 1.2.2.2 mjf 0, /*10: Misc TX/RX ctrl */ 118 1.2.2.2 mjf ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, /*11: Clock Mode ctrl */ 119 1.2.2.2 mjf BPS_TO_TCONST((PCLK/16), ZS_DEFSPEED), /*12: BAUDLO */ 120 1.2.2.2 mjf 0, /*13: BAUDHI */ 121 1.2.2.2 mjf ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, /*14: Misc ctrl */ 122 1.2.2.2 mjf ZSWR15_BREAK_IE, /*15: Ext/Status intr ctrl */ 123 1.2.2.2 mjf }; 124 1.2.2.2 mjf 125 1.2.2.2 mjf /* register address offset for each channel */ 126 1.2.2.2 mjf static const int chanoff[] = { ZS_CHAN_A, ZS_CHAN_B }; 127 1.2.2.2 mjf 128 1.2.2.2 mjf 129 1.2.2.2 mjf static int 130 1.2.2.2 mjf zs_match(device_t parent, cfdata_t cf, void *aux) 131 1.2.2.2 mjf { 132 1.2.2.2 mjf static int matched; 133 1.2.2.2 mjf 134 1.2.2.2 mjf /* only one zs */ 135 1.2.2.2 mjf if (matched) 136 1.2.2.2 mjf return 0; 137 1.2.2.2 mjf 138 1.2.2.2 mjf /* only Qube 2700 could have Z85C30 serial */ 139 1.2.2.2 mjf if (cobalt_id != COBALT_ID_QUBE2700) 140 1.2.2.2 mjf return 0; 141 1.2.2.2 mjf 142 1.2.2.2 mjf if (!console_present) 143 1.2.2.2 mjf return 0; 144 1.2.2.2 mjf 145 1.2.2.2 mjf matched = 1; 146 1.2.2.2 mjf return 1; 147 1.2.2.2 mjf } 148 1.2.2.2 mjf 149 1.2.2.2 mjf /* 150 1.2.2.2 mjf * Attach a found zs. 151 1.2.2.2 mjf */ 152 1.2.2.2 mjf static void 153 1.2.2.2 mjf zs_attach(device_t parent, device_t self, void *aux) 154 1.2.2.2 mjf { 155 1.2.2.2 mjf struct zsc_softc *zsc = device_private(self); 156 1.2.2.2 mjf struct mainbus_attach_args *maa = aux; 157 1.2.2.2 mjf struct zsc_attach_args zsc_args; 158 1.2.2.2 mjf uint8_t *zs_base; 159 1.2.2.2 mjf struct zs_chanstate *cs; 160 1.2.2.2 mjf int s, channel; 161 1.2.2.2 mjf 162 1.2.2.2 mjf zsc->zsc_dev = self; 163 1.2.2.2 mjf 164 1.2.2.2 mjf /* XXX: MI z8530 doesn't use bus_space(9) yet */ 165 1.2.2.2 mjf zs_base = (void *)MIPS_PHYS_TO_KSEG1(maa->ma_addr); 166 1.2.2.2 mjf 167 1.2.2.2 mjf aprint_normal(": optional Z85C30 serial port\n"); 168 1.2.2.2 mjf 169 1.2.2.2 mjf /* 170 1.2.2.2 mjf * Initialize software state for each channel. 171 1.2.2.2 mjf */ 172 1.2.2.2 mjf for (channel = 0; channel < 2; channel++) { 173 1.2.2.2 mjf zsc_args.channel = channel; 174 1.2.2.2 mjf cs = &zsc->zsc_cs_store[channel]; 175 1.2.2.2 mjf 176 1.2.2.2 mjf zsc->zsc_cs[channel] = cs; 177 1.2.2.2 mjf 178 1.2.2.2 mjf zs_init_reg[2] = 0; 179 1.2.2.2 mjf 180 1.2.2.2 mjf if ((zs_base + chanoff[channel]) == zs_cons) { 181 1.2.2.2 mjf memcpy(cs, zs_conschan, sizeof(struct zs_chanstate)); 182 1.2.2.2 mjf zs_conschan = cs; 183 1.2.2.2 mjf zsc_args.hwflags = ZS_HWFLAG_CONSOLE; 184 1.2.2.2 mjf } else { 185 1.2.2.2 mjf cs->cs_reg_csr = zs_base + chanoff[channel] + ZS_CSR; 186 1.2.2.2 mjf cs->cs_reg_data = zs_base + chanoff[channel] + ZS_DATA; 187 1.2.2.2 mjf memcpy(cs->cs_creg, zs_init_reg, 16); 188 1.2.2.2 mjf memcpy(cs->cs_preg, zs_init_reg, 16); 189 1.2.2.2 mjf cs->cs_defspeed = zs_defspeed; 190 1.2.2.2 mjf zsc_args.hwflags = 0; 191 1.2.2.2 mjf } 192 1.2.2.2 mjf 193 1.2.2.2 mjf zs_lock_init(cs); 194 1.2.2.2 mjf cs->cs_defcflag = zs_def_cflag; 195 1.2.2.2 mjf 196 1.2.2.2 mjf cs->cs_channel = channel; 197 1.2.2.2 mjf cs->cs_private = NULL; 198 1.2.2.2 mjf cs->cs_ops = &zsops_null; 199 1.2.2.2 mjf cs->cs_brg_clk = PCLK / 16; 200 1.2.2.2 mjf 201 1.2.2.2 mjf /* Make these correspond to cs_defcflag (-crtscts) */ 202 1.2.2.2 mjf cs->cs_rr0_dcd = ZSRR0_DCD; 203 1.2.2.2 mjf cs->cs_rr0_cts = 0; 204 1.2.2.2 mjf cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 205 1.2.2.2 mjf cs->cs_wr5_rts = 0; 206 1.2.2.2 mjf 207 1.2.2.2 mjf /* 208 1.2.2.2 mjf * Clear the master interrupt enable. 209 1.2.2.2 mjf * The INTENA is common to both channels, 210 1.2.2.2 mjf * so just do it on the A channel. 211 1.2.2.2 mjf */ 212 1.2.2.2 mjf if (channel == 0) { 213 1.2.2.2 mjf s = splhigh(); 214 1.2.2.2 mjf zs_write_reg(cs, 9, 0); 215 1.2.2.2 mjf splx(s); 216 1.2.2.2 mjf } 217 1.2.2.2 mjf 218 1.2.2.2 mjf /* 219 1.2.2.2 mjf * Look for a child driver for this channel. 220 1.2.2.2 mjf * The child attach will setup the hardware. 221 1.2.2.2 mjf */ 222 1.2.2.2 mjf if (!config_found(self, (void *)&zsc_args, zs_print)) { 223 1.2.2.2 mjf /* No sub-driver. Just reset it. */ 224 1.2.2.2 mjf uint8_t reset = (channel == 0) ? 225 1.2.2.2 mjf ZSWR9_A_RESET : ZSWR9_B_RESET; 226 1.2.2.2 mjf s = splhigh(); 227 1.2.2.2 mjf zs_write_reg(cs, 9, reset); 228 1.2.2.2 mjf splx(s); 229 1.2.2.2 mjf } 230 1.2.2.2 mjf } 231 1.2.2.2 mjf 232 1.2.2.2 mjf /* 233 1.2.2.2 mjf * Now safe to install interrupt handlers. 234 1.2.2.2 mjf */ 235 1.2.2.2 mjf icu_intr_establish(maa->ma_irq, IST_EDGE, IPL_SERIAL, zshard, zsc); 236 1.2.2.2 mjf zsc->zsc_softintr_cookie = softint_establish(SOFTINT_SERIAL, 237 1.2.2.2 mjf (void (*)(void *))zsc_intr_soft, zsc); 238 1.2.2.2 mjf 239 1.2.2.2 mjf /* 240 1.2.2.2 mjf * Set the master interrupt enable and interrupt vector. 241 1.2.2.2 mjf * (common to both channels, do it on A) 242 1.2.2.2 mjf */ 243 1.2.2.2 mjf cs = zsc->zsc_cs[0]; 244 1.2.2.2 mjf s = splhigh(); 245 1.2.2.2 mjf /* interrupt vector */ 246 1.2.2.2 mjf zs_write_reg(cs, 2, 0); 247 1.2.2.2 mjf /* master interrupt control (enable) */ 248 1.2.2.2 mjf zs_write_reg(cs, 9, zs_init_reg[9]); 249 1.2.2.2 mjf splx(s); 250 1.2.2.2 mjf } 251 1.2.2.2 mjf 252 1.2.2.2 mjf static int 253 1.2.2.2 mjf zs_print(void *aux, const char *name) 254 1.2.2.2 mjf { 255 1.2.2.2 mjf struct zsc_attach_args *args = aux; 256 1.2.2.2 mjf 257 1.2.2.2 mjf if (name != NULL) 258 1.2.2.2 mjf aprint_normal("%s: ", name); 259 1.2.2.2 mjf 260 1.2.2.2 mjf if (args->channel != -1) 261 1.2.2.2 mjf aprint_normal(" channel %d", args->channel); 262 1.2.2.2 mjf 263 1.2.2.2 mjf return UNCONF; 264 1.2.2.2 mjf } 265 1.2.2.2 mjf 266 1.2.2.2 mjf static int 267 1.2.2.2 mjf zshard(void *arg) 268 1.2.2.2 mjf { 269 1.2.2.2 mjf struct zsc_softc *zsc = arg; 270 1.2.2.2 mjf int rval; 271 1.2.2.2 mjf 272 1.2.2.2 mjf rval = zsc_intr_hard(zsc); 273 1.2.2.2 mjf 274 1.2.2.2 mjf #if 1 275 1.2.2.2 mjf /* XXX: there is some race condition? */ 276 1.2.2.2 mjf if (rval) 277 1.2.2.2 mjf while (zsc_intr_hard(zsc)) 278 1.2.2.2 mjf ; 279 1.2.2.2 mjf #endif 280 1.2.2.2 mjf 281 1.2.2.2 mjf /* We are at splzs here, so no need to lock. */ 282 1.2.2.2 mjf if (zsc->zsc_cs[0]->cs_softreq || zsc->zsc_cs[1]->cs_softreq) 283 1.2.2.2 mjf softint_schedule(zsc->zsc_softintr_cookie); 284 1.2.2.2 mjf 285 1.2.2.2 mjf return rval; 286 1.2.2.2 mjf } 287 1.2.2.2 mjf 288 1.2.2.2 mjf /* 289 1.2.2.2 mjf * Compute the current baud rate given a ZS channel. 290 1.2.2.2 mjf */ 291 1.2.2.2 mjf #if 0 292 1.2.2.2 mjf static int 293 1.2.2.2 mjf zs_get_speed(struct zs_chanstate *cs) 294 1.2.2.2 mjf { 295 1.2.2.2 mjf int tconst; 296 1.2.2.2 mjf 297 1.2.2.2 mjf tconst = zs_read_reg(cs, 12); 298 1.2.2.2 mjf tconst |= zs_read_reg(cs, 13) << 8; 299 1.2.2.2 mjf return TCONST_TO_BPS(cs->cs_brg_clk, tconst); 300 1.2.2.2 mjf } 301 1.2.2.2 mjf #endif 302 1.2.2.2 mjf 303 1.2.2.2 mjf /* 304 1.2.2.2 mjf * MD functions for setting the baud rate and control modes. 305 1.2.2.2 mjf */ 306 1.2.2.2 mjf int 307 1.2.2.2 mjf zs_set_speed(struct zs_chanstate *cs, int bps) 308 1.2.2.2 mjf { 309 1.2.2.2 mjf int tconst, real_bps; 310 1.2.2.2 mjf 311 1.2.2.2 mjf if (bps == 0) 312 1.2.2.2 mjf return 0; 313 1.2.2.2 mjf 314 1.2.2.2 mjf #ifdef DIAGNOSTIC 315 1.2.2.2 mjf if (cs->cs_brg_clk == 0) 316 1.2.2.2 mjf panic("zs_set_speed"); 317 1.2.2.2 mjf #endif 318 1.2.2.2 mjf 319 1.2.2.2 mjf tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 320 1.2.2.2 mjf if (tconst < 0) 321 1.2.2.2 mjf return EINVAL; 322 1.2.2.2 mjf 323 1.2.2.2 mjf /* Convert back to make sure we can do it. */ 324 1.2.2.2 mjf real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 325 1.2.2.2 mjf 326 1.2.2.2 mjf /* Allow ~4% tolerance here */ 327 1.2.2.2 mjf if (abs(real_bps - bps) >= bps * 4 / 100) 328 1.2.2.2 mjf return EINVAL; 329 1.2.2.2 mjf 330 1.2.2.2 mjf cs->cs_preg[12] = tconst; 331 1.2.2.2 mjf cs->cs_preg[13] = tconst >> 8; 332 1.2.2.2 mjf 333 1.2.2.2 mjf /* Caller will stuff the pending registers. */ 334 1.2.2.2 mjf return 0; 335 1.2.2.2 mjf } 336 1.2.2.2 mjf 337 1.2.2.2 mjf int 338 1.2.2.2 mjf zs_set_modes(struct zs_chanstate *cs, int cflag) 339 1.2.2.2 mjf { 340 1.2.2.2 mjf int s; 341 1.2.2.2 mjf 342 1.2.2.2 mjf /* 343 1.2.2.2 mjf * Output hardware flow control on the chip is horrendous: 344 1.2.2.2 mjf * if carrier detect drops, the receiver is disabled, and if 345 1.2.2.2 mjf * CTS drops, the transmitter is stoped IN MID CHARACTER! 346 1.2.2.2 mjf * Therefore, NEVER set the HFC bit, and instead use the 347 1.2.2.2 mjf * status interrupt to detect CTS changes. 348 1.2.2.2 mjf */ 349 1.2.2.2 mjf s = splzs(); 350 1.2.2.2 mjf cs->cs_rr0_pps = 0; 351 1.2.2.2 mjf if ((cflag & (CLOCAL | MDMBUF)) != 0) { 352 1.2.2.2 mjf cs->cs_rr0_dcd = 0; 353 1.2.2.2 mjf if ((cflag & MDMBUF) == 0) 354 1.2.2.2 mjf cs->cs_rr0_pps = ZSRR0_DCD; 355 1.2.2.2 mjf } else 356 1.2.2.2 mjf cs->cs_rr0_dcd = ZSRR0_DCD; 357 1.2.2.2 mjf if ((cflag & CRTSCTS) != 0) { 358 1.2.2.2 mjf cs->cs_wr5_dtr = ZSWR5_DTR; 359 1.2.2.2 mjf cs->cs_wr5_rts = ZSWR5_RTS; 360 1.2.2.2 mjf cs->cs_rr0_cts = ZSRR0_CTS; 361 1.2.2.2 mjf } else if ((cflag & MDMBUF) != 0) { 362 1.2.2.2 mjf cs->cs_wr5_dtr = 0; 363 1.2.2.2 mjf cs->cs_wr5_rts = ZSWR5_DTR; 364 1.2.2.2 mjf cs->cs_rr0_cts = ZSRR0_DCD; 365 1.2.2.2 mjf } else { 366 1.2.2.2 mjf cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 367 1.2.2.2 mjf cs->cs_wr5_rts = 0; 368 1.2.2.2 mjf cs->cs_rr0_cts = 0; 369 1.2.2.2 mjf } 370 1.2.2.2 mjf splx(s); 371 1.2.2.2 mjf 372 1.2.2.2 mjf /* Caller will stuff the pending registers. */ 373 1.2.2.2 mjf return 0; 374 1.2.2.2 mjf } 375 1.2.2.2 mjf 376 1.2.2.2 mjf 377 1.2.2.2 mjf /* 378 1.2.2.2 mjf * Read or write the chip with suitable delays. 379 1.2.2.2 mjf */ 380 1.2.2.2 mjf 381 1.2.2.2 mjf uint8_t 382 1.2.2.2 mjf zs_read_reg(struct zs_chanstate *cs, uint8_t reg) 383 1.2.2.2 mjf { 384 1.2.2.2 mjf uint8_t val; 385 1.2.2.2 mjf 386 1.2.2.2 mjf *cs->cs_reg_csr = reg; 387 1.2.2.2 mjf ZS_DELAY(); 388 1.2.2.2 mjf val = *cs->cs_reg_csr; 389 1.2.2.2 mjf ZS_DELAY(); 390 1.2.2.2 mjf return val; 391 1.2.2.2 mjf } 392 1.2.2.2 mjf 393 1.2.2.2 mjf void 394 1.2.2.2 mjf zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val) 395 1.2.2.2 mjf { 396 1.2.2.2 mjf 397 1.2.2.2 mjf *cs->cs_reg_csr = reg; 398 1.2.2.2 mjf ZS_DELAY(); 399 1.2.2.2 mjf *cs->cs_reg_csr = val; 400 1.2.2.2 mjf ZS_DELAY(); 401 1.2.2.2 mjf } 402 1.2.2.2 mjf 403 1.2.2.2 mjf uint8_t 404 1.2.2.2 mjf zs_read_csr(struct zs_chanstate *cs) 405 1.2.2.2 mjf { 406 1.2.2.2 mjf uint8_t val; 407 1.2.2.2 mjf 408 1.2.2.2 mjf val = *cs->cs_reg_csr; 409 1.2.2.2 mjf ZS_DELAY(); 410 1.2.2.2 mjf return val; 411 1.2.2.2 mjf } 412 1.2.2.2 mjf 413 1.2.2.2 mjf void 414 1.2.2.2 mjf zs_write_csr(struct zs_chanstate *cs, uint8_t val) 415 1.2.2.2 mjf { 416 1.2.2.2 mjf 417 1.2.2.2 mjf *cs->cs_reg_csr = val; 418 1.2.2.2 mjf ZS_DELAY(); 419 1.2.2.2 mjf } 420 1.2.2.2 mjf 421 1.2.2.2 mjf uint8_t 422 1.2.2.2 mjf zs_read_data(struct zs_chanstate *cs) 423 1.2.2.2 mjf { 424 1.2.2.2 mjf uint8_t val; 425 1.2.2.2 mjf 426 1.2.2.2 mjf val = *cs->cs_reg_data; 427 1.2.2.2 mjf ZS_DELAY(); 428 1.2.2.2 mjf return val; 429 1.2.2.2 mjf } 430 1.2.2.2 mjf 431 1.2.2.2 mjf void 432 1.2.2.2 mjf zs_write_data(struct zs_chanstate *cs, uint8_t val) 433 1.2.2.2 mjf { 434 1.2.2.2 mjf 435 1.2.2.2 mjf *cs->cs_reg_data = val; 436 1.2.2.2 mjf ZS_DELAY(); 437 1.2.2.2 mjf } 438 1.2.2.2 mjf 439 1.2.2.2 mjf void 440 1.2.2.2 mjf zs_abort(struct zs_chanstate *cs) 441 1.2.2.2 mjf { 442 1.2.2.2 mjf 443 1.2.2.2 mjf #ifdef DDB 444 1.2.2.2 mjf Debugger(); 445 1.2.2.2 mjf #endif 446 1.2.2.2 mjf } 447 1.2.2.2 mjf 448 1.2.2.2 mjf /* 449 1.2.2.2 mjf * Polled input char. 450 1.2.2.2 mjf */ 451 1.2.2.2 mjf int 452 1.2.2.2 mjf zs_getc(void *arg) 453 1.2.2.2 mjf { 454 1.2.2.2 mjf struct zs_chanstate *cs = arg; 455 1.2.2.2 mjf int s, c; 456 1.2.2.2 mjf uint8_t rr0; 457 1.2.2.2 mjf 458 1.2.2.2 mjf s = splhigh(); 459 1.2.2.2 mjf /* Wait for a character to arrive. */ 460 1.2.2.2 mjf do { 461 1.2.2.2 mjf rr0 = *cs->cs_reg_csr; 462 1.2.2.2 mjf ZS_DELAY(); 463 1.2.2.2 mjf } while ((rr0 & ZSRR0_RX_READY) == 0); 464 1.2.2.2 mjf 465 1.2.2.2 mjf c = *cs->cs_reg_data; 466 1.2.2.2 mjf ZS_DELAY(); 467 1.2.2.2 mjf splx(s); 468 1.2.2.2 mjf 469 1.2.2.2 mjf return c; 470 1.2.2.2 mjf } 471 1.2.2.2 mjf 472 1.2.2.2 mjf /* 473 1.2.2.2 mjf * Polled output char. 474 1.2.2.2 mjf */ 475 1.2.2.2 mjf void 476 1.2.2.2 mjf zs_putc(void *arg, int c) 477 1.2.2.2 mjf { 478 1.2.2.2 mjf struct zs_chanstate *cs = arg; 479 1.2.2.2 mjf int s; 480 1.2.2.2 mjf uint8_t rr0; 481 1.2.2.2 mjf 482 1.2.2.2 mjf s = splhigh(); 483 1.2.2.2 mjf /* Wait for transmitter to become ready. */ 484 1.2.2.2 mjf do { 485 1.2.2.2 mjf rr0 = *cs->cs_reg_csr; 486 1.2.2.2 mjf ZS_DELAY(); 487 1.2.2.2 mjf } while ((rr0 & ZSRR0_TX_READY) == 0); 488 1.2.2.2 mjf 489 1.2.2.2 mjf *cs->cs_reg_data = c; 490 1.2.2.2 mjf ZS_DELAY(); 491 1.2.2.2 mjf splx(s); 492 1.2.2.2 mjf } 493 1.2.2.2 mjf 494 1.2.2.2 mjf void 495 1.2.2.2 mjf zscnprobe(struct consdev *cn) 496 1.2.2.2 mjf { 497 1.2.2.2 mjf 498 1.2.2.2 mjf cn->cn_pri = (console_present != 0 && cobalt_id == COBALT_ID_QUBE2700) 499 1.2.2.2 mjf ? CN_NORMAL : CN_DEAD; 500 1.2.2.2 mjf } 501 1.2.2.2 mjf 502 1.2.2.2 mjf void 503 1.2.2.2 mjf zscninit(struct consdev *cn) 504 1.2.2.2 mjf { 505 1.2.2.2 mjf struct zs_chanstate *cs; 506 1.2.2.2 mjf 507 1.2.2.2 mjf extern const struct cdevsw zstty_cdevsw; 508 1.2.2.2 mjf 509 1.2.2.2 mjf cn->cn_dev = makedev(cdevsw_lookup_major(&zstty_cdevsw), 0); 510 1.2.2.2 mjf 511 1.2.2.2 mjf zs_cons = (uint8_t *)MIPS_PHYS_TO_KSEG1(ZS_BASE) + ZS_CHAN_A; /* XXX */ 512 1.2.2.2 mjf 513 1.2.2.2 mjf zs_conschan = cs = &zs_conschan_store; 514 1.2.2.2 mjf 515 1.2.2.2 mjf /* Setup temporary chanstate. */ 516 1.2.2.2 mjf cs->cs_reg_csr = zs_cons + ZS_CSR; 517 1.2.2.2 mjf cs->cs_reg_data = zs_cons + ZS_DATA; 518 1.2.2.2 mjf 519 1.2.2.2 mjf /* Initialize the pending registers. */ 520 1.2.2.2 mjf memcpy(cs->cs_preg, zs_init_reg, 16); 521 1.2.2.2 mjf cs->cs_preg[5] |= ZSWR5_DTR | ZSWR5_RTS; 522 1.2.2.2 mjf 523 1.2.2.2 mjf cs->cs_preg[12] = BPS_TO_TCONST(PCLK / 16, ZS_DEFSPEED); 524 1.2.2.2 mjf cs->cs_preg[13] = 0; 525 1.2.2.2 mjf cs->cs_defspeed = ZS_DEFSPEED; 526 1.2.2.2 mjf 527 1.2.2.2 mjf /* Clear the master interrupt enable. */ 528 1.2.2.2 mjf zs_write_reg(cs, 9, 0); 529 1.2.2.2 mjf 530 1.2.2.2 mjf /* Reset the whole SCC chip. */ 531 1.2.2.2 mjf zs_write_reg(cs, 9, ZSWR9_HARD_RESET); 532 1.2.2.2 mjf 533 1.2.2.2 mjf /* Copy "pending" to "current" and H/W */ 534 1.2.2.2 mjf zs_loadchannelregs(cs); 535 1.2.2.2 mjf } 536 1.2.2.2 mjf 537 1.2.2.2 mjf int 538 1.2.2.2 mjf zscngetc(dev_t dev) 539 1.2.2.2 mjf { 540 1.2.2.2 mjf 541 1.2.2.2 mjf return zs_getc((void *)zs_conschan); 542 1.2.2.2 mjf } 543 1.2.2.2 mjf 544 1.2.2.2 mjf void 545 1.2.2.2 mjf zscnputc(dev_t dev, int c) 546 1.2.2.2 mjf { 547 1.2.2.2 mjf 548 1.2.2.2 mjf zs_putc((void *)zs_conschan, c); 549 1.2.2.2 mjf } 550
Indexes created Thu Oct 02 14:10:14 GMT 2025