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intr.h revision 1.2 
      1 /*	$NetBSD: intr.h,v 1.2 2000/03/21 02:27:50 soren Exp $	*/
      2 
      3 #include <mips/cpuregs.h>
      4 
      5 #define	IPL_NONE	0	/* Disable only this interrupt. */
      6 #define	IPL_BIO		1	/* Disable block I/O interrupts. */
      7 #define	IPL_NET		2	/* Disable network interrupts. */
      8 #define	IPL_TTY		3	/* Disable terminal interrupts. */
      9 #define	IPL_IMP		4	/* memory allocation */
     10 #define	IPL_CLOCK	4	/* Disable clock interrupts. */
     11 #define	IPL_STATCLOCK	5	/* Disable profiling interrupts. */
     12 #define	IPL_HIGH	6	/* Disable all interrupts. */
     13 #define NIPL		7
     14 
     15 /* Interrupt sharing types. */
     16 #define IST_NONE	0	/* none */
     17 #define IST_PULSE	1	/* pulsed */
     18 #define IST_EDGE	2	/* edge-triggered */
     19 #define IST_LEVEL	3	/* level-triggered */
     20 
     21 #define SIR_CLOCK	31
     22 #define SIR_NET		30
     23 #define SIR_CLOCKMASK	((1 << SIR_CLOCK))
     24 #define SIR_NETMASK	((1 << SIR_NET) | SIR_CLOCKMASK)
     25 #define SIR_ALLMASK	(SIR_CLOCKMASK | SIR_NETMASK)
     26 
     27 #ifndef _LOCORE
     28 
     29 int			imask[NIPL];
     30 
     31 extern int		_splraise(int);
     32 extern int		_spllower(int);
     33 extern int		_splset(int);
     34 extern int		_splget(void);
     35 extern void		_splnone(void);
     36 extern void		_setsoftintr(int);
     37 extern void		_clrsoftintr(int);
     38 
     39 #define setsoftclock()	_setsoftintr(MIPS_SOFT_INT_MASK_0)
     40 #define setsoftnet()	_setsoftintr(MIPS_SOFT_INT_MASK_1)
     41 #define clearsoftclock() _clrsoftintr(MIPS_SOFT_INT_MASK_0)
     42 #define clearsoftnet()	_clrsoftintr(MIPS_SOFT_INT_MASK_1)
     43 
     44 #define splhigh()       _splraise(MIPS_INT_MASK)
     45 #define spl0()          (void)_spllower(0)
     46 #define splx(s)         (void)_splset(s)
     47 #define SPLSOFT		MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1
     48 #define SPLBIO		SPLSOFT | MIPS_INT_MASK_4
     49 #define SPLNET		SPLBIO | MIPS_INT_MASK_1 | MIPS_INT_MASK_2
     50 #define SPLTTY		SPLNET | MIPS_INT_MASK_3
     51 #define SPLCLOCK	SPLTTY | MIPS_INT_MASK_0 | MIPS_INT_MASK_5
     52 #define splbio()        _splraise(SPLBIO)
     53 #define splnet()        _splraise(SPLNET)
     54 #define spltty()        _splraise(SPLTTY)
     55 #define splimp()	_splraise(SPLTTY)
     56 #define splclock()      _splraise(SPLCLOCK)
     57 #define splstatclock()  splclock()
     58 #define spllowersoftclock() _spllower(MIPS_SOFT_INT_MASK_0)
     59 #define splsoftclock()	_splraise(MIPS_SOFT_INT_MASK_0)
     60 #define splsoftnet()	_splraise(MIPS_SOFT_INT_MASK_1)
     61 
     62 extern unsigned int	intrcnt[];
     63 #define SOFTCLOCK_INTR	0
     64 #define SOFTNET_INTR	1
     65 #define CLOCK_INTR	2
     66 #define FPU_INTR	3
     67 
     68 /* Handle device interrupts. */
     69 extern int		(*mips_hardware_intr)(unsigned int, unsigned int,
     70 						unsigned int, unsigned int);
     71 
     72 /* Handle software interrupts. */
     73 extern void		(*mips_software_intr)(int);
     74 
     75 #endif /* _LOCORE */
     76