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intr.h revision 1.23.4.1 
      1 /*	$NetBSD: intr.h,v 1.23.4.1 2006/09/23 08:52:19 yamt Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 2000 Soren S. Jorvang.  All rights reserved.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions, and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  *
     15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
     16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
     19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     25  * SUCH DAMAGE.
     26  */
     27 
     28 #ifndef	_COBALT_INTR_H_
     29 #define	_COBALT_INTR_H_
     30 
     31 #define	IPL_NONE	0	/* Disable only this interrupt. */
     32 #define	IPL_SOFT	1	/* generic software interrupts */
     33 #define	IPL_SOFTSERIAL	2	/* serial software interrupts */
     34 #define	IPL_SOFTNET	3	/* network software interrupts */
     35 #define	IPL_SOFTCLOCK	4	/* clock software interrupts */
     36 #define	IPL_BIO		5	/* Disable block I/O interrupts. */
     37 #define	IPL_NET		6	/* Disable network interrupts. */
     38 #define	IPL_TTY		7	/* Disable terminal interrupts. */
     39 #define	IPL_SERIAL	IPL_TTY	/* Disable serial hardware interrupts. */
     40 #define	IPL_VM		8	/* Memory allocation */
     41 #define	IPL_CLOCK	9	/* Disable clock interrupts. */
     42 #define	IPL_STATCLOCK	10	/* Disable profiling interrupts. */
     43 #define	IPL_HIGH	11	/* Disable all interrupts. */
     44 #define	IPL_SCHED	IPL_HIGH
     45 #define	IPL_LOCK	IPL_HIGH
     46 #define NIPL		12
     47 
     48 /* Interrupt sharing types. */
     49 #define IST_NONE	0	/* none */
     50 #define IST_PULSE	1	/* pulsed */
     51 #define IST_EDGE	2	/* edge-triggered */
     52 #define IST_LEVEL	3	/* level-triggered */
     53 
     54 /* Soft interrupt numbers. */
     55 #define	SI_SOFT		0	/* generic software interrupts */
     56 #define	SI_SOFTSERIAL	1	/* serial software interrupts */
     57 #define	SI_SOFTNET	2	/* network software interrupts */
     58 #define	SI_SOFTCLOCK	3	/* clock software interrupts */
     59 
     60 #define	SI_NQUEUES	4
     61 
     62 #define	SI_QUEUENAMES {							\
     63 	"misc",								\
     64 	"serial",							\
     65 	"net",								\
     66 	"clock",							\
     67 }
     68 
     69 #ifdef _KERNEL
     70 #ifndef _LOCORE
     71 
     72 #include <sys/device.h>
     73 #include <mips/cpuregs.h>
     74 
     75 int  _splraise(int);
     76 int  _spllower(int);
     77 int  _splset(int);
     78 int  _splget(void);
     79 void _splnone(void);
     80 void _setsoftintr(int);
     81 void _clrsoftintr(int);
     82 
     83 #define splhigh()       _splraise(MIPS_INT_MASK)
     84 #define spl0()          (void)_spllower(0)
     85 #define splx(s)         (void)_splset(s)
     86 #define SPLSOFT		(MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1)
     87 #define SPLBIO		(SPLSOFT | MIPS_INT_MASK_4)
     88 #define SPLNET		(SPLBIO | MIPS_INT_MASK_1 | MIPS_INT_MASK_2)
     89 #define SPLTTY		(SPLNET | MIPS_INT_MASK_3)
     90 #define SPLCLOCK	(SPLTTY | MIPS_INT_MASK_0 | MIPS_INT_MASK_5)
     91 #define splbio()	_splraise(SPLBIO)
     92 #define splnet()	_splraise(SPLNET)
     93 #define spltty()	_splraise(SPLTTY)
     94 #define spllpt()	spltty()
     95 #define splserial()	_splraise(SPLTTY)
     96 #define splclock()	_splraise(SPLCLOCK)
     97 #define splvm()		splclock()
     98 #define splstatclock()	splclock()
     99 #define spllowersoftclock() _spllower(MIPS_SOFT_INT_MASK_0)
    100 
    101 #define	splsched()	splhigh()
    102 #define	spllock()	splhigh()
    103 
    104 #define splsoft()	_splraise(MIPS_SOFT_INT_MASK_0)
    105 #define splsoftclock()	_splraise(MIPS_SOFT_INT_MASK_0)
    106 #define splsoftnet()	_splraise(MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1)
    107 #define splsoftserial()	_splraise(MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1)
    108 
    109 typedef int ipl_t;
    110 typedef struct {
    111 	int _spl;
    112 } ipl_cookie_t;
    113 
    114 ipl_cookie_t makeiplcookie(ipl_t);
    115 
    116 static inline int
    117 splraiseipl(ipl_cookie_t icookie)
    118 {
    119 
    120 	return _splraise(icookie._spl);
    121 }
    122 
    123 struct cobalt_intrhand {
    124 	LIST_ENTRY(cobalt_intrhand) ih_q;
    125 	int (*ih_func)(void *);
    126 	void *ih_arg;
    127 	int ih_type;
    128 	int ih_cookie_type;
    129 #define	COBALT_COOKIE_TYPE_CPU	0x1
    130 #define	COBALT_COOKIE_TYPE_ICU	0x2
    131 
    132 	struct evcnt ih_evcnt;
    133 	char ih_evname[32];
    134 };
    135 
    136 #include <mips/softintr.h>
    137 
    138 void *cpu_intr_establish(int, int, int (*)(void *), void *);
    139 void *icu_intr_establish(int, int, int, int (*)(void *), void *);
    140 void cpu_intr_disestablish(void *);
    141 void icu_intr_disestablish(void *);
    142 void icu_init(void);
    143 
    144 #endif /* !_LOCORE */
    145 #endif /* _LOCORE */
    146 
    147 #endif	/* !_COBALT_INTR_H_ */
    148