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intr.h revision 1.30 
      1 /*	$NetBSD: intr.h,v 1.30 2008/01/04 22:55:25 ad Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 2000 Soren S. Jorvang.  All rights reserved.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions, and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  *
     15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
     16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
     19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     25  * SUCH DAMAGE.
     26  */
     27 
     28 #ifndef	_COBALT_INTR_H_
     29 #define	_COBALT_INTR_H_
     30 
     31 #define	IPL_NONE	0	/* Disable only this interrupt. */
     32 #define	IPL_SOFTCLOCK	1	/* generic software interrupts */
     33 #define	IPL_SOFTBIO	1	/* clock software interrupts */
     34 #define	IPL_SOFTNET	2	/* network software interrupts */
     35 #define	IPL_SOFTSERIAL	2	/* serial software interrupts */
     36 #define	IPL_VM		3	/* Memory allocation */
     37 #define	IPL_SCHED	4	/* Disable clock interrupts. */
     38 #define	IPL_HIGH	4	/* Disable all interrupts. */
     39 #define NIPL		5
     40 
     41 /* Interrupt sharing types. */
     42 #define IST_NONE	0	/* none */
     43 #define IST_PULSE	1	/* pulsed */
     44 #define IST_EDGE	2	/* edge-triggered */
     45 #define IST_LEVEL	3	/* level-triggered */
     46 
     47 #ifdef _KERNEL
     48 #ifndef _LOCORE
     49 
     50 #include <sys/evcnt.h>
     51 #include <mips/cpuregs.h>
     52 #include <mips/locore.h>
     53 
     54 #define SPLVM		(MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 | \
     55 			MIPS_INT_MASK_1 | MIPS_INT_MASK_2 | \
     56 			MIPS_INT_MASK_3 | MIPS_INT_MASK_4)
     57 #define SPLSCHED	(SPLVM | MIPS_INT_MASK_5)
     58 
     59 #define spl0()          (void)_spllower(0)
     60 #define splx(s)         (void)_splset(s)
     61 #define splvm()		_splraise(SPLVM)
     62 #define splsched()	_splraise(SPLSCHED)
     63 #define splhigh()       _splraise(MIPS_INT_MASK)
     64 
     65 #define splsoftclock()	_splraise(MIPS_SOFT_INT_MASK_0)
     66 #define splsoftbio()	_splraise(MIPS_SOFT_INT_MASK_0)
     67 #define splsoftnet()	_splraise(MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1)
     68 #define splsoftserial()	_splraise(MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1)
     69 
     70 typedef int ipl_t;
     71 typedef struct {
     72 	int _spl;
     73 } ipl_cookie_t;
     74 
     75 ipl_cookie_t makeiplcookie(ipl_t);
     76 
     77 static inline int
     78 splraiseipl(ipl_cookie_t icookie)
     79 {
     80 
     81 	return _splraise(icookie._spl);
     82 }
     83 
     84 struct cobalt_intrhand {
     85 	LIST_ENTRY(cobalt_intrhand) ih_q;
     86 	int (*ih_func)(void *);
     87 	void *ih_arg;
     88 	int ih_type;
     89 	int ih_cookie_type;
     90 #define	COBALT_COOKIE_TYPE_CPU	0x1
     91 #define	COBALT_COOKIE_TYPE_ICU	0x2
     92 
     93 	struct evcnt ih_evcnt;
     94 	char ih_evname[32];
     95 };
     96 
     97 #include <mips/softintr.h>
     98 
     99 void *cpu_intr_establish(int, int, int (*)(void *), void *);
    100 void *icu_intr_establish(int, int, int, int (*)(void *), void *);
    101 void cpu_intr_disestablish(void *);
    102 void icu_intr_disestablish(void *);
    103 void icu_init(void);
    104 
    105 #endif /* !_LOCORE */
    106 #endif /* _LOCORE */
    107 
    108 #endif	/* !_COBALT_INTR_H_ */
    109