cache.c revision 1.2.8.2 1 1.2.8.2 matt /* $NetBSD: cache.c,v 1.2.8.2 2007/11/06 23:15:44 matt Exp $ */
2 1.2.8.2 matt
3 1.2.8.2 matt /*
4 1.2.8.2 matt * Copyright 2001 Wasabi Systems, Inc.
5 1.2.8.2 matt * All rights reserved.
6 1.2.8.2 matt *
7 1.2.8.2 matt * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8 1.2.8.2 matt *
9 1.2.8.2 matt * Redistribution and use in source and binary forms, with or without
10 1.2.8.2 matt * modification, are permitted provided that the following conditions
11 1.2.8.2 matt * are met:
12 1.2.8.2 matt * 1. Redistributions of source code must retain the above copyright
13 1.2.8.2 matt * notice, this list of conditions and the following disclaimer.
14 1.2.8.2 matt * 2. Redistributions in binary form must reproduce the above copyright
15 1.2.8.2 matt * notice, this list of conditions and the following disclaimer in the
16 1.2.8.2 matt * documentation and/or other materials provided with the distribution.
17 1.2.8.2 matt * 3. All advertising materials mentioning features or use of this software
18 1.2.8.2 matt * must display the following acknowledgement:
19 1.2.8.2 matt * This product includes software developed for the NetBSD Project by
20 1.2.8.2 matt * Wasabi Systems, Inc.
21 1.2.8.2 matt * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 1.2.8.2 matt * or promote products derived from this software without specific prior
23 1.2.8.2 matt * written permission.
24 1.2.8.2 matt *
25 1.2.8.2 matt * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 1.2.8.2 matt * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 1.2.8.2 matt * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 1.2.8.2 matt * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 1.2.8.2 matt * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 1.2.8.2 matt * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 1.2.8.2 matt * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 1.2.8.2 matt * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 1.2.8.2 matt * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 1.2.8.2 matt * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 1.2.8.2 matt * POSSIBILITY OF SUCH DAMAGE.
36 1.2.8.2 matt */
37 1.2.8.2 matt
38 1.2.8.2 matt #include <lib/libsa/stand.h>
39 1.2.8.2 matt #include <lib/libkern/libkern.h>
40 1.2.8.2 matt
41 1.2.8.2 matt #include <mips/cpuregs.h>
42 1.2.8.2 matt #include <mips/cache_r4k.h>
43 1.2.8.2 matt
44 1.2.8.2 matt #include "boot.h"
45 1.2.8.2 matt
46 1.2.8.2 matt #define round_line(x) (((x) + (CACHELINESIZE - 1)) & ~(CACHELINESIZE - 1))
47 1.2.8.2 matt #define trunc_line(x) ((x) & ~(CACHELINESIZE - 1))
48 1.2.8.2 matt
49 1.2.8.2 matt __asm(".set mips3");
50 1.2.8.2 matt
51 1.2.8.2 matt void
52 1.2.8.2 matt pdcache_inv(uint32_t va, u_int size)
53 1.2.8.2 matt {
54 1.2.8.2 matt uint32_t eva;
55 1.2.8.2 matt
56 1.2.8.2 matt eva = round_line(va + size);
57 1.2.8.2 matt va = trunc_line(va);
58 1.2.8.2 matt
59 1.2.8.2 matt while (va < eva) {
60 1.2.8.2 matt cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_INV);
61 1.2.8.2 matt va += CACHELINESIZE;
62 1.2.8.2 matt }
63 1.2.8.2 matt }
64 1.2.8.2 matt
65 1.2.8.2 matt void
66 1.2.8.2 matt pdcache_wb(uint32_t va, u_int size)
67 1.2.8.2 matt {
68 1.2.8.2 matt uint32_t eva;
69 1.2.8.2 matt
70 1.2.8.2 matt eva = round_line(va + size);
71 1.2.8.2 matt va = trunc_line(va);
72 1.2.8.2 matt
73 1.2.8.2 matt while (va < eva) {
74 1.2.8.2 matt cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB);
75 1.2.8.2 matt va += CACHELINESIZE;
76 1.2.8.2 matt }
77 1.2.8.2 matt }
78 1.2.8.2 matt
79 1.2.8.2 matt void
80 1.2.8.2 matt pdcache_wbinv(uint32_t va, u_int size)
81 1.2.8.2 matt {
82 1.2.8.2 matt uint32_t eva;
83 1.2.8.2 matt
84 1.2.8.2 matt eva = round_line(va + size);
85 1.2.8.2 matt va = trunc_line(va);
86 1.2.8.2 matt
87 1.2.8.2 matt while (va < eva) {
88 1.2.8.2 matt cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
89 1.2.8.2 matt va += CACHELINESIZE;
90 1.2.8.2 matt }
91 1.2.8.2 matt }
92