tlp.c revision 1.3.14.2
1 /* $NetBSD: tlp.c,v 1.3.14.2 2007/12/03 19:03:11 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 2007 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Tohru Nishimura. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/socket.h> 41 42 #include <netinet/in.h> 43 #include <netinet/in_systm.h> 44 45 #include <lib/libsa/stand.h> 46 #include <lib/libsa/net.h> 47 48 #include <mips/cpuregs.h> 49 50 #include "boot.h" 51 52 /* 53 * - little endian access for CSR register. 54 * - assume KSEG0 on vtophys() translation. 55 * - PIPT writeback cache aware. 56 */ 57 #define CSR_WRITE(l, r, v) \ 58 do { \ 59 *(volatile uint32_t *)((l)->csr + (r)) = (v); \ 60 } while (0) 61 #define CSR_READ(l, r) (*(volatile uint32_t *)((l)->csr + (r))) 62 #define VTOPHYS(va) MIPS_KSEG0_TO_PHYS(va) 63 #define wb(adr, siz) pdcache_wb((uint32_t)(adr), (u_int)(siz)) 64 #define wbinv(adr, siz) pdcache_wbinv((uint32_t)(adr), (u_int)(siz)) 65 #define inv(adr, siz) pdcache_inv((uint32_t)(adr), (u_int)(siz)) 66 #define DELAY(n) delay(n) 67 #define ALLOC(T, A) (T *)((uint32_t)alloc(sizeof(T) + (A)) & ~((A) - 1)) 68 69 #define T0_OWN (1U<<31) /* desc is ready to tx */ 70 #define T0_ES (1U<<15) /* Tx error summary */ 71 #define T1_LS (1U<<30) /* last segment */ 72 #define T1_FS (1U<<29) /* first segment */ 73 #define T1_SET (1U<<27) /* "setup packet" */ 74 #define T1_TER (1U<<25) /* end of ring mark */ 75 #define T1_TBS_MASK 0x7ff /* segment size 10:0 */ 76 #define R0_OWN (1U<<31) /* desc is empty */ 77 #define R0_FS (1U<<30) /* first desc of frame */ 78 #define R0_LS (1U<<8) /* last desc of frame */ 79 #define R0_ES (1U<<15) /* Rx error summary */ 80 #define R1_RCH (1U<<24) /* Second address chained */ 81 #define R1_RER (1U<<25) /* end of ring mark */ 82 #define R0_FL_MASK 0x3fff0000 /* frame length 29:16 */ 83 #define R1_RBS_MASK 0x7ff /* segment size 10:0 */ 84 85 #define DESCSIZE 16 86 struct desc { 87 volatile uint32_t xd0, xd1, xd2, xd3; 88 #if CACHELINESIZE > DESCSIZE 89 uint8_t pad[CACHELINESIZE - DESCSIZE]; 90 #endif 91 }; 92 93 #define TLP_BMR 0x000 /* 0: bus mode */ 94 #define BMR_RST (1U<< 0) /* software reset */ 95 #define TLP_TPD 0x008 /* 1: instruct Tx to start */ 96 #define TPD_POLL (1U<< 0) /* transmit poll demand */ 97 #define TLP_RPD 0x010 /* 2: instruct Rx to start */ 98 #define RPD_POLL (1U<< 0) /* receive poll demand */ 99 #define TLP_RRBA 0x018 /* 3: Rx descriptor base */ 100 #define TLP_TRBA 0x020 /* 4: Tx descriptor base */ 101 #define TLP_STS 0x028 /* 5: status */ 102 #define STS_TS 0x00700000 /* Tx status */ 103 #define STS_RS 0x000e0000 /* Rx status */ 104 #define TLP_OMR 0x030 /* 6: operation mode */ 105 #define OMR_SDP (1U<<25) /* always ON */ 106 #define OMR_PS (1U<<18) /* port select */ 107 #define OMR_PM (1U<< 6) /* promicuous */ 108 #define OMR_TEN (1U<<13) /* instruct start/stop Tx */ 109 #define OMR_REN (1U<< 1) /* instruct start/stop Rx */ 110 #define OMR_FD (1U<< 9) /* FDX */ 111 #define TLP_IEN 0x38 /* 7: interrupt enable mask */ 112 #define TLP_APROM 0x048 /* 9: SEEPROM and MII management */ 113 #define SROM_RD (1U <<14) /* read operation */ 114 #define SROM_WR (1U <<13) /* write openration */ 115 #define SROM_SR (1U <<11) /* SEEPROM select */ 116 #define TLP_CSR12 0x60 /* SIA status */ 117 118 #define TLP_CSR15 0x78 /* SIA general register */ 119 #define SIAGEN_MD0 (1U<<16) 120 #define SIAGEN_CWE (1U<<28) 121 122 #define FRAMESIZE 1536 123 #define BUFSIZE 2048 124 #define NRXBUF 2 125 #define NEXT_RXBUF(x) (((x) + 1) & (NRXBUF - 1)) 126 127 struct local { 128 struct desc TxD; 129 struct desc RxD[NRXBUF]; 130 uint8_t txstore[BUFSIZE]; 131 uint8_t rxstore[NRXBUF][BUFSIZE]; 132 uint32_t csr, omr; 133 u_int rx; 134 u_int sromsft; 135 u_int phy; 136 uint32_t bmsr, anlpar; 137 }; 138 139 #define COBALT_TLP0_BASE 0x10100000 140 #define SROM_MAC_OFFSET 0 141 142 static void size_srom(struct local *); 143 static u_int read_srom(struct local *, int); 144 #if 0 145 static u_int tlp_mii_read(struct local *, int, int); 146 static void tlp_mii_write(struct local *, int, int, int); 147 static void mii_initphy(struct local *); 148 #endif 149 150 void * 151 tlp_init(void *cookie) 152 { 153 uint32_t val; 154 struct local *l; 155 struct desc *TxD, *RxD; 156 uint8_t *en; 157 int i; 158 159 l = ALLOC(struct local, CACHELINESIZE); 160 memset(l, 0, sizeof(struct local)); 161 162 DPRINTF(("tlp: l = %p, TxD = %p, RxD[0] = %p, RxD[1] = %p\n", 163 l, &l->TxD, &l->RxD[0], &l->RxD[1])); 164 DPRINTF(("tlp: txstore = %p, rxstore[0] = %p, rxstore[1] = %p\n", 165 l->txstore, l->rxstore[0], l->rxstore[1])); 166 167 #if 0 168 /* XXX assume tlp0 at pci0 dev 7 function 0 */ 169 tag = (0 << 16) | ( 7 << 11) | (0 << 8); 170 /* memory map is not initialized by the firmware on cobalt */ 171 l->csr = MIPS_PHYS_TO_KSEG1(pcicfgread(tag, 0x10) & 0xfffffffc); 172 DPRINTF(("%s: CSR = 0x%x\n", __func__, l->csr)); 173 #else 174 l->csr = MIPS_PHYS_TO_KSEG1(COBALT_TLP0_BASE); 175 #endif 176 177 val = CSR_READ(l, TLP_BMR); 178 CSR_WRITE(l, TLP_BMR, val | BMR_RST); 179 DELAY(1000); 180 CSR_WRITE(l, TLP_BMR, val); 181 DELAY(1000); 182 (void)CSR_READ(l, TLP_BMR); 183 184 l->omr = OMR_PS | OMR_SDP; 185 CSR_WRITE(l, TLP_OMR, l->omr); 186 CSR_WRITE(l, TLP_STS, ~0); 187 CSR_WRITE(l, TLP_IEN, 0); 188 189 #if 0 190 mii_initphy(l); 191 #endif 192 size_srom(l); 193 194 en = cookie; 195 /* MAC address is stored at offset 0 in SROM on cobalt */ 196 val = read_srom(l, SROM_MAC_OFFSET / 2 + 0); 197 en[0] = val; 198 en[1] = val >> 8; 199 val = read_srom(l, SROM_MAC_OFFSET / 2 + 1); 200 en[2] = val; 201 en[3] = val >> 8; 202 val = read_srom(l, SROM_MAC_OFFSET / 2 + 2); 203 en[4] = val; 204 en[5] = val >> 8; 205 206 DPRINTF(("tlp: MAC address %x:%x:%x:%x:%x:%x\n", 207 en[0], en[1], en[2], en[3], en[4], en[5])); 208 209 RxD = &l->RxD[0]; 210 for (i = 0; i < NRXBUF; i++) { 211 RxD[i].xd3 = htole32(VTOPHYS(&RxD[NEXT_RXBUF(i)])); 212 RxD[i].xd2 = htole32(VTOPHYS(l->rxstore[i])); 213 RxD[i].xd1 = htole32(R1_RCH|FRAMESIZE); 214 RxD[i].xd0 = htole32(R0_OWN); 215 } 216 CSR_WRITE(l, TLP_RRBA, VTOPHYS(RxD)); 217 218 /* "setup packet" to have own station address */ 219 TxD = &l->TxD; 220 TxD->xd3 = htole32(VTOPHYS(TxD)); 221 TxD->xd2 = htole32(VTOPHYS(l->txstore)); 222 TxD->xd1 = htole32(T1_SET | T1_TER); 223 TxD->xd0 = htole32(0); 224 CSR_WRITE(l, TLP_TRBA, VTOPHYS(TxD)); 225 226 memset(l->txstore, 0, FRAMESIZE); 227 228 /* make sure the entire descriptors transfered to memory */ 229 wbinv(l, sizeof(struct local)); 230 231 l->rx = 0; 232 l->omr |= OMR_FD | OMR_TEN | OMR_REN; 233 234 #if 1 235 /* reset PHY (cobalt quirk from if_tlp_pci.c) */ 236 CSR_WRITE(l, TLP_CSR15, SIAGEN_CWE | SIAGEN_MD0); 237 DELAY(10); 238 CSR_WRITE(l, TLP_CSR15, SIAGEN_CWE); 239 DELAY(10); 240 #endif 241 242 /* start Tx/Rx */ 243 CSR_WRITE(l, TLP_OMR, l->omr); 244 #if 0 245 CSR_WRITE(l, TLP_TPD, TPD_POLL); 246 #endif 247 CSR_WRITE(l, TLP_RPD, RPD_POLL); 248 249 return l; 250 } 251 252 int 253 tlp_send(void *dev, char *buf, u_int len) 254 { 255 struct local *l = dev; 256 struct desc *TxD; 257 u_int loop; 258 259 #if 1 260 wb(buf, len); 261 TxD = &l->TxD; 262 TxD->xd3 = htole32(VTOPHYS(TxD)); 263 TxD->xd2 = htole32(VTOPHYS(buf)); 264 TxD->xd1 = htole32(T1_FS | T1_LS | T1_TER | (len & T1_TBS_MASK)); 265 #else 266 memcpy(l->txstore, buf, len); 267 wb(l->txstore, len); 268 TxD = &l->TxD; 269 TxD->xd3 = htole32(VTOPHYS(TxD)); 270 TxD->xd2 = htole32(VTOPHYS(l->txstore)); 271 TxD->xd1 = htole32(T1_FS | T1_LS | T1_TER | (len & T1_TBS_MASK)); 272 #endif 273 TxD->xd0 = htole32(T0_OWN); 274 wbinv(TxD, sizeof(struct desc)); 275 CSR_WRITE(l, TLP_TPD, TPD_POLL); 276 loop = 100; 277 do { 278 if ((le32toh(TxD->xd0) & T0_OWN) == 0) 279 goto done; 280 inv(TxD, sizeof(struct desc)); 281 DELAY(10); 282 } while (--loop > 0); 283 printf("xmit failed\n"); 284 return -1; 285 done: 286 return len; 287 } 288 289 int 290 tlp_recv(void *dev, char *buf, u_int maxlen, u_int timo) 291 { 292 struct local *l = dev; 293 struct desc *RxD; 294 u_int bound, len; 295 uint32_t rxstat; 296 uint8_t *ptr; 297 298 bound = 1000 * timo; 299 300 again: 301 RxD = &l->RxD[l->rx]; 302 do { 303 rxstat = le32toh(RxD->xd0); 304 inv(RxD, sizeof(struct desc)); 305 if ((rxstat & R0_OWN) == 0) 306 goto gotone; 307 DELAY(1000); /* 1 milli second */ 308 } while (--bound > 0); 309 errno = 0; 310 CSR_WRITE(l, TLP_RPD, RPD_POLL); 311 return -1; 312 gotone: 313 if (rxstat & R0_ES) { 314 RxD->xd0 = htole32(R0_OWN); 315 wbinv(RxD, sizeof(struct desc)); 316 l->rx = NEXT_RXBUF(l->rx); 317 CSR_WRITE(l, TLP_RPD, RPD_POLL); 318 goto again; 319 } 320 /* good frame */ 321 len = ((rxstat & R0_FL_MASK) >> 16) - 4; /* HASFCS */ 322 if (len > maxlen) 323 len = maxlen; 324 ptr = l->rxstore[l->rx]; 325 memcpy(buf, ptr, len); 326 inv(ptr, FRAMESIZE); 327 RxD->xd0 = htole32(R0_OWN); 328 wbinv(RxD, sizeof(struct desc)); 329 l->rx = NEXT_RXBUF(l->rx); 330 CSR_WRITE(l, TLP_OMR, l->omr); /* necessary? */ 331 return len; 332 } 333 334 static void 335 size_srom(struct local *l) 336 { 337 /* determine 8/6 bit addressing SEEPROM */ 338 l->sromsft = 8; 339 l->sromsft = (read_srom(l, 255) & 0x40000) ? 8 : 6; 340 } 341 342 /* 343 * bare SEEPROM access with bitbang'ing 344 */ 345 #define R110 6 /* SEEPROM read op */ 346 #define CS (1U << 0) /* hold chip select */ 347 #define CLK (1U << 1) /* clk bit */ 348 #define D1 (1U << 2) /* bit existence */ 349 #define D0 0 /* bit absence */ 350 #define VV (1U << 3) /* taken 0/1 from SEEPROM */ 351 352 static u_int 353 read_srom(struct local *l, int off) 354 { 355 u_int idx, cnt, ret; 356 uint32_t val, x1, x0, bit; 357 358 idx = off & 0xff; /* A7-A0 */ 359 idx |= R110 << l->sromsft; /* 110 for READ */ 360 361 val = SROM_RD | SROM_SR; 362 CSR_WRITE(l, TLP_APROM, val); 363 val |= CS; /* hold CS */ 364 CSR_WRITE(l, TLP_APROM, val); 365 366 x1 = val | D1; /* 1 */ 367 x0 = val | D0; /* 0 */ 368 /* instruct R110 op. at off in MSB first order */ 369 for (cnt = (1 << (l->sromsft + 2)); cnt > 0; cnt >>= 1) { 370 bit = (idx & cnt) ? x1 : x0; 371 CSR_WRITE(l, TLP_APROM, bit); 372 DELAY(10); 373 CSR_WRITE(l, TLP_APROM, bit | CLK); 374 DELAY(10); 375 } 376 /* read 16bit quantity in MSB first order */ 377 ret = 0; 378 for (cnt = 16; cnt > 0; cnt--) { 379 CSR_WRITE(l, TLP_APROM, val); 380 DELAY(10); 381 CSR_WRITE(l, TLP_APROM, val | CLK); 382 DELAY(10); 383 ret = (ret << 1) | !!(CSR_READ(l, TLP_APROM) & VV); 384 } 385 val &= ~CS; /* turn off chip select */ 386 CSR_WRITE(l, TLP_APROM, val); 387 388 return ret; 389 } 390 391 #if 0 392 393 static u_int 394 tlp_mii_read(struct local *l, int phy, int reg) 395 { 396 /* later ... */ 397 return 0; 398 } 399 400 static void 401 tlp_mii_write(struct local *l, int phy, int reg, int val) 402 { 403 /* later ... */ 404 } 405 406 #define MII_BMCR 0x00 /* Basic mode control register (rw) */ 407 #define BMCR_RESET 0x8000 /* reset */ 408 #define BMCR_AUTOEN 0x1000 /* autonegotiation enable */ 409 #define BMCR_ISO 0x0400 /* isolate */ 410 #define BMCR_STARTNEG 0x0200 /* restart autonegotiation */ 411 #define MII_BMSR 0x01 /* Basic mode status register (ro) */ 412 413 static void 414 mii_initphy(struct local *l) 415 { 416 int phy, bound; 417 uint32_t ctl, sts; 418 419 for (phy = 0; phy < 32; phy++) { 420 ctl = tlp_mii_read(l, phy, MII_BMCR); 421 sts = tlp_mii_read(l, phy, MII_BMSR); 422 if (ctl != 0xffff && sts != 0xffff) 423 goto found; 424 } 425 printf("MII: no PHY found\n"); 426 return; 427 found: 428 ctl = tlp_mii_read(l, phy, MII_BMCR); 429 tlp_mii_write(l, phy, MII_BMCR, ctl | BMCR_RESET); 430 bound = 100; 431 do { 432 DELAY(10); 433 ctl = tlp_mii_read(l, phy, MII_BMCR); 434 if (ctl == 0xffff) { 435 printf("MII: PHY %d has died after reset\n", phy); 436 return; 437 } 438 } while (bound-- > 0 && (ctl & BMCR_RESET)); 439 if (bound == 0) { 440 printf("PHY %d reset failed\n", phy); 441 } 442 ctl &= ~BMCR_ISO; 443 tlp_mii_write(l, phy, MII_BMCR, ctl); 444 sts = tlp_mii_read(l, phy, MII_BMSR) | 445 tlp_mii_read(l, phy, MII_BMSR); /* read twice */ 446 l->phy = phy; 447 l->bmsr = sts; 448 } 449 450 static void 451 mii_dealan(struct local *, u_int timo) 452 { 453 uint32_t anar; 454 u_int bound; 455 456 anar = ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA; 457 tlp_mii_write(l, l->phy, MII_ANAR, anar); 458 tlp_mii_write(l, l->phy, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 459 l->anlpar = 0; 460 bound = getsecs() + timo; 461 do { 462 l->bmsr = tlp_mii_read(l, l->phy, MII_BMSR) | 463 tlp_mii_read(l, l->phy, MII_BMSR); /* read twice */ 464 if ((l->bmsr & BMSR_LINK) && (l->bmsr & BMSR_ACOMP)) { 465 l->anlpar = tlp_mii_read(l, l->phy, MII_ANLPAR); 466 break; 467 } 468 DELAY(10 * 1000); 469 } while (getsecs() < bound); 470 return; 471 } 472 #endif 473 /* $NetBSD: tlp.c,v 1.3.14.2 2007/12/03 19:03:11 ad Exp $ */ 474 475 /*- 476 * Copyright (c) 2007 The NetBSD Foundation, Inc. 477 * All rights reserved. 478 * 479 * This code is derived from software contributed to The NetBSD Foundation 480 * by Tohru Nishimura. 481 * 482 * Redistribution and use in source and binary forms, with or without 483 * modification, are permitted provided that the following conditions 484 * are met: 485 * 1. Redistributions of source code must retain the above copyright 486 * notice, this list of conditions and the following disclaimer. 487 * 2. Redistributions in binary form must reproduce the above copyright 488 * notice, this list of conditions and the following disclaimer in the 489 * documentation and/or other materials provided with the distribution. 490 * 3. All advertising materials mentioning features or use of this software 491 * must display the following acknowledgement: 492 * This product includes software developed by the NetBSD 493 * Foundation, Inc. and its contributors. 494 * 4. Neither the name of The NetBSD Foundation nor the names of its 495 * contributors may be used to endorse or promote products derived 496 * from this software without specific prior written permission. 497 * 498 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 499 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 500 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 501 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 502 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 503 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 504 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 505 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 506 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 507 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 508 * POSSIBILITY OF SUCH DAMAGE. 509 */ 510 511 #include <sys/param.h> 512 #include <sys/socket.h> 513 514 #include <netinet/in.h> 515 #include <netinet/in_systm.h> 516 517 #include <lib/libsa/stand.h> 518 #include <lib/libsa/net.h> 519 520 #include <mips/cpuregs.h> 521 522 #include "boot.h" 523 524 /* 525 * - little endian access for CSR register. 526 * - assume KSEG0 on vtophys() translation. 527 * - PIPT writeback cache aware. 528 */ 529 #define CSR_WRITE(l, r, v) \ 530 do { \ 531 *(volatile uint32_t *)((l)->csr + (r)) = (v); \ 532 } while (0) 533 #define CSR_READ(l, r) (*(volatile uint32_t *)((l)->csr + (r))) 534 #define VTOPHYS(va) MIPS_KSEG0_TO_PHYS(va) 535 #define wb(adr, siz) pdcache_wb((uint32_t)(adr), (u_int)(siz)) 536 #define wbinv(adr, siz) pdcache_wbinv((uint32_t)(adr), (u_int)(siz)) 537 #define inv(adr, siz) pdcache_inv((uint32_t)(adr), (u_int)(siz)) 538 #define DELAY(n) delay(n) 539 #define ALLOC(T, A) (T *)((uint32_t)alloc(sizeof(T) + (A)) & ~((A) - 1)) 540 541 #define T0_OWN (1U<<31) /* desc is ready to tx */ 542 #define T0_ES (1U<<15) /* Tx error summary */ 543 #define T1_LS (1U<<30) /* last segment */ 544 #define T1_FS (1U<<29) /* first segment */ 545 #define T1_SET (1U<<27) /* "setup packet" */ 546 #define T1_TER (1U<<25) /* end of ring mark */ 547 #define T1_TBS_MASK 0x7ff /* segment size 10:0 */ 548 #define R0_OWN (1U<<31) /* desc is empty */ 549 #define R0_FS (1U<<30) /* first desc of frame */ 550 #define R0_LS (1U<<8) /* last desc of frame */ 551 #define R0_ES (1U<<15) /* Rx error summary */ 552 #define R1_RCH (1U<<24) /* Second address chained */ 553 #define R1_RER (1U<<25) /* end of ring mark */ 554 #define R0_FL_MASK 0x3fff0000 /* frame length 29:16 */ 555 #define R1_RBS_MASK 0x7ff /* segment size 10:0 */ 556 557 #define DESCSIZE 16 558 struct desc { 559 volatile uint32_t xd0, xd1, xd2, xd3; 560 #if CACHELINESIZE > DESCSIZE 561 uint8_t pad[CACHELINESIZE - DESCSIZE]; 562 #endif 563 }; 564 565 #define TLP_BMR 0x000 /* 0: bus mode */ 566 #define BMR_RST (1U<< 0) /* software reset */ 567 #define TLP_TPD 0x008 /* 1: instruct Tx to start */ 568 #define TPD_POLL (1U<< 0) /* transmit poll demand */ 569 #define TLP_RPD 0x010 /* 2: instruct Rx to start */ 570 #define RPD_POLL (1U<< 0) /* receive poll demand */ 571 #define TLP_RRBA 0x018 /* 3: Rx descriptor base */ 572 #define TLP_TRBA 0x020 /* 4: Tx descriptor base */ 573 #define TLP_STS 0x028 /* 5: status */ 574 #define STS_TS 0x00700000 /* Tx status */ 575 #define STS_RS 0x000e0000 /* Rx status */ 576 #define TLP_OMR 0x030 /* 6: operation mode */ 577 #define OMR_SDP (1U<<25) /* always ON */ 578 #define OMR_PS (1U<<18) /* port select */ 579 #define OMR_PM (1U<< 6) /* promicuous */ 580 #define OMR_TEN (1U<<13) /* instruct start/stop Tx */ 581 #define OMR_REN (1U<< 1) /* instruct start/stop Rx */ 582 #define OMR_FD (1U<< 9) /* FDX */ 583 #define TLP_IEN 0x38 /* 7: interrupt enable mask */ 584 #define TLP_APROM 0x048 /* 9: SEEPROM and MII management */ 585 #define SROM_RD (1U <<14) /* read operation */ 586 #define SROM_WR (1U <<13) /* write openration */ 587 #define SROM_SR (1U <<11) /* SEEPROM select */ 588 #define TLP_CSR12 0x60 /* SIA status */ 589 590 #define TLP_CSR15 0x78 /* SIA general register */ 591 #define SIAGEN_MD0 (1U<<16) 592 #define SIAGEN_CWE (1U<<28) 593 594 #define FRAMESIZE 1536 595 #define BUFSIZE 2048 596 #define NRXBUF 2 597 #define NEXT_RXBUF(x) (((x) + 1) & (NRXBUF - 1)) 598 599 struct local { 600 struct desc TxD; 601 struct desc RxD[NRXBUF]; 602 uint8_t txstore[BUFSIZE]; 603 uint8_t rxstore[NRXBUF][BUFSIZE]; 604 uint32_t csr, omr; 605 u_int rx; 606 u_int sromsft; 607 u_int phy; 608 uint32_t bmsr, anlpar; 609 }; 610 611 #define COBALT_TLP0_BASE 0x10100000 612 #define SROM_MAC_OFFSET 0 613 614 static void size_srom(struct local *); 615 static u_int read_srom(struct local *, int); 616 #if 0 617 static u_int tlp_mii_read(struct local *, int, int); 618 static void tlp_mii_write(struct local *, int, int, int); 619 static void mii_initphy(struct local *); 620 #endif 621 622 void * 623 tlp_init(void *cookie) 624 { 625 uint32_t val; 626 struct local *l; 627 struct desc *TxD, *RxD; 628 uint8_t *en; 629 int i; 630 631 l = ALLOC(struct local, CACHELINESIZE); 632 memset(l, 0, sizeof(struct local)); 633 634 DPRINTF(("tlp: l = %p, TxD = %p, RxD[0] = %p, RxD[1] = %p\n", 635 l, &l->TxD, &l->RxD[0], &l->RxD[1])); 636 DPRINTF(("tlp: txstore = %p, rxstore[0] = %p, rxstore[1] = %p\n", 637 l->txstore, l->rxstore[0], l->rxstore[1])); 638 639 #if 0 640 /* XXX assume tlp0 at pci0 dev 7 function 0 */ 641 tag = (0 << 16) | ( 7 << 11) | (0 << 8); 642 /* memory map is not initialized by the firmware on cobalt */ 643 l->csr = MIPS_PHYS_TO_KSEG1(pcicfgread(tag, 0x10) & 0xfffffffc); 644 DPRINTF(("%s: CSR = 0x%x\n", __func__, l->csr)); 645 #else 646 l->csr = MIPS_PHYS_TO_KSEG1(COBALT_TLP0_BASE); 647 #endif 648 649 val = CSR_READ(l, TLP_BMR); 650 CSR_WRITE(l, TLP_BMR, val | BMR_RST); 651 DELAY(1000); 652 CSR_WRITE(l, TLP_BMR, val); 653 DELAY(1000); 654 (void)CSR_READ(l, TLP_BMR); 655 656 l->omr = OMR_PS | OMR_SDP; 657 CSR_WRITE(l, TLP_OMR, l->omr); 658 CSR_WRITE(l, TLP_STS, ~0); 659 CSR_WRITE(l, TLP_IEN, 0); 660 661 #if 0 662 mii_initphy(l); 663 #endif 664 size_srom(l); 665 666 en = cookie; 667 /* MAC address is stored at offset 0 in SROM on cobalt */ 668 val = read_srom(l, SROM_MAC_OFFSET / 2 + 0); 669 en[0] = val; 670 en[1] = val >> 8; 671 val = read_srom(l, SROM_MAC_OFFSET / 2 + 1); 672 en[2] = val; 673 en[3] = val >> 8; 674 val = read_srom(l, SROM_MAC_OFFSET / 2 + 2); 675 en[4] = val; 676 en[5] = val >> 8; 677 678 DPRINTF(("tlp: MAC address %x:%x:%x:%x:%x:%x\n", 679 en[0], en[1], en[2], en[3], en[4], en[5])); 680 681 RxD = &l->RxD[0]; 682 for (i = 0; i < NRXBUF; i++) { 683 RxD[i].xd3 = htole32(VTOPHYS(&RxD[NEXT_RXBUF(i)])); 684 RxD[i].xd2 = htole32(VTOPHYS(l->rxstore[i])); 685 RxD[i].xd1 = htole32(R1_RCH|FRAMESIZE); 686 RxD[i].xd0 = htole32(R0_OWN); 687 } 688 CSR_WRITE(l, TLP_RRBA, VTOPHYS(RxD)); 689 690 /* "setup packet" to have own station address */ 691 TxD = &l->TxD; 692 TxD->xd3 = htole32(VTOPHYS(TxD)); 693 TxD->xd2 = htole32(VTOPHYS(l->txstore)); 694 TxD->xd1 = htole32(T1_SET | T1_TER); 695 TxD->xd0 = htole32(0); 696 CSR_WRITE(l, TLP_TRBA, VTOPHYS(TxD)); 697 698 memset(l->txstore, 0, FRAMESIZE); 699 700 /* make sure the entire descriptors transfered to memory */ 701 wbinv(l, sizeof(struct local)); 702 703 l->rx = 0; 704 l->omr |= OMR_FD | OMR_TEN | OMR_REN; 705 706 #if 1 707 /* reset PHY (cobalt quirk from if_tlp_pci.c) */ 708 CSR_WRITE(l, TLP_CSR15, SIAGEN_CWE | SIAGEN_MD0); 709 DELAY(10); 710 CSR_WRITE(l, TLP_CSR15, SIAGEN_CWE); 711 DELAY(10); 712 #endif 713 714 /* start Tx/Rx */ 715 CSR_WRITE(l, TLP_OMR, l->omr); 716 #if 0 717 CSR_WRITE(l, TLP_TPD, TPD_POLL); 718 #endif 719 CSR_WRITE(l, TLP_RPD, RPD_POLL); 720 721 return l; 722 } 723 724 int 725 tlp_send(void *dev, char *buf, u_int len) 726 { 727 struct local *l = dev; 728 struct desc *TxD; 729 u_int loop; 730 731 #if 1 732 wb(buf, len); 733 TxD = &l->TxD; 734 TxD->xd3 = htole32(VTOPHYS(TxD)); 735 TxD->xd2 = htole32(VTOPHYS(buf)); 736 TxD->xd1 = htole32(T1_FS | T1_LS | T1_TER | (len & T1_TBS_MASK)); 737 #else 738 memcpy(l->txstore, buf, len); 739 wb(l->txstore, len); 740 TxD = &l->TxD; 741 TxD->xd3 = htole32(VTOPHYS(TxD)); 742 TxD->xd2 = htole32(VTOPHYS(l->txstore)); 743 TxD->xd1 = htole32(T1_FS | T1_LS | T1_TER | (len & T1_TBS_MASK)); 744 #endif 745 TxD->xd0 = htole32(T0_OWN); 746 wbinv(TxD, sizeof(struct desc)); 747 CSR_WRITE(l, TLP_TPD, TPD_POLL); 748 loop = 100; 749 do { 750 if ((le32toh(TxD->xd0) & T0_OWN) == 0) 751 goto done; 752 inv(TxD, sizeof(struct desc)); 753 DELAY(10); 754 } while (--loop > 0); 755 printf("xmit failed\n"); 756 return -1; 757 done: 758 return len; 759 } 760 761 int 762 tlp_recv(void *dev, char *buf, u_int maxlen, u_int timo) 763 { 764 struct local *l = dev; 765 struct desc *RxD; 766 u_int bound, len; 767 uint32_t rxstat; 768 uint8_t *ptr; 769 770 bound = 1000 * timo; 771 772 again: 773 RxD = &l->RxD[l->rx]; 774 do { 775 rxstat = le32toh(RxD->xd0); 776 inv(RxD, sizeof(struct desc)); 777 if ((rxstat & R0_OWN) == 0) 778 goto gotone; 779 DELAY(1000); /* 1 milli second */ 780 } while (--bound > 0); 781 errno = 0; 782 CSR_WRITE(l, TLP_RPD, RPD_POLL); 783 return -1; 784 gotone: 785 if (rxstat & R0_ES) { 786 RxD->xd0 = htole32(R0_OWN); 787 wbinv(RxD, sizeof(struct desc)); 788 l->rx = NEXT_RXBUF(l->rx); 789 CSR_WRITE(l, TLP_RPD, RPD_POLL); 790 goto again; 791 } 792 /* good frame */ 793 len = ((rxstat & R0_FL_MASK) >> 16) - 4; /* HASFCS */ 794 if (len > maxlen) 795 len = maxlen; 796 ptr = l->rxstore[l->rx]; 797 memcpy(buf, ptr, len); 798 inv(ptr, FRAMESIZE); 799 RxD->xd0 = htole32(R0_OWN); 800 wbinv(RxD, sizeof(struct desc)); 801 l->rx = NEXT_RXBUF(l->rx); 802 CSR_WRITE(l, TLP_OMR, l->omr); /* necessary? */ 803 return len; 804 } 805 806 static void 807 size_srom(struct local *l) 808 { 809 /* determine 8/6 bit addressing SEEPROM */ 810 l->sromsft = 8; 811 l->sromsft = (read_srom(l, 255) & 0x40000) ? 8 : 6; 812 } 813 814 /* 815 * bare SEEPROM access with bitbang'ing 816 */ 817 #define R110 6 /* SEEPROM read op */ 818 #define CS (1U << 0) /* hold chip select */ 819 #define CLK (1U << 1) /* clk bit */ 820 #define D1 (1U << 2) /* bit existence */ 821 #define D0 0 /* bit absence */ 822 #define VV (1U << 3) /* taken 0/1 from SEEPROM */ 823 824 static u_int 825 read_srom(struct local *l, int off) 826 { 827 u_int idx, cnt, ret; 828 uint32_t val, x1, x0, bit; 829 830 idx = off & 0xff; /* A7-A0 */ 831 idx |= R110 << l->sromsft; /* 110 for READ */ 832 833 val = SROM_RD | SROM_SR; 834 CSR_WRITE(l, TLP_APROM, val); 835 val |= CS; /* hold CS */ 836 CSR_WRITE(l, TLP_APROM, val); 837 838 x1 = val | D1; /* 1 */ 839 x0 = val | D0; /* 0 */ 840 /* instruct R110 op. at off in MSB first order */ 841 for (cnt = (1 << (l->sromsft + 2)); cnt > 0; cnt >>= 1) { 842 bit = (idx & cnt) ? x1 : x0; 843 CSR_WRITE(l, TLP_APROM, bit); 844 DELAY(10); 845 CSR_WRITE(l, TLP_APROM, bit | CLK); 846 DELAY(10); 847 } 848 /* read 16bit quantity in MSB first order */ 849 ret = 0; 850 for (cnt = 16; cnt > 0; cnt--) { 851 CSR_WRITE(l, TLP_APROM, val); 852 DELAY(10); 853 CSR_WRITE(l, TLP_APROM, val | CLK); 854 DELAY(10); 855 ret = (ret << 1) | !!(CSR_READ(l, TLP_APROM) & VV); 856 } 857 val &= ~CS; /* turn off chip select */ 858 CSR_WRITE(l, TLP_APROM, val); 859 860 return ret; 861 } 862 863 #if 0 864 865 static u_int 866 tlp_mii_read(struct local *l, int phy, int reg) 867 { 868 /* later ... */ 869 return 0; 870 } 871 872 static void 873 tlp_mii_write(struct local *l, int phy, int reg, int val) 874 { 875 /* later ... */ 876 } 877 878 #define MII_BMCR 0x00 /* Basic mode control register (rw) */ 879 #define BMCR_RESET 0x8000 /* reset */ 880 #define BMCR_AUTOEN 0x1000 /* autonegotiation enable */ 881 #define BMCR_ISO 0x0400 /* isolate */ 882 #define BMCR_STARTNEG 0x0200 /* restart autonegotiation */ 883 #define MII_BMSR 0x01 /* Basic mode status register (ro) */ 884 885 static void 886 mii_initphy(struct local *l) 887 { 888 int phy, bound; 889 uint32_t ctl, sts; 890 891 for (phy = 0; phy < 32; phy++) { 892 ctl = tlp_mii_read(l, phy, MII_BMCR); 893 sts = tlp_mii_read(l, phy, MII_BMSR); 894 if (ctl != 0xffff && sts != 0xffff) 895 goto found; 896 } 897 printf("MII: no PHY found\n"); 898 return; 899 found: 900 ctl = tlp_mii_read(l, phy, MII_BMCR); 901 tlp_mii_write(l, phy, MII_BMCR, ctl | BMCR_RESET); 902 bound = 100; 903 do { 904 DELAY(10); 905 ctl = tlp_mii_read(l, phy, MII_BMCR); 906 if (ctl == 0xffff) { 907 printf("MII: PHY %d has died after reset\n", phy); 908 return; 909 } 910 } while (bound-- > 0 && (ctl & BMCR_RESET)); 911 if (bound == 0) { 912 printf("PHY %d reset failed\n", phy); 913 } 914 ctl &= ~BMCR_ISO; 915 tlp_mii_write(l, phy, MII_BMCR, ctl); 916 sts = tlp_mii_read(l, phy, MII_BMSR) | 917 tlp_mii_read(l, phy, MII_BMSR); /* read twice */ 918 l->phy = phy; 919 l->bmsr = sts; 920 } 921 922 static void 923 mii_dealan(struct local *, u_int timo) 924 { 925 uint32_t anar; 926 u_int bound; 927 928 anar = ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA; 929 tlp_mii_write(l, l->phy, MII_ANAR, anar); 930 tlp_mii_write(l, l->phy, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 931 l->anlpar = 0; 932 bound = getsecs() + timo; 933 do { 934 l->bmsr = tlp_mii_read(l, l->phy, MII_BMSR) | 935 tlp_mii_read(l, l->phy, MII_BMSR); /* read twice */ 936 if ((l->bmsr & BMSR_LINK) && (l->bmsr & BMSR_ACOMP)) { 937 l->anlpar = tlp_mii_read(l, l->phy, MII_ANLPAR); 938 break; 939 } 940 DELAY(10 * 1000); 941 } while (getsecs() < bound); 942 return; 943 } 944 #endif 945 /* $NetBSD: tlp.c,v 1.3.14.2 2007/12/03 19:03:11 ad Exp $ */ 946 947 /*- 948 * Copyright (c) 2007 The NetBSD Foundation, Inc. 949 * All rights reserved. 950 * 951 * This code is derived from software contributed to The NetBSD Foundation 952 * by Tohru Nishimura. 953 * 954 * Redistribution and use in source and binary forms, with or without 955 * modification, are permitted provided that the following conditions 956 * are met: 957 * 1. Redistributions of source code must retain the above copyright 958 * notice, this list of conditions and the following disclaimer. 959 * 2. Redistributions in binary form must reproduce the above copyright 960 * notice, this list of conditions and the following disclaimer in the 961 * documentation and/or other materials provided with the distribution. 962 * 3. All advertising materials mentioning features or use of this software 963 * must display the following acknowledgement: 964 * This product includes software developed by the NetBSD 965 * Foundation, Inc. and its contributors. 966 * 4. Neither the name of The NetBSD Foundation nor the names of its 967 * contributors may be used to endorse or promote products derived 968 * from this software without specific prior written permission. 969 * 970 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 971 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 972 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 973 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 974 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 975 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 976 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 977 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 978 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 979 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 980 * POSSIBILITY OF SUCH DAMAGE. 981 */ 982 983 #include <sys/param.h> 984 #include <sys/socket.h> 985 986 #include <netinet/in.h> 987 #include <netinet/in_systm.h> 988 989 #include <lib/libsa/stand.h> 990 #include <lib/libsa/net.h> 991 992 #include <mips/cpuregs.h> 993 994 #include "boot.h" 995 996 /* 997 * - little endian access for CSR register. 998 * - assume KSEG0 on vtophys() translation. 999 * - PIPT writeback cache aware. 1000 */ 1001 #define CSR_WRITE(l, r, v) \ 1002 do { \ 1003 *(volatile uint32_t *)((l)->csr + (r)) = (v); \ 1004 } while (0) 1005 #define CSR_READ(l, r) (*(volatile uint32_t *)((l)->csr + (r))) 1006 #define VTOPHYS(va) MIPS_KSEG0_TO_PHYS(va) 1007 #define wb(adr, siz) pdcache_wb((uint32_t)(adr), (u_int)(siz)) 1008 #define wbinv(adr, siz) pdcache_wbinv((uint32_t)(adr), (u_int)(siz)) 1009 #define inv(adr, siz) pdcache_inv((uint32_t)(adr), (u_int)(siz)) 1010 #define DELAY(n) delay(n) 1011 #define ALLOC(T, A) (T *)((uint32_t)alloc(sizeof(T) + (A)) & ~((A) - 1)) 1012 1013 #define T0_OWN (1U<<31) /* desc is ready to tx */ 1014 #define T0_ES (1U<<15) /* Tx error summary */ 1015 #define T1_LS (1U<<30) /* last segment */ 1016 #define T1_FS (1U<<29) /* first segment */ 1017 #define T1_SET (1U<<27) /* "setup packet" */ 1018 #define T1_TER (1U<<25) /* end of ring mark */ 1019 #define T1_TBS_MASK 0x7ff /* segment size 10:0 */ 1020 #define R0_OWN (1U<<31) /* desc is empty */ 1021 #define R0_FS (1U<<30) /* first desc of frame */ 1022 #define R0_LS (1U<<8) /* last desc of frame */ 1023 #define R0_ES (1U<<15) /* Rx error summary */ 1024 #define R1_RCH (1U<<24) /* Second address chained */ 1025 #define R1_RER (1U<<25) /* end of ring mark */ 1026 #define R0_FL_MASK 0x3fff0000 /* frame length 29:16 */ 1027 #define R1_RBS_MASK 0x7ff /* segment size 10:0 */ 1028 1029 #define DESCSIZE 16 1030 struct desc { 1031 volatile uint32_t xd0, xd1, xd2, xd3; 1032 #if CACHELINESIZE > DESCSIZE 1033 uint8_t pad[CACHELINESIZE - DESCSIZE]; 1034 #endif 1035 }; 1036 1037 #define TLP_BMR 0x000 /* 0: bus mode */ 1038 #define BMR_RST (1U<< 0) /* software reset */ 1039 #define TLP_TPD 0x008 /* 1: instruct Tx to start */ 1040 #define TPD_POLL (1U<< 0) /* transmit poll demand */ 1041 #define TLP_RPD 0x010 /* 2: instruct Rx to start */ 1042 #define RPD_POLL (1U<< 0) /* receive poll demand */ 1043 #define TLP_RRBA 0x018 /* 3: Rx descriptor base */ 1044 #define TLP_TRBA 0x020 /* 4: Tx descriptor base */ 1045 #define TLP_STS 0x028 /* 5: status */ 1046 #define STS_TS 0x00700000 /* Tx status */ 1047 #define STS_RS 0x000e0000 /* Rx status */ 1048 #define TLP_OMR 0x030 /* 6: operation mode */ 1049 #define OMR_SDP (1U<<25) /* always ON */ 1050 #define OMR_PS (1U<<18) /* port select */ 1051 #define OMR_PM (1U<< 6) /* promicuous */ 1052 #define OMR_TEN (1U<<13) /* instruct start/stop Tx */ 1053 #define OMR_REN (1U<< 1) /* instruct start/stop Rx */ 1054 #define OMR_FD (1U<< 9) /* FDX */ 1055 #define TLP_IEN 0x38 /* 7: interrupt enable mask */ 1056 #define TLP_APROM 0x048 /* 9: SEEPROM and MII management */ 1057 #define SROM_RD (1U <<14) /* read operation */ 1058 #define SROM_WR (1U <<13) /* write openration */ 1059 #define SROM_SR (1U <<11) /* SEEPROM select */ 1060 #define TLP_CSR12 0x60 /* SIA status */ 1061 1062 #define TLP_CSR15 0x78 /* SIA general register */ 1063 #define SIAGEN_MD0 (1U<<16) 1064 #define SIAGEN_CWE (1U<<28) 1065 1066 #define FRAMESIZE 1536 1067 #define BUFSIZE 2048 1068 #define NRXBUF 2 1069 #define NEXT_RXBUF(x) (((x) + 1) & (NRXBUF - 1)) 1070 1071 struct local { 1072 struct desc TxD; 1073 struct desc RxD[NRXBUF]; 1074 uint8_t txstore[BUFSIZE]; 1075 uint8_t rxstore[NRXBUF][BUFSIZE]; 1076 uint32_t csr, omr; 1077 u_int rx; 1078 u_int sromsft; 1079 u_int phy; 1080 uint32_t bmsr, anlpar; 1081 }; 1082 1083 #define COBALT_TLP0_BASE 0x10100000 1084 #define SROM_MAC_OFFSET 0 1085 1086 static void size_srom(struct local *); 1087 static u_int read_srom(struct local *, int); 1088 #if 0 1089 static u_int tlp_mii_read(struct local *, int, int); 1090 static void tlp_mii_write(struct local *, int, int, int); 1091 static void mii_initphy(struct local *); 1092 #endif 1093 1094 void * 1095 tlp_init(void *cookie) 1096 { 1097 uint32_t val; 1098 struct local *l; 1099 struct desc *TxD, *RxD; 1100 uint8_t *en; 1101 int i; 1102 1103 l = ALLOC(struct local, CACHELINESIZE); 1104 memset(l, 0, sizeof(struct local)); 1105 1106 DPRINTF(("tlp: l = %p, TxD = %p, RxD[0] = %p, RxD[1] = %p\n", 1107 l, &l->TxD, &l->RxD[0], &l->RxD[1])); 1108 DPRINTF(("tlp: txstore = %p, rxstore[0] = %p, rxstore[1] = %p\n", 1109 l->txstore, l->rxstore[0], l->rxstore[1])); 1110 1111 #if 0 1112 /* XXX assume tlp0 at pci0 dev 7 function 0 */ 1113 tag = (0 << 16) | ( 7 << 11) | (0 << 8); 1114 /* memory map is not initialized by the firmware on cobalt */ 1115 l->csr = MIPS_PHYS_TO_KSEG1(pcicfgread(tag, 0x10) & 0xfffffffc); 1116 DPRINTF(("%s: CSR = 0x%x\n", __func__, l->csr)); 1117 #else 1118 l->csr = MIPS_PHYS_TO_KSEG1(COBALT_TLP0_BASE); 1119 #endif 1120 1121 val = CSR_READ(l, TLP_BMR); 1122 CSR_WRITE(l, TLP_BMR, val | BMR_RST); 1123 DELAY(1000); 1124 CSR_WRITE(l, TLP_BMR, val); 1125 DELAY(1000); 1126 (void)CSR_READ(l, TLP_BMR); 1127 1128 l->omr = OMR_PS | OMR_SDP; 1129 CSR_WRITE(l, TLP_OMR, l->omr); 1130 CSR_WRITE(l, TLP_STS, ~0); 1131 CSR_WRITE(l, TLP_IEN, 0); 1132 1133 #if 0 1134 mii_initphy(l); 1135 #endif 1136 size_srom(l); 1137 1138 en = cookie; 1139 /* MAC address is stored at offset 0 in SROM on cobalt */ 1140 val = read_srom(l, SROM_MAC_OFFSET / 2 + 0); 1141 en[0] = val; 1142 en[1] = val >> 8; 1143 val = read_srom(l, SROM_MAC_OFFSET / 2 + 1); 1144 en[2] = val; 1145 en[3] = val >> 8; 1146 val = read_srom(l, SROM_MAC_OFFSET / 2 + 2); 1147 en[4] = val; 1148 en[5] = val >> 8; 1149 1150 DPRINTF(("tlp: MAC address %x:%x:%x:%x:%x:%x\n", 1151 en[0], en[1], en[2], en[3], en[4], en[5])); 1152 1153 RxD = &l->RxD[0]; 1154 for (i = 0; i < NRXBUF; i++) { 1155 RxD[i].xd3 = htole32(VTOPHYS(&RxD[NEXT_RXBUF(i)])); 1156 RxD[i].xd2 = htole32(VTOPHYS(l->rxstore[i])); 1157 RxD[i].xd1 = htole32(R1_RCH|FRAMESIZE); 1158 RxD[i].xd0 = htole32(R0_OWN); 1159 } 1160 CSR_WRITE(l, TLP_RRBA, VTOPHYS(RxD)); 1161 1162 /* "setup packet" to have own station address */ 1163 TxD = &l->TxD; 1164 TxD->xd3 = htole32(VTOPHYS(TxD)); 1165 TxD->xd2 = htole32(VTOPHYS(l->txstore)); 1166 TxD->xd1 = htole32(T1_SET | T1_TER); 1167 TxD->xd0 = htole32(0); 1168 CSR_WRITE(l, TLP_TRBA, VTOPHYS(TxD)); 1169 1170 memset(l->txstore, 0, FRAMESIZE); 1171 1172 /* make sure the entire descriptors transfered to memory */ 1173 wbinv(l, sizeof(struct local)); 1174 1175 l->rx = 0; 1176 l->omr |= OMR_FD | OMR_TEN | OMR_REN; 1177 1178 #if 1 1179 /* reset PHY (cobalt quirk from if_tlp_pci.c) */ 1180 CSR_WRITE(l, TLP_CSR15, SIAGEN_CWE | SIAGEN_MD0); 1181 DELAY(10); 1182 CSR_WRITE(l, TLP_CSR15, SIAGEN_CWE); 1183 DELAY(10); 1184 #endif 1185 1186 /* start Tx/Rx */ 1187 CSR_WRITE(l, TLP_OMR, l->omr); 1188 #if 0 1189 CSR_WRITE(l, TLP_TPD, TPD_POLL); 1190 #endif 1191 CSR_WRITE(l, TLP_RPD, RPD_POLL); 1192 1193 return l; 1194 } 1195 1196 int 1197 tlp_send(void *dev, char *buf, u_int len) 1198 { 1199 struct local *l = dev; 1200 struct desc *TxD; 1201 u_int loop; 1202 1203 #if 1 1204 wb(buf, len); 1205 TxD = &l->TxD; 1206 TxD->xd3 = htole32(VTOPHYS(TxD)); 1207 TxD->xd2 = htole32(VTOPHYS(buf)); 1208 TxD->xd1 = htole32(T1_FS | T1_LS | T1_TER | (len & T1_TBS_MASK)); 1209 #else 1210 memcpy(l->txstore, buf, len); 1211 wb(l->txstore, len); 1212 TxD = &l->TxD; 1213 TxD->xd3 = htole32(VTOPHYS(TxD)); 1214 TxD->xd2 = htole32(VTOPHYS(l->txstore)); 1215 TxD->xd1 = htole32(T1_FS | T1_LS | T1_TER | (len & T1_TBS_MASK)); 1216 #endif 1217 TxD->xd0 = htole32(T0_OWN); 1218 wbinv(TxD, sizeof(struct desc)); 1219 CSR_WRITE(l, TLP_TPD, TPD_POLL); 1220 loop = 100; 1221 do { 1222 if ((le32toh(TxD->xd0) & T0_OWN) == 0) 1223 goto done; 1224 inv(TxD, sizeof(struct desc)); 1225 DELAY(10); 1226 } while (--loop > 0); 1227 printf("xmit failed\n"); 1228 return -1; 1229 done: 1230 return len; 1231 } 1232 1233 int 1234 tlp_recv(void *dev, char *buf, u_int maxlen, u_int timo) 1235 { 1236 struct local *l = dev; 1237 struct desc *RxD; 1238 u_int bound, len; 1239 uint32_t rxstat; 1240 uint8_t *ptr; 1241 1242 bound = 1000 * timo; 1243 1244 again: 1245 RxD = &l->RxD[l->rx]; 1246 do { 1247 rxstat = le32toh(RxD->xd0); 1248 inv(RxD, sizeof(struct desc)); 1249 if ((rxstat & R0_OWN) == 0) 1250 goto gotone; 1251 DELAY(1000); /* 1 milli second */ 1252 } while (--bound > 0); 1253 errno = 0; 1254 CSR_WRITE(l, TLP_RPD, RPD_POLL); 1255 return -1; 1256 gotone: 1257 if (rxstat & R0_ES) { 1258 RxD->xd0 = htole32(R0_OWN); 1259 wbinv(RxD, sizeof(struct desc)); 1260 l->rx = NEXT_RXBUF(l->rx); 1261 CSR_WRITE(l, TLP_RPD, RPD_POLL); 1262 goto again; 1263 } 1264 /* good frame */ 1265 len = ((rxstat & R0_FL_MASK) >> 16) - 4; /* HASFCS */ 1266 if (len > maxlen) 1267 len = maxlen; 1268 ptr = l->rxstore[l->rx]; 1269 memcpy(buf, ptr, len); 1270 inv(ptr, FRAMESIZE); 1271 RxD->xd0 = htole32(R0_OWN); 1272 wbinv(RxD, sizeof(struct desc)); 1273 l->rx = NEXT_RXBUF(l->rx); 1274 CSR_WRITE(l, TLP_OMR, l->omr); /* necessary? */ 1275 return len; 1276 } 1277 1278 static void 1279 size_srom(struct local *l) 1280 { 1281 /* determine 8/6 bit addressing SEEPROM */ 1282 l->sromsft = 8; 1283 l->sromsft = (read_srom(l, 255) & 0x40000) ? 8 : 6; 1284 } 1285 1286 /* 1287 * bare SEEPROM access with bitbang'ing 1288 */ 1289 #define R110 6 /* SEEPROM read op */ 1290 #define CS (1U << 0) /* hold chip select */ 1291 #define CLK (1U << 1) /* clk bit */ 1292 #define D1 (1U << 2) /* bit existence */ 1293 #define D0 0 /* bit absence */ 1294 #define VV (1U << 3) /* taken 0/1 from SEEPROM */ 1295 1296 static u_int 1297 read_srom(struct local *l, int off) 1298 { 1299 u_int idx, cnt, ret; 1300 uint32_t val, x1, x0, bit; 1301 1302 idx = off & 0xff; /* A7-A0 */ 1303 idx |= R110 << l->sromsft; /* 110 for READ */ 1304 1305 val = SROM_RD | SROM_SR; 1306 CSR_WRITE(l, TLP_APROM, val); 1307 val |= CS; /* hold CS */ 1308 CSR_WRITE(l, TLP_APROM, val); 1309 1310 x1 = val | D1; /* 1 */ 1311 x0 = val | D0; /* 0 */ 1312 /* instruct R110 op. at off in MSB first order */ 1313 for (cnt = (1 << (l->sromsft + 2)); cnt > 0; cnt >>= 1) { 1314 bit = (idx & cnt) ? x1 : x0; 1315 CSR_WRITE(l, TLP_APROM, bit); 1316 DELAY(10); 1317 CSR_WRITE(l, TLP_APROM, bit | CLK); 1318 DELAY(10); 1319 } 1320 /* read 16bit quantity in MSB first order */ 1321 ret = 0; 1322 for (cnt = 16; cnt > 0; cnt--) { 1323 CSR_WRITE(l, TLP_APROM, val); 1324 DELAY(10); 1325 CSR_WRITE(l, TLP_APROM, val | CLK); 1326 DELAY(10); 1327 ret = (ret << 1) | !!(CSR_READ(l, TLP_APROM) & VV); 1328 } 1329 val &= ~CS; /* turn off chip select */ 1330 CSR_WRITE(l, TLP_APROM, val); 1331 1332 return ret; 1333 } 1334 1335 #if 0 1336 1337 static u_int 1338 tlp_mii_read(struct local *l, int phy, int reg) 1339 { 1340 /* later ... */ 1341 return 0; 1342 } 1343 1344 static void 1345 tlp_mii_write(struct local *l, int phy, int reg, int val) 1346 { 1347 /* later ... */ 1348 } 1349 1350 #define MII_BMCR 0x00 /* Basic mode control register (rw) */ 1351 #define BMCR_RESET 0x8000 /* reset */ 1352 #define BMCR_AUTOEN 0x1000 /* autonegotiation enable */ 1353 #define BMCR_ISO 0x0400 /* isolate */ 1354 #define BMCR_STARTNEG 0x0200 /* restart autonegotiation */ 1355 #define MII_BMSR 0x01 /* Basic mode status register (ro) */ 1356 1357 static void 1358 mii_initphy(struct local *l) 1359 { 1360 int phy, bound; 1361 uint32_t ctl, sts; 1362 1363 for (phy = 0; phy < 32; phy++) { 1364 ctl = tlp_mii_read(l, phy, MII_BMCR); 1365 sts = tlp_mii_read(l, phy, MII_BMSR); 1366 if (ctl != 0xffff && sts != 0xffff) 1367 goto found; 1368 } 1369 printf("MII: no PHY found\n"); 1370 return; 1371 found: 1372 ctl = tlp_mii_read(l, phy, MII_BMCR); 1373 tlp_mii_write(l, phy, MII_BMCR, ctl | BMCR_RESET); 1374 bound = 100; 1375 do { 1376 DELAY(10); 1377 ctl = tlp_mii_read(l, phy, MII_BMCR); 1378 if (ctl == 0xffff) { 1379 printf("MII: PHY %d has died after reset\n", phy); 1380 return; 1381 } 1382 } while (bound-- > 0 && (ctl & BMCR_RESET)); 1383 if (bound == 0) { 1384 printf("PHY %d reset failed\n", phy); 1385 } 1386 ctl &= ~BMCR_ISO; 1387 tlp_mii_write(l, phy, MII_BMCR, ctl); 1388 sts = tlp_mii_read(l, phy, MII_BMSR) | 1389 tlp_mii_read(l, phy, MII_BMSR); /* read twice */ 1390 l->phy = phy; 1391 l->bmsr = sts; 1392 } 1393 1394 static void 1395 mii_dealan(struct local *, u_int timo) 1396 { 1397 uint32_t anar; 1398 u_int bound; 1399 1400 anar = ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA; 1401 tlp_mii_write(l, l->phy, MII_ANAR, anar); 1402 tlp_mii_write(l, l->phy, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 1403 l->anlpar = 0; 1404 bound = getsecs() + timo; 1405 do { 1406 l->bmsr = tlp_mii_read(l, l->phy, MII_BMSR) | 1407 tlp_mii_read(l, l->phy, MII_BMSR); /* read twice */ 1408 if ((l->bmsr & BMSR_LINK) && (l->bmsr & BMSR_ACOMP)) { 1409 l->anlpar = tlp_mii_read(l, l->phy, MII_ANLPAR); 1410 break; 1411 } 1412 DELAY(10 * 1000); 1413 } while (getsecs() < bound); 1414 return; 1415 } 1416 #endif 1417
Indexes created Mon Oct 13 08:09:50 GMT 2025