g2bus_bus_mem.c revision 1.14 1 1.14 martin /* $NetBSD: g2bus_bus_mem.c,v 1.14 2008/04/28 20:23:16 martin Exp $ */
2 1.1 thorpej
3 1.1 thorpej /*-
4 1.1 thorpej * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 1.1 thorpej * All rights reserved.
6 1.1 thorpej *
7 1.1 thorpej * This code is derived from software contributed to The NetBSD Foundation
8 1.1 thorpej * by Jason R. Thorpe.
9 1.1 thorpej *
10 1.1 thorpej * Redistribution and use in source and binary forms, with or without
11 1.1 thorpej * modification, are permitted provided that the following conditions
12 1.1 thorpej * are met:
13 1.1 thorpej * 1. Redistributions of source code must retain the above copyright
14 1.1 thorpej * notice, this list of conditions and the following disclaimer.
15 1.1 thorpej * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 thorpej * notice, this list of conditions and the following disclaimer in the
17 1.1 thorpej * documentation and/or other materials provided with the distribution.
18 1.1 thorpej *
19 1.1 thorpej * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 1.1 thorpej * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 1.1 thorpej * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 1.1 thorpej * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 1.1 thorpej * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 1.1 thorpej * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 1.1 thorpej * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 1.1 thorpej * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 1.1 thorpej * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 1.1 thorpej * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 1.1 thorpej * POSSIBILITY OF SUCH DAMAGE.
30 1.1 thorpej */
31 1.1 thorpej
32 1.1 thorpej /*
33 1.1 thorpej * Bus space implementation for the SEGA G2 bus.
34 1.1 thorpej *
35 1.1 thorpej * NOTE: We only implement a small subset of what the bus_space(9)
36 1.1 thorpej * API specifies. Right now, the GAPS PCI bridge is only used for
37 1.1 thorpej * the Dreamcast Broadband Adatper, so we only provide what the
38 1.1 thorpej * pci(4) and rtk(4) drivers need.
39 1.1 thorpej */
40 1.1 thorpej
41 1.1 thorpej #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
42 1.14 martin __KERNEL_RCSID(0, "$NetBSD: g2bus_bus_mem.c,v 1.14 2008/04/28 20:23:16 martin Exp $");
43 1.1 thorpej
44 1.1 thorpej #include <sys/param.h>
45 1.13 tsutsui #include <sys/systm.h>
46 1.1 thorpej #include <sys/device.h>
47 1.1 thorpej
48 1.13 tsutsui #include <machine/cpu.h>
49 1.1 thorpej #include <machine/bus.h>
50 1.1 thorpej
51 1.1 thorpej #include <dreamcast/dev/g2/g2busvar.h>
52 1.1 thorpej
53 1.1 thorpej int g2bus_bus_mem_map(void *, bus_addr_t, bus_size_t, int,
54 1.1 thorpej bus_space_handle_t *);
55 1.1 thorpej void g2bus_bus_mem_unmap(void *, bus_space_handle_t, bus_size_t);
56 1.1 thorpej
57 1.10 tsutsui uint8_t g2bus_bus_mem_read_1(void *, bus_space_handle_t, bus_size_t);
58 1.10 tsutsui uint16_t g2bus_bus_mem_read_2(void *, bus_space_handle_t, bus_size_t);
59 1.10 tsutsui uint32_t g2bus_bus_mem_read_4(void *, bus_space_handle_t, bus_size_t);
60 1.1 thorpej
61 1.1 thorpej void g2bus_bus_mem_write_1(void *, bus_space_handle_t, bus_size_t,
62 1.10 tsutsui uint8_t);
63 1.1 thorpej void g2bus_bus_mem_write_2(void *, bus_space_handle_t, bus_size_t,
64 1.10 tsutsui uint16_t);
65 1.1 thorpej void g2bus_bus_mem_write_4(void *, bus_space_handle_t, bus_size_t,
66 1.10 tsutsui uint32_t);
67 1.1 thorpej
68 1.3 thorpej void g2bus_bus_mem_read_region_1(void *, bus_space_handle_t, bus_size_t,
69 1.10 tsutsui uint8_t *, bus_size_t);
70 1.9 marcus void g2bus_bus_mem_read_region_2(void *, bus_space_handle_t, bus_size_t,
71 1.10 tsutsui uint16_t *, bus_size_t);
72 1.9 marcus void g2bus_bus_mem_read_region_4(void *, bus_space_handle_t, bus_size_t,
73 1.10 tsutsui uint32_t *, bus_size_t);
74 1.3 thorpej
75 1.3 thorpej void g2bus_bus_mem_write_region_1(void *, bus_space_handle_t, bus_size_t,
76 1.10 tsutsui const uint8_t *, bus_size_t);
77 1.9 marcus void g2bus_bus_mem_write_region_2(void *, bus_space_handle_t, bus_size_t,
78 1.10 tsutsui const uint16_t *, bus_size_t);
79 1.9 marcus void g2bus_bus_mem_write_region_4(void *, bus_space_handle_t, bus_size_t,
80 1.10 tsutsui const uint32_t *, bus_size_t);
81 1.9 marcus
82 1.9 marcus void g2bus_bus_mem_set_region_4(void *, bus_space_handle_t, bus_size_t,
83 1.10 tsutsui uint32_t, bus_size_t);
84 1.3 thorpej
85 1.10 tsutsui uint8_t g2bus_sparse_bus_mem_read_1(void *, bus_space_handle_t, bus_size_t);
86 1.10 tsutsui uint16_t g2bus_sparse_bus_mem_read_2(void *, bus_space_handle_t, bus_size_t);
87 1.10 tsutsui uint32_t g2bus_sparse_bus_mem_read_4(void *, bus_space_handle_t, bus_size_t);
88 1.6 tsutsui
89 1.6 tsutsui void g2bus_sparse_bus_mem_write_1(void *, bus_space_handle_t, bus_size_t,
90 1.10 tsutsui uint8_t);
91 1.6 tsutsui void g2bus_sparse_bus_mem_write_2(void *, bus_space_handle_t, bus_size_t,
92 1.10 tsutsui uint16_t);
93 1.6 tsutsui void g2bus_sparse_bus_mem_write_4(void *, bus_space_handle_t, bus_size_t,
94 1.10 tsutsui uint32_t);
95 1.6 tsutsui
96 1.6 tsutsui void g2bus_sparse_bus_mem_read_region_1(void *, bus_space_handle_t,
97 1.10 tsutsui bus_size_t, uint8_t *, bus_size_t);
98 1.6 tsutsui
99 1.6 tsutsui void g2bus_sparse_bus_mem_write_region_1(void *, bus_space_handle_t,
100 1.10 tsutsui bus_size_t, const uint8_t *, bus_size_t);
101 1.6 tsutsui
102 1.6 tsutsui void g2bus_sparse_bus_mem_read_multi_1(void *, bus_space_handle_t,
103 1.10 tsutsui bus_size_t, uint8_t *, bus_size_t);
104 1.6 tsutsui
105 1.6 tsutsui void g2bus_sparse_bus_mem_write_multi_1(void *, bus_space_handle_t,
106 1.10 tsutsui bus_size_t, const uint8_t *, bus_size_t);
107 1.6 tsutsui
108 1.1 thorpej void
109 1.1 thorpej g2bus_bus_mem_init(struct g2bus_softc *sc)
110 1.1 thorpej {
111 1.1 thorpej bus_space_tag_t t = &sc->sc_memt;
112 1.1 thorpej
113 1.1 thorpej memset(t, 0, sizeof(*t));
114 1.1 thorpej
115 1.1 thorpej t->dbs_map = g2bus_bus_mem_map;
116 1.1 thorpej t->dbs_unmap = g2bus_bus_mem_unmap;
117 1.1 thorpej
118 1.1 thorpej t->dbs_r_1 = g2bus_bus_mem_read_1;
119 1.1 thorpej t->dbs_r_2 = g2bus_bus_mem_read_2;
120 1.1 thorpej t->dbs_r_4 = g2bus_bus_mem_read_4;
121 1.1 thorpej
122 1.1 thorpej t->dbs_w_1 = g2bus_bus_mem_write_1;
123 1.1 thorpej t->dbs_w_2 = g2bus_bus_mem_write_2;
124 1.1 thorpej t->dbs_w_4 = g2bus_bus_mem_write_4;
125 1.3 thorpej
126 1.3 thorpej t->dbs_rr_1 = g2bus_bus_mem_read_region_1;
127 1.9 marcus t->dbs_rr_2 = g2bus_bus_mem_read_region_2;
128 1.9 marcus t->dbs_rr_4 = g2bus_bus_mem_read_region_4;
129 1.3 thorpej
130 1.3 thorpej t->dbs_wr_1 = g2bus_bus_mem_write_region_1;
131 1.9 marcus t->dbs_wr_2 = g2bus_bus_mem_write_region_2;
132 1.9 marcus t->dbs_wr_4 = g2bus_bus_mem_write_region_4;
133 1.9 marcus
134 1.9 marcus t->dbs_sr_4 = g2bus_bus_mem_set_region_4;
135 1.1 thorpej }
136 1.1 thorpej
137 1.1 thorpej int
138 1.1 thorpej g2bus_bus_mem_map(void *v, bus_addr_t addr, bus_size_t size, int flags,
139 1.1 thorpej bus_space_handle_t *shp)
140 1.1 thorpej {
141 1.1 thorpej
142 1.1 thorpej KASSERT((addr & SH3_PHYS_MASK) == addr);
143 1.1 thorpej *shp = SH3_PHYS_TO_P2SEG(addr);
144 1.1 thorpej
145 1.10 tsutsui return 0;
146 1.1 thorpej }
147 1.1 thorpej
148 1.1 thorpej void
149 1.1 thorpej g2bus_bus_mem_unmap(void *v, bus_space_handle_t sh, bus_size_t size)
150 1.1 thorpej {
151 1.1 thorpej
152 1.1 thorpej KASSERT(sh >= SH3_P2SEG_BASE && sh <= SH3_P2SEG_END);
153 1.1 thorpej /* Nothing to do. */
154 1.1 thorpej }
155 1.1 thorpej
156 1.1 thorpej /*
157 1.2 marcus * G2 bus cycles must not be interrupted by IRQs or G2 DMA.
158 1.2 marcus * The following paired macros will take the necessary precautions.
159 1.1 thorpej */
160 1.1 thorpej
161 1.7 tsutsui #define G2LOCK_DECL \
162 1.7 tsutsui int __s
163 1.7 tsutsui
164 1.7 tsutsui #define G2_LOCK() \
165 1.2 marcus do { \
166 1.7 tsutsui __s = _cpu_intr_suspend(); \
167 1.2 marcus /* suspend any G2 DMA here... */ \
168 1.12 perry while ((*(volatile uint32_t *)0xa05f688c) & 0x20) \
169 1.7 tsutsui ; \
170 1.7 tsutsui } while (/*CONSTCOND*/0)
171 1.2 marcus
172 1.7 tsutsui #define G2_UNLOCK() \
173 1.2 marcus do { \
174 1.2 marcus /* resume any G2 DMA here... */ \
175 1.7 tsutsui _cpu_intr_resume(__s); \
176 1.7 tsutsui } while (/*CONSTCOND*/0)
177 1.2 marcus
178 1.10 tsutsui uint8_t
179 1.1 thorpej g2bus_bus_mem_read_1(void *v, bus_space_handle_t sh, bus_size_t off)
180 1.1 thorpej {
181 1.7 tsutsui G2LOCK_DECL;
182 1.10 tsutsui uint8_t rv;
183 1.1 thorpej
184 1.7 tsutsui G2_LOCK();
185 1.2 marcus
186 1.12 perry rv = *(volatile uint8_t *)(sh + off);
187 1.1 thorpej
188 1.7 tsutsui G2_UNLOCK();
189 1.2 marcus
190 1.10 tsutsui return rv;
191 1.1 thorpej }
192 1.1 thorpej
193 1.10 tsutsui uint16_t
194 1.1 thorpej g2bus_bus_mem_read_2(void *v, bus_space_handle_t sh, bus_size_t off)
195 1.1 thorpej {
196 1.7 tsutsui G2LOCK_DECL;
197 1.10 tsutsui uint16_t rv;
198 1.1 thorpej
199 1.7 tsutsui G2_LOCK();
200 1.2 marcus
201 1.12 perry rv = *(volatile uint16_t *)(sh + off);
202 1.1 thorpej
203 1.7 tsutsui G2_UNLOCK();
204 1.2 marcus
205 1.10 tsutsui return rv;
206 1.1 thorpej }
207 1.1 thorpej
208 1.10 tsutsui uint32_t
209 1.1 thorpej g2bus_bus_mem_read_4(void *v, bus_space_handle_t sh, bus_size_t off)
210 1.1 thorpej {
211 1.7 tsutsui G2LOCK_DECL;
212 1.10 tsutsui uint32_t rv;
213 1.1 thorpej
214 1.7 tsutsui G2_LOCK();
215 1.2 marcus
216 1.12 perry rv = *(volatile uint32_t *)(sh + off);
217 1.1 thorpej
218 1.7 tsutsui G2_UNLOCK();
219 1.2 marcus
220 1.10 tsutsui return rv;
221 1.1 thorpej }
222 1.1 thorpej
223 1.1 thorpej void
224 1.1 thorpej g2bus_bus_mem_write_1(void *v, bus_space_handle_t sh, bus_size_t off,
225 1.10 tsutsui uint8_t val)
226 1.1 thorpej {
227 1.7 tsutsui G2LOCK_DECL;
228 1.1 thorpej
229 1.7 tsutsui G2_LOCK();
230 1.2 marcus
231 1.12 perry *(volatile uint8_t *)(sh + off) = val;
232 1.2 marcus
233 1.7 tsutsui G2_UNLOCK();
234 1.1 thorpej }
235 1.1 thorpej
236 1.1 thorpej void
237 1.1 thorpej g2bus_bus_mem_write_2(void *v, bus_space_handle_t sh, bus_size_t off,
238 1.10 tsutsui uint16_t val)
239 1.1 thorpej {
240 1.7 tsutsui G2LOCK_DECL;
241 1.1 thorpej
242 1.7 tsutsui G2_LOCK();
243 1.2 marcus
244 1.12 perry *(volatile uint16_t *)(sh + off) = val;
245 1.2 marcus
246 1.7 tsutsui G2_UNLOCK();
247 1.1 thorpej }
248 1.1 thorpej
249 1.1 thorpej void
250 1.1 thorpej g2bus_bus_mem_write_4(void *v, bus_space_handle_t sh, bus_size_t off,
251 1.10 tsutsui uint32_t val)
252 1.1 thorpej {
253 1.7 tsutsui G2LOCK_DECL;
254 1.1 thorpej
255 1.7 tsutsui G2_LOCK();
256 1.2 marcus
257 1.12 perry *(volatile uint32_t *)(sh + off) = val;
258 1.3 thorpej
259 1.7 tsutsui G2_UNLOCK();
260 1.3 thorpej }
261 1.3 thorpej
262 1.3 thorpej void
263 1.3 thorpej g2bus_bus_mem_read_region_1(void *v, bus_space_handle_t sh, bus_size_t off,
264 1.10 tsutsui uint8_t *addr, bus_size_t len)
265 1.3 thorpej {
266 1.7 tsutsui G2LOCK_DECL;
267 1.12 perry volatile const uint8_t *baddr = (uint8_t *)(sh + off);
268 1.3 thorpej
269 1.7 tsutsui G2_LOCK();
270 1.3 thorpej
271 1.3 thorpej while (len--)
272 1.3 thorpej *addr++ = *baddr++;
273 1.3 thorpej
274 1.7 tsutsui G2_UNLOCK();
275 1.3 thorpej }
276 1.3 thorpej
277 1.3 thorpej void
278 1.9 marcus g2bus_bus_mem_read_region_2(void *v, bus_space_handle_t sh, bus_size_t off,
279 1.10 tsutsui uint16_t *addr, bus_size_t len)
280 1.9 marcus {
281 1.9 marcus G2LOCK_DECL;
282 1.12 perry volatile const uint16_t *baddr = (uint16_t *)(sh + off);
283 1.9 marcus
284 1.9 marcus G2_LOCK();
285 1.9 marcus
286 1.9 marcus while (len--)
287 1.9 marcus *addr++ = *baddr++;
288 1.9 marcus
289 1.9 marcus G2_UNLOCK();
290 1.9 marcus }
291 1.9 marcus
292 1.9 marcus void
293 1.9 marcus g2bus_bus_mem_read_region_4(void *v, bus_space_handle_t sh, bus_size_t off,
294 1.10 tsutsui uint32_t *addr, bus_size_t len)
295 1.9 marcus {
296 1.9 marcus G2LOCK_DECL;
297 1.12 perry volatile const uint32_t *baddr = (uint32_t *)(sh + off);
298 1.9 marcus
299 1.9 marcus G2_LOCK();
300 1.9 marcus
301 1.9 marcus while (len--)
302 1.9 marcus *addr++ = *baddr++;
303 1.9 marcus
304 1.9 marcus G2_UNLOCK();
305 1.9 marcus }
306 1.9 marcus
307 1.9 marcus void
308 1.3 thorpej g2bus_bus_mem_write_region_1(void *v, bus_space_handle_t sh, bus_size_t off,
309 1.10 tsutsui const uint8_t *addr, bus_size_t len)
310 1.3 thorpej {
311 1.7 tsutsui G2LOCK_DECL;
312 1.12 perry volatile uint8_t *baddr = (uint8_t *)(sh + off);
313 1.3 thorpej
314 1.7 tsutsui G2_LOCK();
315 1.3 thorpej
316 1.3 thorpej while (len--)
317 1.3 thorpej *baddr++ = *addr++;
318 1.9 marcus
319 1.9 marcus G2_UNLOCK();
320 1.9 marcus }
321 1.9 marcus
322 1.9 marcus void
323 1.9 marcus g2bus_bus_mem_write_region_2(void *v, bus_space_handle_t sh, bus_size_t off,
324 1.10 tsutsui const uint16_t *addr, bus_size_t len)
325 1.9 marcus {
326 1.9 marcus G2LOCK_DECL;
327 1.12 perry volatile uint16_t *baddr = (uint16_t *)(sh + off);
328 1.9 marcus
329 1.9 marcus G2_LOCK();
330 1.9 marcus
331 1.9 marcus while (len--)
332 1.9 marcus *baddr++ = *addr++;
333 1.9 marcus
334 1.9 marcus G2_UNLOCK();
335 1.9 marcus }
336 1.9 marcus
337 1.9 marcus void
338 1.9 marcus g2bus_bus_mem_write_region_4(void *v, bus_space_handle_t sh, bus_size_t off,
339 1.10 tsutsui const uint32_t *addr, bus_size_t len)
340 1.9 marcus {
341 1.9 marcus G2LOCK_DECL;
342 1.12 perry volatile uint32_t *baddr = (uint32_t *)(sh + off);
343 1.9 marcus
344 1.9 marcus G2_LOCK();
345 1.9 marcus
346 1.9 marcus while (len--)
347 1.9 marcus *baddr++ = *addr++;
348 1.9 marcus
349 1.9 marcus G2_UNLOCK();
350 1.9 marcus }
351 1.9 marcus
352 1.9 marcus void
353 1.9 marcus g2bus_bus_mem_set_region_4(void *v, bus_space_handle_t sh, bus_size_t off,
354 1.10 tsutsui uint32_t val, bus_size_t len)
355 1.9 marcus {
356 1.9 marcus G2LOCK_DECL;
357 1.12 perry volatile uint32_t *baddr = (uint32_t *)(sh + off);
358 1.9 marcus
359 1.9 marcus G2_LOCK();
360 1.9 marcus
361 1.9 marcus while (len--)
362 1.9 marcus *baddr++ = val;
363 1.6 tsutsui
364 1.7 tsutsui G2_UNLOCK();
365 1.6 tsutsui }
366 1.6 tsutsui
367 1.6 tsutsui void
368 1.6 tsutsui g2bus_set_bus_mem_sparse(bus_space_tag_t memt)
369 1.6 tsutsui {
370 1.6 tsutsui
371 1.6 tsutsui memt->dbs_r_1 = g2bus_sparse_bus_mem_read_1;
372 1.6 tsutsui memt->dbs_r_2 = g2bus_sparse_bus_mem_read_2;
373 1.6 tsutsui memt->dbs_r_4 = g2bus_sparse_bus_mem_read_4;
374 1.6 tsutsui
375 1.6 tsutsui memt->dbs_w_1 = g2bus_sparse_bus_mem_write_1;
376 1.6 tsutsui memt->dbs_w_2 = g2bus_sparse_bus_mem_write_2;
377 1.6 tsutsui memt->dbs_w_4 = g2bus_sparse_bus_mem_write_4;
378 1.6 tsutsui
379 1.6 tsutsui memt->dbs_rr_1 = g2bus_sparse_bus_mem_read_region_1;
380 1.6 tsutsui
381 1.6 tsutsui memt->dbs_wr_1 = g2bus_sparse_bus_mem_write_region_1;
382 1.6 tsutsui
383 1.6 tsutsui memt->dbs_rm_1 = g2bus_sparse_bus_mem_read_multi_1;
384 1.6 tsutsui
385 1.6 tsutsui memt->dbs_wm_1 = g2bus_sparse_bus_mem_write_multi_1;
386 1.6 tsutsui }
387 1.6 tsutsui
388 1.10 tsutsui uint8_t
389 1.6 tsutsui g2bus_sparse_bus_mem_read_1(void *v, bus_space_handle_t sh, bus_size_t off)
390 1.6 tsutsui {
391 1.7 tsutsui G2LOCK_DECL;
392 1.10 tsutsui uint8_t rv;
393 1.6 tsutsui
394 1.7 tsutsui G2_LOCK();
395 1.6 tsutsui
396 1.12 perry rv = *(volatile uint8_t *)(sh + (off * 4));
397 1.6 tsutsui
398 1.7 tsutsui G2_UNLOCK();
399 1.6 tsutsui
400 1.10 tsutsui return rv;
401 1.6 tsutsui }
402 1.6 tsutsui
403 1.10 tsutsui uint16_t
404 1.6 tsutsui g2bus_sparse_bus_mem_read_2(void *v, bus_space_handle_t sh, bus_size_t off)
405 1.6 tsutsui {
406 1.7 tsutsui G2LOCK_DECL;
407 1.10 tsutsui uint16_t rv;
408 1.6 tsutsui
409 1.7 tsutsui G2_LOCK();
410 1.6 tsutsui
411 1.12 perry rv = *(volatile uint16_t *)(sh + (off * 4));
412 1.6 tsutsui
413 1.7 tsutsui G2_UNLOCK();
414 1.6 tsutsui
415 1.10 tsutsui return rv;
416 1.6 tsutsui }
417 1.6 tsutsui
418 1.10 tsutsui uint32_t
419 1.6 tsutsui g2bus_sparse_bus_mem_read_4(void *v, bus_space_handle_t sh, bus_size_t off)
420 1.6 tsutsui {
421 1.7 tsutsui G2LOCK_DECL;
422 1.10 tsutsui uint32_t rv;
423 1.6 tsutsui
424 1.7 tsutsui G2_LOCK();
425 1.6 tsutsui
426 1.12 perry rv = *(volatile uint32_t *)(sh + (off * 4));
427 1.6 tsutsui
428 1.7 tsutsui G2_UNLOCK();
429 1.6 tsutsui
430 1.10 tsutsui return rv;
431 1.6 tsutsui }
432 1.6 tsutsui
433 1.6 tsutsui void
434 1.6 tsutsui g2bus_sparse_bus_mem_write_1(void *v, bus_space_handle_t sh, bus_size_t off,
435 1.10 tsutsui uint8_t val)
436 1.6 tsutsui {
437 1.7 tsutsui G2LOCK_DECL;
438 1.6 tsutsui
439 1.7 tsutsui G2_LOCK();
440 1.6 tsutsui
441 1.12 perry *(volatile uint8_t *)(sh + (off * 4)) = val;
442 1.6 tsutsui
443 1.7 tsutsui G2_UNLOCK();
444 1.6 tsutsui }
445 1.6 tsutsui
446 1.6 tsutsui void
447 1.6 tsutsui g2bus_sparse_bus_mem_write_2(void *v, bus_space_handle_t sh, bus_size_t off,
448 1.10 tsutsui uint16_t val)
449 1.6 tsutsui {
450 1.7 tsutsui G2LOCK_DECL;
451 1.6 tsutsui
452 1.7 tsutsui G2_LOCK();
453 1.6 tsutsui
454 1.12 perry *(volatile uint16_t *)(sh + (off * 4)) = val;
455 1.6 tsutsui
456 1.7 tsutsui G2_UNLOCK();
457 1.6 tsutsui }
458 1.6 tsutsui
459 1.6 tsutsui void
460 1.6 tsutsui g2bus_sparse_bus_mem_write_4(void *v, bus_space_handle_t sh, bus_size_t off,
461 1.10 tsutsui uint32_t val)
462 1.6 tsutsui {
463 1.7 tsutsui G2LOCK_DECL;
464 1.6 tsutsui
465 1.7 tsutsui G2_LOCK();
466 1.6 tsutsui
467 1.12 perry *(volatile uint32_t *)(sh + (off * 4)) = val;
468 1.6 tsutsui
469 1.7 tsutsui G2_UNLOCK();
470 1.6 tsutsui }
471 1.6 tsutsui
472 1.6 tsutsui void
473 1.6 tsutsui g2bus_sparse_bus_mem_read_region_1(void *v, bus_space_handle_t sh,
474 1.10 tsutsui bus_size_t off, uint8_t *addr, bus_size_t len)
475 1.6 tsutsui {
476 1.7 tsutsui G2LOCK_DECL;
477 1.12 perry volatile const uint8_t *baddr = (uint8_t *)(sh + (off * 4));
478 1.6 tsutsui
479 1.7 tsutsui G2_LOCK();
480 1.6 tsutsui
481 1.6 tsutsui while (len--) {
482 1.6 tsutsui *addr++ = *baddr;
483 1.6 tsutsui baddr += 4;
484 1.6 tsutsui }
485 1.6 tsutsui
486 1.7 tsutsui G2_UNLOCK();
487 1.6 tsutsui }
488 1.6 tsutsui
489 1.6 tsutsui void
490 1.6 tsutsui g2bus_sparse_bus_mem_write_region_1(void *v, bus_space_handle_t sh,
491 1.10 tsutsui bus_size_t off, const uint8_t *addr, bus_size_t len)
492 1.6 tsutsui {
493 1.7 tsutsui G2LOCK_DECL;
494 1.12 perry volatile uint8_t *baddr = (uint8_t *)(sh + (off * 4));
495 1.6 tsutsui
496 1.7 tsutsui G2_LOCK();
497 1.6 tsutsui
498 1.6 tsutsui while (len--) {
499 1.6 tsutsui *baddr = *addr++;
500 1.6 tsutsui baddr += 4;
501 1.6 tsutsui }
502 1.6 tsutsui
503 1.7 tsutsui G2_UNLOCK();
504 1.6 tsutsui }
505 1.6 tsutsui
506 1.6 tsutsui void
507 1.6 tsutsui g2bus_sparse_bus_mem_read_multi_1(void *v, bus_space_handle_t sh,
508 1.10 tsutsui bus_size_t off, uint8_t *addr, bus_size_t len)
509 1.6 tsutsui {
510 1.7 tsutsui G2LOCK_DECL;
511 1.12 perry volatile const uint8_t *baddr = (uint8_t *)(sh + (off * 4));
512 1.6 tsutsui
513 1.7 tsutsui G2_LOCK();
514 1.6 tsutsui
515 1.6 tsutsui while (len--)
516 1.6 tsutsui *addr++ = *baddr;
517 1.6 tsutsui
518 1.7 tsutsui G2_UNLOCK();
519 1.6 tsutsui }
520 1.6 tsutsui
521 1.6 tsutsui void
522 1.6 tsutsui g2bus_sparse_bus_mem_write_multi_1(void *v, bus_space_handle_t sh,
523 1.10 tsutsui bus_size_t off, const uint8_t *addr, bus_size_t len)
524 1.6 tsutsui {
525 1.7 tsutsui G2LOCK_DECL;
526 1.12 perry volatile uint8_t *baddr = (uint8_t *)(sh + (off * 4));
527 1.6 tsutsui
528 1.7 tsutsui G2_LOCK();
529 1.6 tsutsui
530 1.6 tsutsui while (len--)
531 1.6 tsutsui *baddr = *addr++;
532 1.2 marcus
533 1.7 tsutsui G2_UNLOCK();
534 1.1 thorpej }
535