bus.h revision 1.4.4.1
1 /* $NetBSD: bus.h,v 1.4.4.1 2021/04/03 22:28:21 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #ifndef _EMIPS_BUS_H_ 34 #define _EMIPS_BUS_H_ 35 36 #include <mips/locore.h> 37 38 /* 39 * Utility macros; do not use outside this file. 40 */ 41 #define __PB_TYPENAME_PREFIX(BITS) ___CONCAT(u_int,BITS) 42 #define __PB_TYPENAME(BITS) ___CONCAT(__PB_TYPENAME_PREFIX(BITS),_t) 43 44 /* 45 * Bus address and size types 46 */ 47 typedef u_long bus_addr_t; 48 typedef u_long bus_size_t; 49 50 #define PRIxBUSADDR "lx" 51 #define PRIxBUSSIZE "lx" 52 #define PRIuBUSSIZE "lu" 53 /* 54 * Access methods for bus resources and address space. 55 */ 56 typedef int bus_space_tag_t; 57 typedef u_long bus_space_handle_t; 58 59 #define PRIxBSH "lx" 60 61 /* 62 * int bus_space_map(bus_space_tag_t t, bus_addr_t addr, 63 * bus_size_t size, int flags, bus_space_handle_t *bshp); 64 * 65 * Map a region of bus space. 66 */ 67 68 #define BUS_SPACE_MAP_CACHEABLE 0x01 69 #define BUS_SPACE_MAP_LINEAR 0x02 70 #define BUS_SPACE_MAP_PREFETCHABLE 0x04 71 72 int bus_space_map(bus_space_tag_t, bus_addr_t, bus_size_t, 73 int, bus_space_handle_t *); 74 75 /* 76 * void bus_space_unmap(bus_space_tag_t t, 77 * bus_space_handle_t bsh, bus_size_t size); 78 * 79 * Unmap a region of bus space. 80 */ 81 82 void bus_space_unmap(bus_space_tag_t, bus_space_handle_t, bus_size_t); 83 84 /* 85 * int bus_space_subregion(bus_space_tag_t t, 86 * bus_space_handle_t bsh, bus_size_t offset, bus_size_t size, 87 * bus_space_handle_t *nbshp); 88 * 89 * Get a new handle for a subregion of an already-mapped area of bus space. 90 */ 91 92 int bus_space_subregion(bus_space_tag_t t, bus_space_handle_t bsh, 93 bus_size_t offset, bus_size_t size, bus_space_handle_t *nbshp); 94 95 /* 96 * int bus_space_alloc(bus_space_tag_t t, bus_addr_t, rstart, 97 * bus_addr_t rend, bus_size_t size, bus_size_t align, 98 * bus_size_t boundary, int flags, bus_addr_t *addrp, 99 * bus_space_handle_t *bshp); 100 * 101 * Allocate a region of bus space. 102 */ 103 104 int bus_space_alloc(bus_space_tag_t t, bus_addr_t rstart, 105 bus_addr_t rend, bus_size_t size, bus_size_t align, 106 bus_size_t boundary, int cacheable, bus_addr_t *addrp, 107 bus_space_handle_t *bshp); 108 109 /* 110 * int bus_space_free(bus_space_tag_t t, 111 * bus_space_handle_t bsh, bus_size_t size); 112 * 113 * Free a region of bus space. 114 */ 115 116 void bus_space_free(bus_space_tag_t t, bus_space_handle_t bsh, 117 bus_size_t size); 118 119 /* 120 * void *bus_space_vaddr(bus_space_tag_t, bus_space_handle_t); 121 * 122 * Get the kernel virtual address for the mapped bus space. 123 * Only allowed for regions mapped with BUS_SPACE_MAP_LINEAR. 124 * (XXX not enforced) 125 */ 126 #define bus_space_vaddr(t, h) \ 127 ((void *)(h)) 128 129 /* 130 * u_intN_t bus_space_read_N(bus_space_tag_t tag, 131 * bus_space_handle_t bsh, bus_size_t offset); 132 * 133 * Read a 1, 2, 4, or 8 byte quantity from bus space 134 * described by tag/handle/offset. 135 */ 136 137 #define bus_space_read_1(t, h, o) \ 138 ((void) t, (*(volatile u_int8_t *)((h) + (o)))) 139 140 #define bus_space_read_2(t, h, o) \ 141 ((void) t, (*(volatile u_int16_t *)((h) + (o)))) 142 143 #define bus_space_read_4(t, h, o) \ 144 ((void) t, (*(volatile u_int32_t *)((h) + (o)))) 145 146 /* 147 * void bus_space_read_multi_N(bus_space_tag_t tag, 148 * bus_space_handle_t bsh, bus_size_t offset, 149 * u_intN_t *addr, size_t count); 150 * 151 * Read `count' 1, 2, 4, or 8 byte quantities from bus space 152 * described by tag/handle/offset and copy into buffer provided. 153 */ 154 155 #define __EMIPS_bus_space_read_multi(BYTES,BITS) \ 156 static __inline void __CONCAT(bus_space_read_multi_,BYTES) \ 157 (bus_space_tag_t, bus_space_handle_t, bus_size_t, \ 158 __PB_TYPENAME(BITS) *, size_t); \ 159 \ 160 static __inline void \ 161 __CONCAT(bus_space_read_multi_,BYTES)( \ 162 bus_space_tag_t t, \ 163 bus_space_handle_t h, \ 164 bus_size_t o, \ 165 __PB_TYPENAME(BITS) *a, \ 166 size_t c) \ 167 { \ 168 \ 169 while (c--) \ 170 *a++ = __CONCAT(bus_space_read_,BYTES)(t, h, o); \ 171 } 172 173 __EMIPS_bus_space_read_multi(1,8) 174 __EMIPS_bus_space_read_multi(2,16) 175 __EMIPS_bus_space_read_multi(4,32) 176 177 #undef __EMIPS_bus_space_read_multi 178 179 /* 180 * void bus_space_read_region_N(bus_space_tag_t tag, 181 * bus_space_handle_t bsh, bus_size_t offset, 182 * u_intN_t *addr, size_t count); 183 * 184 * Read `count' 1, 2, 4, or 8 byte quantities from bus space 185 * described by tag/handle and starting at `offset' and copy into 186 * buffer provided. 187 */ 188 189 #define __EMIPS_bus_space_read_region(BYTES,BITS) \ 190 static __inline void __CONCAT(bus_space_read_region_,BYTES) \ 191 (bus_space_tag_t, bus_space_handle_t, bus_size_t, \ 192 __PB_TYPENAME(BITS) *, size_t); \ 193 \ 194 static __inline void \ 195 __CONCAT(bus_space_read_region_,BYTES)( \ 196 bus_space_tag_t t, \ 197 bus_space_handle_t h, \ 198 bus_size_t o, \ 199 __PB_TYPENAME(BITS) *a, \ 200 size_t c) \ 201 { \ 202 \ 203 while (c--) { \ 204 *a++ = __CONCAT(bus_space_read_,BYTES)(t, h, o); \ 205 o += BYTES; \ 206 } \ 207 } 208 209 __EMIPS_bus_space_read_region(1,8) 210 __EMIPS_bus_space_read_region(2,16) 211 __EMIPS_bus_space_read_region(4,32) 212 213 #undef __EMIPS_bus_space_read_region 214 215 /* 216 * void bus_space_write_N(bus_space_tag_t tag, 217 * bus_space_handle_t bsh, bus_size_t offset, 218 * u_intN_t value); 219 * 220 * Write the 1, 2, 4, or 8 byte value `value' to bus space 221 * described by tag/handle/offset. 222 */ 223 224 #define bus_space_write_1(t, h, o, v) \ 225 do { \ 226 (void) t; \ 227 *(volatile u_int8_t *)((h) + (o)) = (v); \ 228 wbflush(); /* XXX */ \ 229 } while (0) 230 231 #define bus_space_write_2(t, h, o, v) \ 232 do { \ 233 (void) t; \ 234 *(volatile u_int16_t *)((h) + (o)) = (v); \ 235 wbflush(); /* XXX */ \ 236 } while (0) 237 238 #define bus_space_write_4(t, h, o, v) \ 239 do { \ 240 (void) t; \ 241 *(volatile u_int32_t *)((h) + (o)) = (v); \ 242 wbflush(); /* XXX */ \ 243 } while (0) 244 245 /* 246 * void bus_space_write_multi_N(bus_space_tag_t tag, 247 * bus_space_handle_t bsh, bus_size_t offset, 248 * const u_intN_t *addr, size_t count); 249 * 250 * Write `count' 1, 2, 4, or 8 byte quantities from the buffer 251 * provided to bus space described by tag/handle/offset. 252 */ 253 254 #define __EMIPS_bus_space_write_multi(BYTES,BITS) \ 255 static __inline void __CONCAT(bus_space_write_multi_,BYTES) \ 256 (bus_space_tag_t, bus_space_handle_t, bus_size_t, \ 257 __PB_TYPENAME(BITS) *, size_t); \ 258 \ 259 static __inline void \ 260 __CONCAT(bus_space_write_multi_,BYTES)( \ 261 bus_space_tag_t t, \ 262 bus_space_handle_t h, \ 263 bus_size_t o, \ 264 __PB_TYPENAME(BITS) *a, \ 265 size_t c) \ 266 { \ 267 \ 268 while (c--) \ 269 __CONCAT(bus_space_write_,BYTES)(t, h, o, *a++); \ 270 } 271 272 __EMIPS_bus_space_write_multi(1,8) 273 __EMIPS_bus_space_write_multi(2,16) 274 __EMIPS_bus_space_write_multi(4,32) 275 276 #undef __EMIPS_bus_space_write_multi 277 278 /* 279 * void bus_space_write_region_N(bus_space_tag_t tag, 280 * bus_space_handle_t bsh, bus_size_t offset, 281 * const u_intN_t *addr, size_t count); 282 * 283 * Write `count' 1, 2, 4, or 8 byte quantities from the buffer provided 284 * to bus space described by tag/handle starting at `offset'. 285 */ 286 287 #define __EMIPS_bus_space_write_region(BYTES,BITS) \ 288 static __inline void __CONCAT(bus_space_write_region_,BYTES) \ 289 (bus_space_tag_t, bus_space_handle_t, bus_size_t, \ 290 __PB_TYPENAME(BITS) *, size_t); \ 291 \ 292 static __inline void \ 293 __CONCAT(bus_space_write_region_,BYTES)( \ 294 bus_space_tag_t t, \ 295 bus_space_handle_t h, \ 296 bus_size_t o, \ 297 __PB_TYPENAME(BITS) *a, \ 298 size_t c) \ 299 { \ 300 \ 301 while (c--) { \ 302 __CONCAT(bus_space_write_,BYTES)(t, h, o, *a++); \ 303 o += BYTES; \ 304 } \ 305 } 306 307 __EMIPS_bus_space_write_region(1,8) 308 __EMIPS_bus_space_write_region(2,16) 309 __EMIPS_bus_space_write_region(4,32) 310 311 #undef __EMIPS_bus_space_write_region 312 313 /* 314 * void bus_space_set_multi_N(bus_space_tag_t tag, 315 * bus_space_handle_t bsh, bus_size_t offset, u_intN_t val, 316 * size_t count); 317 * 318 * Write the 1, 2, 4, or 8 byte value `val' to bus space described 319 * by tag/handle/offset `count' times. 320 */ 321 322 #define __EMIPS_bus_space_set_multi(BYTES,BITS) \ 323 static __inline void __CONCAT(bus_space_set_multi_,BYTES) \ 324 (bus_space_tag_t, bus_space_handle_t, bus_size_t, \ 325 __PB_TYPENAME(BITS), size_t); \ 326 \ 327 static __inline void \ 328 __CONCAT(bus_space_set_multi_,BYTES)( \ 329 bus_space_tag_t t, \ 330 bus_space_handle_t h, \ 331 bus_size_t o, \ 332 __PB_TYPENAME(BITS) v, \ 333 size_t c) \ 334 { \ 335 \ 336 while (c--) \ 337 __CONCAT(bus_space_write_,BYTES)(t, h, o, v); \ 338 } 339 340 __EMIPS_bus_space_set_multi(1,8) 341 __EMIPS_bus_space_set_multi(2,16) 342 __EMIPS_bus_space_set_multi(4,32) 343 344 #undef __EMIPS_bus_space_set_multi 345 346 /* 347 * void bus_space_set_region_N(bus_space_tag_t tag, 348 * bus_space_handle_t bsh, bus_size_t offset, u_intN_t val, 349 * size_t count); 350 * 351 * Write `count' 1, 2, 4, or 8 byte value `val' to bus space described 352 * by tag/handle starting at `offset'. 353 */ 354 355 #define __EMIPS_bus_space_set_region(BYTES,BITS) \ 356 static __inline void __CONCAT(bus_space_set_region_,BYTES) \ 357 (bus_space_tag_t, bus_space_handle_t, bus_size_t, \ 358 __PB_TYPENAME(BITS), size_t); \ 359 \ 360 static __inline void \ 361 __CONCAT(bus_space_set_region_,BYTES)( \ 362 bus_space_tag_t t, \ 363 bus_space_handle_t h, \ 364 bus_size_t o, \ 365 __PB_TYPENAME(BITS) v, \ 366 size_t c) \ 367 { \ 368 \ 369 while (c--) { \ 370 __CONCAT(bus_space_write_,BYTES)(t, h, o, v); \ 371 o += BYTES; \ 372 } \ 373 } 374 375 __EMIPS_bus_space_set_region(1,8) 376 __EMIPS_bus_space_set_region(2,16) 377 __EMIPS_bus_space_set_region(4,32) 378 379 #undef __EMIPS_bus_space_set_region 380 381 /* 382 * void bus_space_copy_region_N(bus_space_tag_t tag, 383 * bus_space_handle_t bsh1, bus_size_t off1, 384 * bus_space_handle_t bsh2, bus_size_t off2, 385 * bus_size_t count); 386 * 387 * Copy `count' 1, 2, 4, or 8 byte values from bus space starting 388 * at tag/bsh1/off1 to bus space starting at tag/bsh2/off2. 389 */ 390 391 #define __EMIPS_copy_region(BYTES) \ 392 static __inline void __CONCAT(bus_space_copy_region_,BYTES) \ 393 (bus_space_tag_t, \ 394 bus_space_handle_t bsh1, bus_size_t off1, \ 395 bus_space_handle_t bsh2, bus_size_t off2, \ 396 bus_size_t count); \ 397 \ 398 static __inline void \ 399 __CONCAT(bus_space_copy_region_,BYTES)( \ 400 bus_space_tag_t t, \ 401 bus_space_handle_t h1, \ 402 bus_size_t o1, \ 403 bus_space_handle_t h2, \ 404 bus_size_t o2, \ 405 bus_size_t c) \ 406 { \ 407 bus_size_t o; \ 408 \ 409 if ((h1 + o1) >= (h2 + o2)) { \ 410 /* src after dest: copy forward */ \ 411 for (o = 0; c != 0; c--, o += BYTES) \ 412 __CONCAT(bus_space_write_,BYTES)(t, h2, o2 + o, \ 413 __CONCAT(bus_space_read_,BYTES)(t, h1, o1 + o)); \ 414 } else { \ 415 /* dest after src: copy backwards */ \ 416 for (o = (c - 1) * BYTES; c != 0; c--, o -= BYTES) \ 417 __CONCAT(bus_space_write_,BYTES)(t, h2, o2 + o, \ 418 __CONCAT(bus_space_read_,BYTES)(t, h1, o1 + o)); \ 419 } \ 420 } 421 422 __EMIPS_copy_region(1) 423 __EMIPS_copy_region(2) 424 __EMIPS_copy_region(4) 425 426 #undef __EMIPS_copy_region 427 428 /* 429 * Bus read/write barrier methods. 430 * 431 * void bus_space_barrier(bus_space_tag_t tag, 432 * bus_space_handle_t bsh, bus_size_t offset, 433 * bus_size_t len, int flags); 434 * 435 * On the MIPS, we just flush the write buffer. 436 */ 437 #define bus_space_barrier(t, h, o, l, f) \ 438 ((void)((void)(t), (void)(h), (void)(o), (void)(l), (void)(f), \ 439 wbflush())) 440 #define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */ 441 #define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */ 442 443 #undef __PB_TYPENAME_PREFIX 444 #undef __PB_TYPENAME 445 446 #define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t) 447 448 /* 449 * Flags used in various bus DMA methods. 450 */ 451 #define BUS_DMA_WAITOK 0x000 /* safe to sleep (pseudo-flag) */ 452 #define BUS_DMA_NOWAIT 0x001 /* not safe to sleep */ 453 #define BUS_DMA_ALLOCNOW 0x002 /* perform resource allocation now */ 454 #define BUS_DMA_COHERENT 0x004 /* hint: map memory DMA coherent */ 455 #define BUS_DMA_STREAMING 0x008 /* hint: sequential, unidirectional */ 456 #define BUS_DMA_BUS1 0x010 /* placeholders for bus functions... */ 457 #define BUS_DMA_BUS2 0x020 458 #define BUS_DMA_BUS3 0x040 459 #define BUS_DMA_BUS4 0x080 460 #define BUS_DMA_READ 0x100 /* mapping is device -> memory only */ 461 #define BUS_DMA_WRITE 0x200 /* mapping is memory -> device only */ 462 #define BUS_DMA_NOCACHE 0x400 /* hint: map non-cached memory */ 463 464 #define EMIPS_DMAMAP_COHERENT 0x10000 /* no cache flush necessary on sync */ 465 466 /* Forwards needed by prototypes below. */ 467 struct mbuf; 468 struct uio; 469 470 /* 471 * Operations performed by bus_dmamap_sync(). 472 */ 473 #define BUS_DMASYNC_PREREAD 0x01 /* pre-read synchronization */ 474 #define BUS_DMASYNC_POSTREAD 0x02 /* post-read synchronization */ 475 #define BUS_DMASYNC_PREWRITE 0x04 /* pre-write synchronization */ 476 #define BUS_DMASYNC_POSTWRITE 0x08 /* post-write synchronization */ 477 478 typedef struct emips_bus_dma_tag *bus_dma_tag_t; 479 typedef struct emips_bus_dmamap *bus_dmamap_t; 480 481 #define BUS_DMA_TAG_VALID(t) ((t) != (bus_dma_tag_t)0) 482 483 /* 484 * bus_dma_segment_t 485 * 486 * Describes a single contiguous DMA transaction. Values 487 * are suitable for programming into DMA registers. 488 */ 489 struct emips_bus_dma_segment { 490 bus_addr_t ds_addr; /* DMA address */ 491 bus_size_t ds_len; /* length of transfer */ 492 bus_addr_t _ds_vaddr; /* virtual address, 0 if invalid */ 493 }; 494 typedef struct emips_bus_dma_segment bus_dma_segment_t; 495 496 /* 497 * bus_dma_tag_t 498 * 499 * A machine-dependent opaque type describing the implementation of 500 * DMA for a given bus. 501 */ 502 503 struct emips_bus_dma_tag { 504 /* 505 * DMA mapping methods. 506 */ 507 int (*_dmamap_create)(bus_dma_tag_t, bus_size_t, int, 508 bus_size_t, bus_size_t, int, bus_dmamap_t *); 509 void (*_dmamap_destroy)(bus_dma_tag_t, bus_dmamap_t); 510 int (*_dmamap_load)(bus_dma_tag_t, bus_dmamap_t, void *, 511 bus_size_t, struct proc *, int); 512 int (*_dmamap_load_mbuf)(bus_dma_tag_t, bus_dmamap_t, 513 struct mbuf *, int); 514 int (*_dmamap_load_uio)(bus_dma_tag_t, bus_dmamap_t, 515 struct uio *, int); 516 int (*_dmamap_load_raw)(bus_dma_tag_t, bus_dmamap_t, 517 bus_dma_segment_t *, int, bus_size_t, int); 518 void (*_dmamap_unload)(bus_dma_tag_t, bus_dmamap_t); 519 void (*_dmamap_sync)(bus_dma_tag_t, bus_dmamap_t, 520 bus_addr_t, bus_size_t, int); 521 522 /* 523 * DMA memory utility functions. 524 */ 525 int (*_dmamem_alloc)(bus_dma_tag_t, bus_size_t, bus_size_t, 526 bus_size_t, bus_dma_segment_t *, int, int *, int); 527 void (*_dmamem_free)(bus_dma_tag_t, 528 bus_dma_segment_t *, int); 529 int (*_dmamem_map)(bus_dma_tag_t, bus_dma_segment_t *, 530 int, size_t, void **, int); 531 void (*_dmamem_unmap)(bus_dma_tag_t, void *, size_t); 532 paddr_t (*_dmamem_mmap)(bus_dma_tag_t, bus_dma_segment_t *, 533 int, off_t, int, int); 534 }; 535 536 #define bus_dmamap_create(t, s, n, m, b, f, p) \ 537 (*(t)->_dmamap_create)((t), (s), (n), (m), (b), (f), (p)) 538 #define bus_dmamap_destroy(t, p) \ 539 (*(t)->_dmamap_destroy)((t), (p)) 540 #define bus_dmamap_load(t, m, b, s, p, f) \ 541 (*(t)->_dmamap_load)((t), (m), (b), (s), (p), (f)) 542 #define bus_dmamap_load_mbuf(t, m, b, f) \ 543 (*(t)->_dmamap_load_mbuf)((t), (m), (b), (f)) 544 #define bus_dmamap_load_uio(t, m, u, f) \ 545 (*(t)->_dmamap_load_uio)((t), (m), (u), (f)) 546 #define bus_dmamap_load_raw(t, m, sg, n, s, f) \ 547 (*(t)->_dmamap_load_raw)((t), (m), (sg), (n), (s), (f)) 548 #define bus_dmamap_unload(t, p) \ 549 (*(t)->_dmamap_unload)((t), (p)) 550 #define bus_dmamap_sync(t, p, o, l, ops) \ 551 (*(t)->_dmamap_sync)((t), (p), (o), (l), (ops)) 552 553 #define bus_dmamem_alloc(t, s, a, b, sg, n, r, f) \ 554 (*(t)->_dmamem_alloc)((t), (s), (a), (b), (sg), (n), (r), (f)) 555 #define bus_dmamem_free(t, sg, n) \ 556 (*(t)->_dmamem_free)((t), (sg), (n)) 557 #define bus_dmamem_map(t, sg, n, s, k, f) \ 558 (*(t)->_dmamem_map)((t), (sg), (n), (s), (k), (f)) 559 #define bus_dmamem_unmap(t, k, s) \ 560 (*(t)->_dmamem_unmap)((t), (k), (s)) 561 #define bus_dmamem_mmap(t, sg, n, o, p, f) \ 562 (*(t)->_dmamem_mmap)((t), (sg), (n), (o), (p), (f)) 563 564 #define bus_dmatag_subregion(t, mna, mxa, nt, f) EOPNOTSUPP 565 #define bus_dmatag_destroy(t) 566 567 /* 568 * bus_dmamap_t 569 * 570 * Describes a DMA mapping. 571 */ 572 struct emips_bus_dmamap { 573 /* 574 * PRIVATE MEMBERS: not for use my machine-independent code. 575 */ 576 bus_size_t _dm_size; /* largest DMA transfer mappable */ 577 int _dm_segcnt; /* number of segs this map can map */ 578 bus_size_t _dm_maxmaxsegsz; /* fixed largest possible segment */ 579 bus_size_t _dm_boundary; /* don't cross this */ 580 int _dm_flags; /* misc. flags */ 581 struct vmspace *_dm_vmspace; /* vmspace that owns the mapping */ 582 583 /* 584 * PUBLIC MEMBERS: these are used by machine-independent code. 585 */ 586 bus_size_t dm_maxsegsz; /* largest possible segment */ 587 bus_size_t dm_mapsize; /* size of the mapping */ 588 int dm_nsegs; /* # valid segments in mapping */ 589 bus_dma_segment_t dm_segs[1]; /* segments; variable length */ 590 }; 591 592 #ifdef _EMIPS_BUS_DMA_PRIVATE 593 void emips_bus_dma_init(void); 594 595 int _bus_dmamap_create(bus_dma_tag_t, bus_size_t, int, bus_size_t, 596 bus_size_t, int, bus_dmamap_t *); 597 void _bus_dmamap_destroy(bus_dma_tag_t, bus_dmamap_t); 598 int _bus_dmamap_load(bus_dma_tag_t, bus_dmamap_t, void *, 599 bus_size_t, struct proc *, int); 600 int _bus_dmamap_load_mbuf(bus_dma_tag_t, bus_dmamap_t, 601 struct mbuf *, int); 602 int _bus_dmamap_load_uio(bus_dma_tag_t, bus_dmamap_t, 603 struct uio *, int); 604 int _bus_dmamap_load_raw(bus_dma_tag_t, bus_dmamap_t, 605 bus_dma_segment_t *, int, bus_size_t, int); 606 void _bus_dmamap_unload(bus_dma_tag_t, bus_dmamap_t); 607 void _bus_dmamap_sync_r3k(bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 608 bus_size_t, int); 609 void _bus_dmamap_sync_r4k(bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 610 bus_size_t, int); 611 612 int _bus_dmamem_alloc(bus_dma_tag_t tag, bus_size_t size, 613 bus_size_t alignment, bus_size_t boundary, 614 bus_dma_segment_t *segs, int nsegs, int *rsegs, int flags); 615 void _bus_dmamem_free(bus_dma_tag_t tag, bus_dma_segment_t *segs, 616 int nsegs); 617 int _bus_dmamem_map(bus_dma_tag_t tag, bus_dma_segment_t *segs, 618 int nsegs, size_t size, void **kvap, int flags); 619 void _bus_dmamem_unmap(bus_dma_tag_t tag, void *kva, 620 size_t size); 621 paddr_t _bus_dmamem_mmap(bus_dma_tag_t tag, bus_dma_segment_t *segs, 622 int nsegs, off_t off, int prot, int flags); 623 624 int _bus_dmamem_alloc_range(bus_dma_tag_t tag, bus_size_t size, 625 bus_size_t alignment, bus_size_t boundary, 626 bus_dma_segment_t *segs, int nsegs, int *rsegs, int flags, 627 vaddr_t low, vaddr_t high); 628 629 extern struct emips_bus_dma_tag emips_default_bus_dma_tag; 630 #endif /* _EMIPS_BUS_DMA_PRIVATE */ 631 632 #endif /* !_EMIPS_BUS_H_ */ 633
Indexes created Sat Oct 25 10:09:55 GMT 2025