cpu.h revision 1.1.12.2 1 1.1.12.2 yamt /* $NetBSD: cpu.h,v 1.1.12.2 2014/05/22 11:39:39 yamt Exp $ */
2 1.1.12.2 yamt /*
3 1.1.12.2 yamt * Copyright (c) 2013 KIYOHARA Takashi
4 1.1.12.2 yamt * All rights reserved.
5 1.1.12.2 yamt *
6 1.1.12.2 yamt * Redistribution and use in source and binary forms, with or without
7 1.1.12.2 yamt * modification, are permitted provided that the following conditions
8 1.1.12.2 yamt * are met:
9 1.1.12.2 yamt * 1. Redistributions of source code must retain the above copyright
10 1.1.12.2 yamt * notice, this list of conditions and the following disclaimer.
11 1.1.12.2 yamt * 2. Redistributions in binary form must reproduce the above copyright
12 1.1.12.2 yamt * notice, this list of conditions and the following disclaimer in the
13 1.1.12.2 yamt * documentation and/or other materials provided with the distribution.
14 1.1.12.2 yamt *
15 1.1.12.2 yamt * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 1.1.12.2 yamt * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
17 1.1.12.2 yamt * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 1.1.12.2 yamt * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 1.1.12.2 yamt * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 1.1.12.2 yamt * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 1.1.12.2 yamt * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 1.1.12.2 yamt * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 1.1.12.2 yamt * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
24 1.1.12.2 yamt * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 1.1.12.2 yamt * POSSIBILITY OF SUCH DAMAGE.
26 1.1.12.2 yamt */
27 1.1.12.2 yamt
28 1.1.12.2 yamt class CPU {
29 1.1.12.2 yamt public:
30 1.1.12.2 yamt virtual void cacheFlush(void);
31 1.1.12.2 yamt virtual void tlbFlush(void);
32 1.1.12.2 yamt };
33 1.1.12.2 yamt
34 1.1.12.2 yamt class ARM7 : public CPU {
35 1.1.12.2 yamt public:
36 1.1.12.2 yamt void cacheFlush(void);
37 1.1.12.2 yamt void tlbFlush(void);
38 1.1.12.2 yamt };
39 1.1.12.2 yamt
40 1.1.12.2 yamt class ARM7TDMI : public CPU {
41 1.1.12.2 yamt public:
42 1.1.12.2 yamt void cacheFlush(void);
43 1.1.12.2 yamt void tlbFlush(void);
44 1.1.12.2 yamt };
45 1.1.12.2 yamt
46 1.1.12.2 yamt class SA1100 : public CPU {
47 1.1.12.2 yamt void cacheFlush(void);
48 1.1.12.2 yamt void tlbFlush(void);
49 1.1.12.2 yamt };
50