epoc32.cpp revision 1.1.4.2
1 1.1.4.2 tls /* $NetBSD: epoc32.cpp,v 1.1.4.2 2013/06/23 06:20:03 tls Exp $ */ 2 1.1.4.2 tls /* 3 1.1.4.2 tls * Copyright (c) 2013 KIYOHARA Takashi 4 1.1.4.2 tls * All rights reserved. 5 1.1.4.2 tls * 6 1.1.4.2 tls * Redistribution and use in source and binary forms, with or without 7 1.1.4.2 tls * modification, are permitted provided that the following conditions 8 1.1.4.2 tls * are met: 9 1.1.4.2 tls * 1. Redistributions of source code must retain the above copyright 10 1.1.4.2 tls * notice, this list of conditions and the following disclaimer. 11 1.1.4.2 tls * 2. Redistributions in binary form must reproduce the above copyright 12 1.1.4.2 tls * notice, this list of conditions and the following disclaimer in the 13 1.1.4.2 tls * documentation and/or other materials provided with the distribution. 14 1.1.4.2 tls * 15 1.1.4.2 tls * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 1.1.4.2 tls * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 1.1.4.2 tls * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 1.1.4.2 tls * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 1.1.4.2 tls * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 1.1.4.2 tls * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 1.1.4.2 tls * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 1.1.4.2 tls * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 1.1.4.2 tls * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 1.1.4.2 tls * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 1.1.4.2 tls * POSSIBILITY OF SUCH DAMAGE. 26 1.1.4.2 tls */ 27 1.1.4.2 tls 28 1.1.4.2 tls #include <e32base.h> 29 1.1.4.2 tls #include <e32def.h> 30 1.1.4.2 tls #include <e32std.h> 31 1.1.4.2 tls 32 1.1.4.2 tls #include "cpu.h" 33 1.1.4.2 tls #include "e32boot.h" 34 1.1.4.2 tls #include "ekern.h" 35 1.1.4.2 tls #include "epoc32.h" 36 1.1.4.2 tls 37 1.1.4.2 tls #include "arm/armreg.h" 38 1.1.4.2 tls #include "arm/arm32/pte.h" 39 1.1.4.2 tls 40 1.1.4.2 tls 41 1.1.4.2 tls static inline void 42 1.1.4.2 tls AllowAllDomains(void) 43 1.1.4.2 tls { 44 1.1.4.2 tls TUint domains; 45 1.1.4.2 tls 46 1.1.4.2 tls #define ALL_DOMAINS(v) \ 47 1.1.4.2 tls (((v) << 28) | \ 48 1.1.4.2 tls ((v) << 24) | \ 49 1.1.4.2 tls ((v) << 20) | \ 50 1.1.4.2 tls ((v) << 16) | \ 51 1.1.4.2 tls ((v) << 12) | \ 52 1.1.4.2 tls ((v) << 8) | \ 53 1.1.4.2 tls ((v) << 4) | \ 54 1.1.4.2 tls ((v) << 0)) 55 1.1.4.2 tls 56 1.1.4.2 tls domains = ALL_DOMAINS(0xf); 57 1.1.4.2 tls __asm("mcr p15, 0, %0, c3, c0" : : "r"(domains)); 58 1.1.4.2 tls } 59 1.1.4.2 tls 60 1.1.4.2 tls EPOC32::EPOC32(void) 61 1.1.4.2 tls { 62 1.1.4.2 tls TUint procid; 63 1.1.4.2 tls 64 1.1.4.2 tls __asm("mrc p15, 0, %0, c0, c0" : "=r"(procid)); 65 1.1.4.2 tls if (procid == CPU_ID_SA1100) { 66 1.1.4.2 tls cpu = new SA1100; 67 1.1.4.2 tls } else if ((procid & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_ARM_LTD) { 68 1.1.4.2 tls if (CPU_ID_IS7(procid)) { 69 1.1.4.2 tls if ((procid & CPU_ID_7ARCH_MASK) == CPU_ID_7ARCH_V3) 70 1.1.4.2 tls cpu = new ARM7; 71 1.1.4.2 tls else 72 1.1.4.2 tls cpu = new ARM7TDMI; 73 1.1.4.2 tls } 74 1.1.4.2 tls } 75 1.1.4.2 tls } 76 1.1.4.2 tls 77 1.1.4.2 tls EPOC32::~EPOC32(void) 78 1.1.4.2 tls { 79 1.1.4.2 tls } 80 1.1.4.2 tls 81 1.1.4.2 tls TAny * 82 1.1.4.2 tls EPOC32::GetPhysicalAddress(TAny *address) 83 1.1.4.2 tls { 84 1.1.4.2 tls TUint l1Index, l1, pageOffset, pa, va; 85 1.1.4.2 tls TUint *l1Tbl; 86 1.1.4.2 tls 87 1.1.4.2 tls AllowAllDomains(); 88 1.1.4.2 tls 89 1.1.4.2 tls l1Tbl = GetTTB(); 90 1.1.4.2 tls 91 1.1.4.2 tls va = (TUint)address; 92 1.1.4.2 tls pa = pageOffset = 0; 93 1.1.4.2 tls l1Index = (va & L1_ADDR_BITS) >> L1_S_SHIFT; 94 1.1.4.2 tls l1 = *(l1Tbl + l1Index); 95 1.1.4.2 tls switch (l1 & L1_TYPE_MASK) { 96 1.1.4.2 tls case L1_TYPE_INV: 97 1.1.4.2 tls case L1_TYPE_F: 98 1.1.4.2 tls return NULL; 99 1.1.4.2 tls 100 1.1.4.2 tls case L1_TYPE_S: 101 1.1.4.2 tls pa = l1 & L1_S_ADDR_MASK; 102 1.1.4.2 tls pageOffset = va & L1_S_OFFSET; 103 1.1.4.2 tls break; 104 1.1.4.2 tls 105 1.1.4.2 tls case L1_TYPE_C: 106 1.1.4.2 tls { 107 1.1.4.2 tls TUint *l2Tbl, tag; 108 1.1.4.2 tls 109 1.1.4.2 tls l2Tbl = (TUint *)(l1 & L1_C_ADDR_MASK); 110 1.1.4.2 tls tag = MapPhysicalAddress(l2Tbl, (TAny **)&l2Tbl); 111 1.1.4.2 tls pa = *(l2Tbl + ((va & L2_ADDR_BITS) >> 12)); 112 1.1.4.2 tls UnmapPhysicalAddress(l2Tbl, tag); 113 1.1.4.2 tls 114 1.1.4.2 tls switch (pa & L2_TYPE_MASK) { 115 1.1.4.2 tls case L2_TYPE_L: 116 1.1.4.2 tls pa &= L2_L_FRAME; 117 1.1.4.2 tls pageOffset = va & L2_L_OFFSET; 118 1.1.4.2 tls break; 119 1.1.4.2 tls 120 1.1.4.2 tls case L2_TYPE_S: 121 1.1.4.2 tls pa &= L2_S_FRAME; 122 1.1.4.2 tls pageOffset = va & L2_S_OFFSET; 123 1.1.4.2 tls break; 124 1.1.4.2 tls 125 1.1.4.2 tls default: 126 1.1.4.2 tls pageOffset = 0xffffffff; /* XXXX */ 127 1.1.4.2 tls } 128 1.1.4.2 tls } 129 1.1.4.2 tls } 130 1.1.4.2 tls return (TAny *)(pa | pageOffset); 131 1.1.4.2 tls } 132 1.1.4.2 tls 133 1.1.4.2 tls TUint 134 1.1.4.2 tls EPOC32::MapPhysicalAddress(TAny *pa, TAny **vap) 135 1.1.4.2 tls { 136 1.1.4.2 tls TUint *l1Tbl, l1Index, l1, tag; 137 1.1.4.2 tls 138 1.1.4.2 tls AllowAllDomains(); 139 1.1.4.2 tls 140 1.1.4.2 tls l1Tbl = GetTTB(); 141 1.1.4.2 tls 142 1.1.4.2 tls l1Index = ((TUint)pa & L1_ADDR_BITS) >> L1_S_SHIFT; 143 1.1.4.2 tls l1 = ((TUint)pa & L1_S_ADDR_MASK) | 144 1.1.4.2 tls L1_S_AP(AP_KRW) | L1_S_IMP | L1_TYPE_S; 145 1.1.4.2 tls tag = *(l1Tbl + l1Index); 146 1.1.4.2 tls *(l1Tbl + l1Index) = l1; 147 1.1.4.2 tls cpu->cacheFlush(); 148 1.1.4.2 tls cpu->tlbFlush(); 149 1.1.4.2 tls *vap = pa; 150 1.1.4.2 tls 151 1.1.4.2 tls return tag; 152 1.1.4.2 tls } 153 1.1.4.2 tls 154 1.1.4.2 tls void 155 1.1.4.2 tls EPOC32::UnmapPhysicalAddress(TAny *address, TUint tag) 156 1.1.4.2 tls { 157 1.1.4.2 tls TUint *l1Tbl, l1Index, pa; 158 1.1.4.2 tls 159 1.1.4.2 tls AllowAllDomains(); 160 1.1.4.2 tls 161 1.1.4.2 tls l1Tbl = GetTTB(); 162 1.1.4.2 tls 163 1.1.4.2 tls pa = (TUint)address; 164 1.1.4.2 tls l1Index = (pa & L1_ADDR_BITS) >> L1_S_SHIFT; 165 1.1.4.2 tls *(l1Tbl + l1Index) = tag; 166 1.1.4.2 tls cpu->cacheFlush(); 167 1.1.4.2 tls cpu->tlbFlush(); 168 1.1.4.2 tls } 169
Indexes created Wed Oct 22 00:09:40 GMT 2025