armadillo9_start.S revision 1.4
1 /* $NetBSD: armadillo9_start.S,v 1.4 2009/10/21 14:15:51 rmind Exp $ */ 2 3 /* 4 * Copyright (c) 2003 5 * Ichiro FUKUHARA <ichiro (at) ichiro.org>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <machine/asm.h> 31 #include <arm/armreg.h> 32 #include <arm/arm32/pte.h> 33 #include "epcom.h" 34 35 .section .start,"ax",%progbits 36 37 .global _C_LABEL(armadillo9_start) 38 _C_LABEL(armadillo9_start): 39 40 /* make sure svc mode and all fiqs&irqs disabled */ 41 mov r0, #(PSR_SVC32_MODE | I32_bit | F32_bit) 42 msr cpsr_c, r0 43 44 /* 45 * We will go ahead and disable the MMU here so that we don't 46 * have to worry about flushing caches, etc. 47 * 48 * Note that we may not currently be running VA==PA, which means 49 * we'll need to leap to the next insn after disabing the MMU. 50 */ 51 adr r8, Lunmapped 52 bic r8, r8, #0xff000000 /* clear upper 8 bits */ 53 orr r8, r8, #0xc0000000 /* OR in physical base address */ 54 55 /* 56 * Setup coprocessor 15. 57 */ 58 mrc p15, 0, r2, c1, c0, 0 59 bic r2, r2, #CPU_CONTROL_MMU_ENABLE 60 bic r2, r2, #CPU_CONTROL_DC_ENABLE 61 bic r2, r2, #CPU_CONTROL_IC_ENABLE 62 mcr p15, 0, r2, c1, c0, 0 63 64 nop 65 nop 66 nop 67 mov pc, r8 /* Heave-ho! */ 68 69 Lunmapped: 70 /* set temporary stack pointer */ 71 ldr sp, Ltable 72 73 #ifdef VERBOSE_INIT_ARM 74 /* initialize UART */ 75 bl init_UART 76 #endif 77 /* copy bootparam */ 78 bl copy_bootparam 79 80 /* copy myself to virtual address */ 81 bl copy_myself 82 83 /* 84 * We want to construct a memory map that maps us 85 * VA==PA (SDRAM at 0xc0000000). We create these 86 * mappings uncached and unbuffered to be safe. 87 */ 88 /* 89 * Step 1: Map the entire address space VA==PA. 90 */ 91 adr r4, Ltable 92 ldr r0, [r4] /* r0 = &l1table */ 93 mov r1, #(L1_TABLE_SIZE / 4) /* 4096 entry */ 94 mov r2, #(L1_S_SIZE) /* 1MB / section */ 95 mov r3, #(L1_S_AP(AP_KRW)) /* kernel read/write */ 96 orr r3, r3, #(L1_TYPE_S) /* L1 entry is section */ 97 1: 98 str r3, [r0], #0x04 99 add r3, r3, r2 100 subs r1, r1, #1 101 bgt 1b 102 103 /* 104 * Step 2: Map VA 0xf0000000->0xf00fffff to PA 0x80000000->0x800fffff. 105 */ 106 ldr r0, [r4] 107 add r0, r0, #(0xf00 * 4) /* offset to 0xf0000000 */ 108 mov r3, #(L1_S_AP(AP_KRW)) /* kernel read/write */ 109 orr r3, r3, #(L1_TYPE_S) /* L1 entry is section */ 110 orr r3, r3, #0x80000000 111 str r3, [r0], #4 112 113 /* 114 * Step 3: Map VA 0xf0100000->0xf02fffff to PA 0x80800000->0x809fffff. 115 */ 116 mov r3, #(L1_S_AP(AP_KRW)) /* kernel read/write */ 117 orr r3, r3, #(L1_TYPE_S) /* L1 entry is section */ 118 orr r3, r3, #0x80000000 119 orr r3, r3, #0x00800000 120 str r3, [r0], #0x4 121 add r3, r3, r2 122 str r3, [r0], #0x4 123 124 /* OK! Page table is set up. Give it to the CPU. */ 125 adr r0, Ltable 126 ldr r0, [r0] 127 mcr p15, 0, r0, c2, c0, 0 128 129 /* Flush the old TLBs, just in case. */ 130 mcr p15, 0, r0, c8, c7, 0 131 132 /* Set the Domain Access register. Very important! */ 133 mov r0, #1 134 mcr p15, 0, r0, c3, c0, 0 135 136 /* Get ready to jump to the "real" kernel entry point... */ 137 ldr r1, Lstart 138 mov r1, r1 /* Make sure the load completes! */ 139 140 /* OK, let's enable the MMU. */ 141 mrc p15, 0, r2, c1, c0, 0 142 orr r2, r2, #CPU_CONTROL_MMU_ENABLE 143 mcr p15, 0, r2, c1, c0, 0 144 145 nop 146 nop 147 nop 148 149 /* CPWAIT sequence to make sure the MMU is on... */ 150 mrc p15, 0, r2, c2, c0, 0 /* arbitrary read of CP15 */ 151 mov r2, r2 /* force it to complete */ 152 mov pc, r1 /* leap to kernel entry point! */ 153 154 #define BOOTPARAM_ADDRESS 0xc0000100 155 #define BOOTPARAM_SIZE 0x0f00 156 157 Ltable: 158 .word armadillo9_start - L1_TABLE_SIZE 159 Lstart: 160 .word start 161 162 Lsection: 163 .word .start 164 .word 0xc0200000 165 .word __bss_start 166 167 Lbootparam_address: 168 .word BOOTPARAM_ADDRESS 169 170 copy_myself: 171 stmfd sp!, {r0-r5, lr} 172 adr r0, Lsection 173 ldmia r0, {r1, r2, r4} /* r1: kernel(load) start address */ 174 /* r2: kernel(virtual) start address */ 175 /* r3: kernel size */ 176 sub r3, r4, r2 /* r4: kernel(virtual) end address */ 177 add r5, r1, r3 /* r5: kernel(load) end address */ 178 #ifdef VERBOSE_INIT_ARM 179 adr r0, Lmsg1 /* "copy kernel from " */ 180 bl print_str 181 bl print_r1 182 adr r0, Lmsg2 /* " to " */ 183 bl print_str 184 bl print_r2 185 adr r0, Lmsg3 /* " size " */ 186 bl print_str 187 bl print_r3 188 bl print_cr 189 #endif 190 1: 191 ldr r0, [r5], #-4 192 str r0, [r4], #-4 193 cmp r5, r1 194 bge 1b 195 ldmfd sp!, {r0-r5, pc} 196 197 copy_bootparam: 198 stmfd sp!, {r0-r3, lr} 199 mov r1, #BOOTPARAM_SIZE 200 ldr r2, Lbootparam_address 201 adr r3, _C_LABEL(bootparam) 202 #ifdef VERBOSE_INIT_ARM 203 adr r0, Lmsg0 /* "copy bootparam from " */ 204 bl print_str 205 bl print_r2 206 adr r0, Lmsg2 /* " to " */ 207 bl print_str 208 bl print_r3 209 adr r0, Lmsg3 /* " size " */ 210 bl print_str 211 bl print_r1 212 bl print_cr 213 #endif 214 1: 215 ldr r0, [r2], #4 216 str r0, [r3], #4 217 subs r1, r1, #4 218 bne 1b 219 ldmfd sp!, {r0-r3, pc} 220 221 #ifdef VERBOSE_INIT_ARM 222 Lmsg0: 223 .asciz "copy bootparam from " 224 .align 0 225 Lmsg1: 226 .asciz "copy kernel from " 227 .align 0 228 Lmsg2: 229 .asciz " to " 230 .align 0 231 Lmsg3: 232 .asciz " size " 233 .align 0 234 235 #if NEPCOM > 0 236 #define EP93XX_APB_UART1 0x808c0000 237 #define EP93XX_APB_UART2 0x808d0000 238 239 #ifndef CONUNIT 240 #define CONUNIT 0 241 #endif 242 243 Lcomaddr: 244 .word EP93XX_APB_UART1 245 .word EP93XX_APB_UART2 246 #endif 247 248 init_UART: 249 stmfd sp!, {r4-r5, lr} 250 #if NEPCOM > 0 251 ldr r4, Lcomaddr+(CONUNIT*4) 252 ldr r5, [r4, #0x08] 253 orr r5, r5, #0x10 254 str r5, [r4, #0x08] /* enable FIFO */ 255 mov r5, #0x01 256 str r5, [r4, #0x14] /* disable interrupt */ 257 #endif 258 ldmfd sp!, {r4-r5, pc} 259 260 print_char: /* char = r0 */ 261 stmfd sp!, {r4-r5, lr} 262 #if NEPCOM > 0 263 ldr r4, Lcomaddr+(CONUNIT*4) 264 1: 265 ldr r5, [r4, #0x18] 266 tst r5, #0x20 /* check TXFF */ 267 bne 1b 268 str r0, [r4, #0x00] 269 #endif 270 ldmfd sp!, {r4-r5, pc} 271 272 print_cr: 273 stmfd sp!, {r0, lr} 274 #if NEPCOM > 0 275 mov r0, #0x0d /* cr */ 276 bl print_char 277 mov r0, #0x0a /* lf */ 278 bl print_char 279 #endif 280 ldmfd sp!, {r0, pc} 281 282 print_str: 283 stmfd sp!, {r0, r4, lr} 284 #if NEPCOM > 0 285 mov r4, r0 286 1: 287 ldrb r0, [r4], #1 288 cmp r0, #0 289 beq 2f 290 bl print_char 291 b 1b 292 2: 293 #endif 294 ldmfd sp!, {r0, r4, pc} 295 296 print_r3: 297 stmfd sp!, {r0, r3-r6, lr} 298 #if NEPCOM > 0 299 mov r4, #28 300 mov r5, #0xf 301 1: 302 and r6, r5, r3, ROR r4 303 cmp r6, #10 304 addlt r0, r6, #'0' 305 addge r0, r6, #('a' - 0x0a) 306 bl print_char 307 subs r4, r4, #4 308 bge 1b 309 #endif 310 ldmfd sp!, {r0, r3-r6, pc} 311 312 #define print_register(reg) \ 313 stmfd sp!, {r3, lr} ;\ 314 mov r3, reg ;\ 315 bl print_r3 ;\ 316 ldmfd sp!, {r3, pc} 317 318 print_r0: 319 print_register(r0) 320 321 print_r1: 322 print_register(r1) 323 324 print_r2: 325 print_register(r2) 326 #endif 327 328 .global _C_LABEL(bootparam) 329 _C_LABEL(bootparam): 330 .space BOOTPARAM_SIZE 331
Indexes created Sun Oct 19 02:09:48 GMT 2025