bcm53xx_machdep.c revision 1.24
1 /* $NetBSD: bcm53xx_machdep.c,v 1.24 2020/10/30 18:54:37 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #define CCA_PRIVATE 33 #define IDM_PRIVATE 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: bcm53xx_machdep.c,v 1.24 2020/10/30 18:54:37 skrll Exp $"); 37 38 #include "opt_arm_debug.h" 39 #include "opt_console.h" 40 #include "opt_evbarm_boardtype.h" 41 #include "opt_broadcom.h" 42 #include "opt_kgdb.h" 43 #include "com.h" 44 #include "pci.h" 45 #include "bcmrng_ccb.h" 46 47 #include <sys/param.h> 48 #include <sys/bus.h> 49 #include <sys/atomic.h> 50 #include <sys/device.h> 51 #include <sys/kernel.h> 52 #include <sys/reboot.h> 53 #include <sys/termios.h> 54 55 #include <dev/cons.h> 56 57 #include <uvm/uvm_extern.h> 58 59 #include <arm/db_machdep.h> 60 #include <arm/undefined.h> 61 #include <arm/arm32/machdep.h> 62 63 #include <machine/autoconf.h> 64 #include <machine/bootconfig.h> 65 66 #define CCA_PRIVATE 67 68 #include <arm/cortex/scu_reg.h> 69 #include <arm/broadcom/bcm53xx_var.h> 70 71 #include <evbarm/bcm53xx/platform.h> 72 73 #if NCOM == 0 74 #error missing COM device for console 75 #endif 76 77 #include <dev/ic/comreg.h> 78 #include <dev/ic/comvar.h> 79 80 extern int _end[]; 81 extern int KERNEL_BASE_phys[]; 82 extern int KERNEL_BASE_virt[]; 83 84 BootConfig bootconfig; 85 static char bootargs[MAX_BOOT_STRING]; 86 char *boot_args = NULL; 87 88 /* filled in before cleaning bss. keep in .data */ 89 u_int uboot_args[4] __attribute__((__section__(".data"))); 90 91 static void bcm53xx_system_reset(void); 92 93 #ifndef CONADDR 94 #define CONADDR (BCM53XX_IOREG_PBASE + CCA_UART0_BASE) 95 #endif 96 #ifndef CONSPEED 97 #define CONSPEED B115200 98 #endif 99 #ifndef CONMODE 100 #define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */ 101 #endif 102 103 void bcm53xx_mpstart(void); 104 void bcm53xx_platform_early_putchar(char); 105 106 #if (NCOM > 0) 107 static const bus_addr_t comcnaddr = (bus_addr_t)CONADDR; 108 109 int comcnspeed = CONSPEED; 110 int comcnmode = CONMODE | CLOCAL; 111 #endif 112 113 #ifdef KGDB 114 #include <sys/kgdb.h> 115 #endif 116 117 static void 118 earlyconsputc(dev_t dev, int c) 119 { 120 uartputc(c); 121 } 122 123 static int 124 earlyconsgetc(dev_t dev) 125 { 126 return 0; 127 } 128 129 static struct consdev earlycons = { 130 .cn_putc = earlyconsputc, 131 .cn_getc = earlyconsgetc, 132 .cn_pollc = nullcnpollc, 133 }; 134 135 /* 136 * Static device mappings. These peripheral registers are mapped at 137 * fixed virtual addresses very early in initarm() so that we can use 138 * them while booting the kernel, and stay at the same address 139 * throughout whole kernel's life time. 140 * 141 * We use this table twice; once with bootstrap page table, and once 142 * with kernel's page table which we build up in initarm(). 143 * 144 * Since we map these registers into the bootstrap page table using 145 * pmap_devmap_bootstrap() which calls pmap_map_chunk(), we map 146 * registers segment-aligned and segment-rounded in order to avoid 147 * using the 2nd page tables. 148 */ 149 150 static const struct pmap_devmap devmap[] = { 151 { 152 KERNEL_IO_IOREG_VBASE, 153 BCM53XX_IOREG_PBASE, /* 0x18000000 */ 154 BCM53XX_IOREG_SIZE, /* 2MB */ 155 VM_PROT_READ|VM_PROT_WRITE, 156 PTE_NOCACHE, 157 }, 158 { 159 KERNEL_IO_ARMCORE_VBASE, 160 BCM53XX_ARMCORE_PBASE, /* 0x19000000 */ 161 BCM53XX_ARMCORE_SIZE, /* 1MB */ 162 VM_PROT_READ|VM_PROT_WRITE, 163 PTE_NOCACHE, 164 }, 165 { 166 KERNEL_IO_ROM_REGION_VBASE, 167 BCM53XX_ROM_REGION_PBASE, /* 0xfff00000 */ 168 BCM53XX_ROM_REGION_SIZE, /* 1MB */ 169 VM_PROT_READ|VM_PROT_WRITE, 170 PTE_NOCACHE, 171 }, 172 #if NPCI > 0 173 { 174 KERNEL_IO_PCIE0_OWIN_VBASE, 175 BCM53XX_PCIE0_OWIN_PBASE, /* 0x08000000 */ 176 BCM53XX_PCIE0_OWIN_SIZE, /* 4MB */ 177 VM_PROT_READ|VM_PROT_WRITE, 178 PTE_NOCACHE, 179 }, 180 { 181 KERNEL_IO_PCIE1_OWIN_VBASE, 182 BCM53XX_PCIE1_OWIN_PBASE, /* 0x40000000 */ 183 BCM53XX_PCIE1_OWIN_SIZE, /* 4MB */ 184 VM_PROT_READ|VM_PROT_WRITE, 185 PTE_NOCACHE, 186 }, 187 { 188 KERNEL_IO_PCIE2_OWIN_VBASE, 189 BCM53XX_PCIE2_OWIN_PBASE, /* 0x48000000 */ 190 BCM53XX_PCIE2_OWIN_SIZE, /* 4MB */ 191 VM_PROT_READ|VM_PROT_WRITE, 192 PTE_NOCACHE, 193 }, 194 #endif /* NPCI > 0 */ 195 { 0, 0, 0, 0, 0 } 196 }; 197 198 static const struct boot_physmem bp_first256 = { 199 .bp_start = 0x80000000 / NBPG, 200 .bp_pages = 0x10000000 / NBPG, 201 .bp_freelist = VM_FREELIST_ISADMA, 202 .bp_flags = 0, 203 }; 204 205 #define BCM53xx_ROM_CPU_ENTRY 0xffff0400 206 207 void 208 bcm53xx_mpstart(void) 209 { 210 #ifdef MULTIPROCESSOR 211 /* 212 * Invalidate all SCU cache tags. That is, for all cores (0-3) 213 */ 214 bus_space_write_4(bcm53xx_armcore_bst, bcm53xx_armcore_bsh, 215 ARMCORE_SCU_BASE + SCU_INV_ALL_REG, 0xffff); 216 217 uint32_t diagctl = bus_space_read_4(bcm53xx_armcore_bst, 218 bcm53xx_armcore_bsh, ARMCORE_SCU_BASE + SCU_DIAG_CONTROL); 219 diagctl |= SCU_DIAG_DISABLE_MIGBIT; 220 bus_space_write_4(bcm53xx_armcore_bst, bcm53xx_armcore_bsh, 221 ARMCORE_SCU_BASE + SCU_DIAG_CONTROL, diagctl); 222 223 uint32_t scu_ctl = bus_space_read_4(bcm53xx_armcore_bst, 224 bcm53xx_armcore_bsh, ARMCORE_SCU_BASE + SCU_CTL); 225 scu_ctl |= SCU_CTL_SCU_ENA; 226 bus_space_write_4(bcm53xx_armcore_bst, bcm53xx_armcore_bsh, 227 ARMCORE_SCU_BASE + SCU_CTL, scu_ctl); 228 229 armv7_dcache_wbinv_all(); 230 231 const paddr_t mpstart = KERN_VTOPHYS((vaddr_t)cpu_mpstart); 232 bus_space_tag_t bcm53xx_rom_bst = &bcmgen_bs_tag; 233 bus_space_handle_t bcm53xx_rom_entry_bsh; 234 235 int error = bus_space_map(bcm53xx_rom_bst, BCM53xx_ROM_CPU_ENTRY, 236 4, 0, &bcm53xx_rom_entry_bsh); 237 238 /* 239 * Before we turn on the MMU, let's the other process out of the 240 * SKU ROM but setting the magic LUT address to our own mp_start 241 * routine. 242 */ 243 bus_space_write_4(bcm53xx_rom_bst, bcm53xx_rom_entry_bsh, mpstart); 244 245 dsb(sy); 246 __asm __volatile("sev" ::: "memory"); 247 248 for (int loop = 0; loop < 16; loop++) { 249 VPRINTF("%u hatched %#x\n", loop, arm_cpu_hatched); 250 if (arm_cpu_hatched == __BITS(arm_cpu_max - 1, 1)) 251 break; 252 int timo = 1500000; 253 while (arm_cpu_hatched != __BITS(arm_cpu_max - 1, 1)) 254 if (--timo == 0) 255 break; 256 } 257 for (size_t i = 1; i < arm_cpu_max; i++) { 258 if (cpu_hatched_p(i)) {) 259 printf("%s: warning: cpu%zu failed to hatch\n", 260 __func__, i); 261 } 262 } 263 264 VPRINTF(" (%u cpu%s, hatched %#x)", 265 arm_cpu_max, arm_cpu_max ? "s" : "", 266 arm_cpu_hatched); 267 #endif /* MULTIPROCESSOR */ 268 } 269 270 /* 271 * vaddr_t initarm(...) 272 * 273 * Initial entry point on startup. This gets called before main() is 274 * entered. 275 * It should be responsible for setting up everything that must be 276 * in place when main is called. 277 * This includes 278 * Taking a copy of the boot configuration structure. 279 * Initialising the physical console so characters can be printed. 280 * Setting up page tables for the kernel 281 */ 282 vaddr_t 283 initarm(void *arg) 284 { 285 /* 286 * Heads up ... Setup the CPU / MMU / TLB functions 287 */ 288 if (set_cpufuncs()) // starts PMC counter 289 panic("cpu not recognized!"); 290 291 cn_tab = &earlycons; 292 293 extern char ARM_BOOTSTRAP_LxPT[]; 294 pmap_devmap_bootstrap((vaddr_t)ARM_BOOTSTRAP_LxPT, devmap); 295 296 bcm53xx_bootstrap(KERNEL_IO_IOREG_VBASE); 297 298 #ifdef MULTIPROCESSOR 299 uint32_t scu_cfg = bus_space_read_4(bcm53xx_armcore_bst, bcm53xx_armcore_bsh, 300 ARMCORE_SCU_BASE + SCU_CFG); 301 arm_cpu_max = 1 + (scu_cfg & SCU_CFG_CPUMAX); 302 membar_producer(); 303 #endif 304 cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT); 305 306 consinit(); 307 308 bcm53xx_cpu_softc_init(curcpu()); 309 bcm53xx_print_clocks(); 310 311 #if NBCMRNG_CCB > 0 312 /* 313 * Start this early since it takes a while to startup up. 314 */ 315 bcm53xx_rng_start(bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh); 316 #endif 317 318 printf("uboot arg = %#x, %#x, %#x, %#x\n", 319 uboot_args[0], uboot_args[1], uboot_args[2], uboot_args[3]); 320 321 /* Talk to the user */ 322 printf("\nNetBSD/evbarm (" ___STRING(EVBARM_BOARDTYPE) ") booting ...\n"); 323 324 bootargs[0] = '\0'; 325 326 #if defined(VERBOSE_INIT_ARM) || 1 327 printf("initarm: Configuring system"); 328 #ifdef MULTIPROCESSOR 329 printf(" (%u cpu%s, hatched %#x)", 330 arm_cpu_max + 1, arm_cpu_max + 1 ? "s" : "", 331 arm_cpu_hatched); 332 #endif 333 printf(", CLIDR=%010o CTR=%#x PMUSERSR=%#x", 334 armreg_clidr_read(), armreg_ctr_read(), armreg_pmuserenr_read()); 335 printf("\n"); 336 #endif 337 338 psize_t memsize = bcm53xx_memprobe(); 339 #ifdef MEMSIZE 340 if ((memsize >> 20) > MEMSIZE) 341 memsize = MEMSIZE*1024*1024; 342 #endif 343 const bool bigmem_p = (memsize >> 20) > 256; 344 345 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 346 const bool mapallmem_p = true; 347 #ifndef PMAP_NEED_ALLOC_POOLPAGE 348 if (memsize > KERNEL_VM_BASE - KERNEL_BASE) { 349 printf("%s: dropping RAM size from %luMB to %uMB\n", 350 __func__, (unsigned long) (ram_size >> 20), 351 (KERNEL_VM_BASE - KERNEL_BASE) >> 20); 352 memsize = KERNEL_VM_BASE - KERNEL_BASE; 353 } 354 #endif 355 #else 356 const bool mapallmem_p = false; 357 #endif 358 KASSERT((armreg_pfr1_read() & ARM_PFR1_SEC_MASK) != 0); 359 arm32_bootmem_init(KERN_VTOPHYS(KERNEL_BASE), memsize, 360 (paddr_t)KERNEL_BASE_phys); 361 362 bcm53xx_dma_bootstrap(memsize); 363 364 /* 365 * This is going to do all the hard work of setting up the first and 366 * and second level page tables. Pages of memory will be allocated 367 * and mapped for other structures that are required for system 368 * operation. When it returns, physical_freestart and free_pages will 369 * have been updated to reflect the allocations that were made. In 370 * addition, kernel_l1pt, kernel_pt_table[], systempage, irqstack, 371 * abtstack, undstack, kernelstack, msgbufphys will be set to point to 372 * the memory that was allocated for them. 373 */ 374 arm32_kernel_vm_init(KERNEL_VM_BASE, ARM_VECTORS_HIGH, 0, devmap, 375 mapallmem_p); 376 377 cpu_reset_address = bcm53xx_system_reset; 378 /* we've a specific device_register routine */ 379 evbarm_device_register = bcm53xx_device_register; 380 if (bigmem_p) { 381 /* 382 * If we have more than 256MB 383 */ 384 arm_poolpage_vmfreelist = bp_first256.bp_freelist; 385 } 386 387 /* 388 * If we have more than 256MB of RAM, set aside the first 256MB for 389 * non-default VM allocations. 390 */ 391 vaddr_t sp = initarm_common(KERNEL_VM_BASE, KERNEL_VM_SIZE, 392 (bigmem_p ? &bp_first256 : NULL), (bigmem_p ? 1 : 0)); 393 394 /* 395 * initarm_common flushes cache if required before AP start 396 */ 397 bcm53xx_mpstart(); 398 399 return sp; 400 } 401 402 void 403 consinit(void) 404 { 405 static bool consinit_called = false; 406 uint32_t v; 407 if (consinit_called) 408 return; 409 410 consinit_called = true; 411 412 /* 413 * Force UART clock to the reference clock 414 */ 415 v = bus_space_read_4(bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh, 416 IDM_BASE + IDM_APBX_BASE + IDM_IO_CONTROL_DIRECT); 417 v &= ~IO_CONTROL_DIRECT_UARTCLKSEL; 418 bus_space_write_4(bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh, 419 IDM_BASE + IDM_APBX_BASE + IDM_IO_CONTROL_DIRECT, v); 420 421 /* 422 * Switch to the reference clock 423 */ 424 v = bus_space_read_4(bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh, 425 CCA_MISC_BASE + MISC_CORECTL); 426 v &= ~CORECTL_UART_CLK_OVERRIDE; 427 bus_space_write_4(bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh, 428 CCA_MISC_BASE + MISC_CORECTL, v); 429 430 if (comcnattach(bcm53xx_ioreg_bst, comcnaddr, comcnspeed, 431 BCM53XX_REF_CLK, COM_TYPE_NORMAL, comcnmode)) 432 panic("Serial console can not be initialized."); 433 } 434 435 static void 436 bcm53xx_system_reset(void) 437 { 438 bus_space_write_4(bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh, 439 MISC_WATCHDOG, 1); 440 } 441
Indexes created Tue Sep 30 20:09:53 GMT 2025