gb225.c revision 1.1
1 /* $NetBSD: gb225.c,v 1.1 2005/02/26 10:49:53 bsh Exp $ */ 2 3 /* 4 * Copyright (c) 2002, 2003 Genetec corp. All rights reserved. 5 * Written by Hiroyuki Bessho for Genetec corp. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of Genetec corp. may not be used to endorse 16 * or promote products derived from this software without specific prior 17 * written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORP. 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/device.h> 36 #include <sys/kernel.h> 37 #include <sys/reboot.h> 38 39 #include <machine/cpu.h> 40 #include <machine/bus.h> 41 #include <machine/intr.h> 42 #include <arm/cpufunc.h> 43 44 #include <arm/mainbus/mainbus.h> 45 #include <arm/xscale/pxa2x0reg.h> 46 #include <arm/xscale/pxa2x0var.h> 47 #include <arm/xscale/pxa2x0_gpio.h> 48 #include <arm/sa11x0/sa11x0_var.h> 49 #include <evbarm/g42xxeb/g42xxeb_reg.h> 50 #include <evbarm/g42xxeb/g42xxeb_var.h> 51 #include <evbarm/g42xxeb/gb225reg.h> 52 #include <evbarm/g42xxeb/gb225var.h> 53 54 #include "locators.h" 55 56 #define OPIO_INTR G42XXEB_INT_EXT3 57 58 59 #define DEBOUNCE_COUNT 2 60 #define DEBOUNCE_TICKS (hz/20) /* 50ms */ 61 62 /* prototypes */ 63 static int opio_match(struct device *, struct cfdata *, void *); 64 static void opio_attach(struct device *, struct device *, void *); 65 static int opio_search(struct device *, struct cfdata *, void *); 66 static int opio_print(void *, const char *); 67 #ifdef OPIO_INTR 68 static int opio_intr( void *arg ); 69 static void opio_debounce(void *arg); 70 #endif 71 72 73 /* attach structures */ 74 CFATTACH_DECL(opio, sizeof(struct opio_softc), opio_match, opio_attach, 75 NULL, NULL); 76 77 /* 78 * int opio_print(void *aux, const char *name) 79 * print configuration info for children 80 */ 81 82 static int 83 opio_print(void *aux, const char *name) 84 { 85 struct obio_attach_args *oba = (struct obio_attach_args*)aux; 86 87 if (oba->oba_addr != OPIOCF_ADDR_DEFAULT) 88 aprint_normal(" addr 0x%lx", oba->oba_addr); 89 return (UNCONF); 90 } 91 92 int 93 opio_match(struct device *parent, struct cfdata *match, void *aux) 94 { 95 struct obio_softc *psc = (struct obio_softc *)parent; 96 uint16_t optid; 97 98 optid = bus_space_read_2(psc->sc_iot, psc->sc_obioreg_ioh, 99 G42XXEB_OPTBRDID); 100 101 return optid == 0x01; 102 } 103 104 void 105 opio_attach(struct device *parent, struct device *self, void *aux) 106 { 107 struct opio_softc *sc = (struct opio_softc*)self; 108 struct obio_softc *bsc = (struct obio_softc *)parent; 109 struct obio_attach_args *oba = aux; 110 uint32_t reg; 111 int i; 112 bus_space_tag_t iot; 113 bus_space_handle_t memctl_ioh = bsc->sc_memctl_ioh; 114 115 iot = oba->oba_iot; 116 sc->sc_iot = iot; 117 sc->sc_memctl_ioh = memctl_ioh; 118 119 /* use 16bit access for CS4, 32bit for CS5 */ 120 reg = bus_space_read_4(iot, memctl_ioh, MEMCTL_MSC2); 121 reg |= MSC_RBW; 122 reg &= ~(MSC_RBW<<16); 123 /* XXX: set access timing */ 124 bus_space_write_4(iot, memctl_ioh, MEMCTL_MSC2, reg); 125 126 /* Set alternative function for GPIO pings 48..57 on PXA2X0 */ 127 #if 0 128 reg = bus_space_read_4(iot, csc->saip.sc_gpioh, GPIO_GPDR1); 129 bus_space_write_4(iot, csc->saip.sc_gpioh, GPIO_GPDR1, 130 (reg & ~0x03ff0000) | 0x00ff0000); 131 reg = bus_space_read_4(iot, csc->saip.sc_gpioh, GPIO_GAFR1_U); 132 bus_space_write_4(iot, csc->saip.sc_gpioh, GPIO_GAFR1_U, 133 (reg & ~0x000fffff) | 0x0005aaaa ); 134 #else 135 for (i=47; i <= 55; ++i) 136 pxa2x0_gpio_set_function(i, GPIO_ALT_FN_2_OUT); 137 pxa2x0_gpio_set_function(56, GPIO_ALT_FN_1_IN); 138 pxa2x0_gpio_set_function(57, GPIO_ALT_FN_1_IN); 139 #endif 140 141 /* Enable bus switch for option board */ 142 reg = bus_space_read_2(iot, bsc->sc_obioreg_ioh, G42XXEB_EXTCTRL); 143 bus_space_write_2(iot, bsc->sc_obioreg_ioh, G42XXEB_EXTCTRL, reg | 3); 144 145 /* Map on-board FPGA registers */ 146 if( bus_space_map( iot, GB225_PLDREG_BASE, GB225_PLDREG_SIZE, 147 0, &(sc->sc_ioh) ) ){ 148 aprint_error("%s: can't map FPGA registers\n", self->dv_xname); 149 } 150 151 aprint_normal("\n"); 152 153 callout_init(&sc->sc_callout); 154 155 for (i=0; i < N_OPIO_INTR; ++i) { 156 sc->sc_intr[i].func = NULL; 157 sc->sc_intr[i].reported_state = 0xff; 158 sc->sc_intr[i].last_state = 0xff; 159 } 160 161 #ifdef OPIO_INTR 162 sc->sc_ih = obio_intr_establish(bsc, OPIO_INTR, IPL_BIO, 163 IST_EDGE_FALLING, opio_intr, sc); 164 #endif 165 166 #ifdef DEBUG 167 printf("%s: CF_DET=%x PCMCIA_DET=%x\n", 168 self->dv_xname, 169 bus_space_read_1(sc->sc_iot, sc->sc_ioh, GB225_CFDET), 170 bus_space_read_1(sc->sc_iot, sc->sc_ioh, GB225_PCMCIADET)); 171 #endif 172 173 /* 174 * Attach each devices 175 */ 176 config_search(opio_search, self, NULL); 177 } 178 179 int 180 opio_search(struct device *parent, struct cfdata *cf, void *aux) 181 { 182 struct opio_softc *sc = (struct opio_softc *)parent; 183 struct obio_attach_args oba; 184 185 oba.oba_sc = sc; 186 oba.oba_iot = sc->sc_iot; 187 oba.oba_addr = cf->cf_loc[OBIOCF_ADDR]; 188 oba.oba_intr = cf->cf_loc[OBIOCF_INTR]; 189 190 if (config_match(parent, cf, &oba) > 0) 191 config_attach(parent, cf, &oba, opio_print); 192 193 return 0; 194 } 195 196 void * 197 opio_intr_establish(struct opio_softc *sc, int intr, int ipl, 198 int (*func)(void *, int), void *arg) 199 { 200 sc->sc_intr[intr].arg = arg; 201 sc->sc_intr[intr].func = func; 202 203 return &sc->sc_intr[intr]; 204 } 205 206 207 #ifdef OPIO_INTR 208 /* 209 * interrupt handler for option board. interrupt sources are: 210 * CF card insertion/removal. 211 * PCMCIA card insertion/removal. 212 * USB power failure. 213 * CF/PCMCIA power failure. 214 * We need to debounce for CF/PCMCIA card insertion/removal signal. 215 */ 216 static int 217 opio_intr( void *arg ) 218 { 219 struct opio_softc *sc = (struct opio_softc *)arg; 220 struct obio_softc *bsc = (struct obio_softc *)sc->sc_dev.dv_parent; 221 222 /* avoid further interrupts while debouncing */ 223 obio_intr_mask(bsc, sc->sc_ih); 224 225 printf("OPIO "); 226 227 if (sc->sc_debounce == ST_STABLE) { 228 /* start debounce timer */ 229 callout_reset(&sc->sc_callout, DEBOUNCE_TICKS, 230 opio_debounce, sc); 231 sc->sc_debounce = ST_BOUNCING; 232 } 233 234 return 1; 235 } 236 237 238 static int 239 do_debounce(struct opio_softc *sc, int intr, int val, int count) 240 { 241 int s; 242 243 244 struct opio_intr_handler *p = &sc->sc_intr[intr]; 245 246 if (p->last_state != val) { 247 p->debounce_count = 0; 248 p->last_state = val; 249 return 1; 250 } 251 else if (p->debounce_count++ < count) 252 return 1; 253 else { 254 /* debounce done. if status has changed, report it */ 255 if (p->reported_state != val) { 256 p->reported_state = val; 257 if (p->func) { 258 s = _splraise(p->level); 259 p->func(p->arg, val); 260 splx(s); 261 } 262 } 263 return 0; 264 } 265 /*NOTREACHED*/ 266 } 267 268 static void 269 opio_debounce(void *arg) 270 { 271 struct opio_softc *sc = arg; 272 struct obio_softc *osc = (struct obio_softc *)sc->sc_dev.dv_parent; 273 bus_space_tag_t iot = sc->sc_iot; 274 bus_space_handle_t ioh = sc->sc_ioh; 275 int flag = 0; 276 uint8_t reg; 277 278 reg = bus_space_read_1(iot, ioh, GB225_CFDET) & CARDDET_DET; 279 flag |= do_debounce(sc, OPIO_INTR_CF_INSERT, reg, DEBOUNCE_COUNT); 280 281 reg = bus_space_read_1(iot, ioh, GB225_PCMCIADET) & CARDDET_DET; 282 flag |= do_debounce(sc, OPIO_INTR_PCMCIA_INSERT, reg, DEBOUNCE_COUNT); 283 284 reg = bus_space_read_1(iot, ioh, GB225_DEVERROR); 285 286 flag |= do_debounce(sc, OPIO_INTR_USB_POWER, reg & DEVERROR_USB, 1); 287 288 flag |= do_debounce(sc, OPIO_INTR_CARD_POWER, reg & DEVERROR_CARD, 1); 289 290 291 if (flag) { 292 /* start debounce timer */ 293 callout_reset(&sc->sc_callout, DEBOUNCE_TICKS, 294 opio_debounce, sc); 295 } 296 else { 297 sc->sc_debounce = ST_STABLE; 298 obio_intr_unmask(osc, sc->sc_ih); 299 } 300 } 301 #endif 302
Indexes created Wed Oct 01 07:09:59 GMT 2025