gb225.c revision 1.11
1 /* $NetBSD: gb225.c,v 1.11 2021/04/24 23:36:32 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2002, 2003 Genetec corp. All rights reserved. 5 * Written by Hiroyuki Bessho for Genetec corp. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of Genetec corp. may not be used to endorse 16 * or promote products derived from this software without specific prior 17 * written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORP. 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/device.h> 36 #include <sys/kernel.h> 37 #include <sys/reboot.h> 38 39 #include <machine/cpu.h> 40 #include <sys/bus.h> 41 #include <machine/intr.h> 42 #include <arm/cpufunc.h> 43 44 #include <arm/mainbus/mainbus.h> 45 #include <arm/xscale/pxa2x0reg.h> 46 #include <arm/xscale/pxa2x0var.h> 47 #include <arm/xscale/pxa2x0_gpio.h> 48 #include <arm/sa11x0/sa11x0_var.h> 49 #include <evbarm/g42xxeb/g42xxeb_reg.h> 50 #include <evbarm/g42xxeb/g42xxeb_var.h> 51 #include <evbarm/g42xxeb/gb225reg.h> 52 #include <evbarm/g42xxeb/gb225var.h> 53 54 #include "locators.h" 55 56 #define OPIO_INTR G42XXEB_INT_EXT3 57 58 59 #define DEBOUNCE_COUNT 2 60 #define DEBOUNCE_TICKS (hz/20) /* 50ms */ 61 62 /* prototypes */ 63 static int opio_match(device_t, cfdata_t, void *); 64 static void opio_attach(device_t, device_t, void *); 65 static int opio_search(device_t, cfdata_t, const int *, void *); 66 static int opio_print(void *, const char *); 67 #ifdef OPIO_INTR 68 static int opio_intr( void *arg ); 69 static void opio_debounce(void *arg); 70 #endif 71 72 73 /* attach structures */ 74 CFATTACH_DECL_NEW(opio, sizeof(struct opio_softc), opio_match, opio_attach, 75 NULL, NULL); 76 77 /* 78 * int opio_print(void *aux, const char *name) 79 * print configuration info for children 80 */ 81 82 static int 83 opio_print(void *aux, const char *name) 84 { 85 struct obio_attach_args *oba = (struct obio_attach_args*)aux; 86 87 if (oba->oba_addr != OPIOCF_ADDR_DEFAULT) 88 aprint_normal(" addr 0x%lx", oba->oba_addr); 89 return (UNCONF); 90 } 91 92 int 93 opio_match(device_t parent, cfdata_t match, void *aux) 94 { 95 struct obio_softc *psc = device_private(parent); 96 uint16_t optid; 97 98 optid = bus_space_read_2(psc->sc_iot, psc->sc_obioreg_ioh, 99 G42XXEB_OPTBRDID); 100 101 return optid == 0x01; 102 } 103 104 void 105 opio_attach(device_t parent, device_t self, void *aux) 106 { 107 struct opio_softc *sc = device_private(self); 108 struct obio_softc *bsc = device_private(parent); 109 struct obio_attach_args *oba = aux; 110 uint32_t reg; 111 int i; 112 bus_space_tag_t iot; 113 bus_space_handle_t memctl_ioh = bsc->sc_memctl_ioh; 114 115 iot = oba->oba_iot; 116 sc->sc_dev = self; 117 sc->sc_iot = iot; 118 sc->sc_memctl_ioh = memctl_ioh; 119 120 /* use 16bit access for CS4, 32bit for CS5 */ 121 reg = bus_space_read_4(iot, memctl_ioh, MEMCTL_MSC2); 122 reg |= MSC_RBW; 123 reg &= ~(MSC_RBW<<16); 124 /* XXX: set access timing */ 125 bus_space_write_4(iot, memctl_ioh, MEMCTL_MSC2, reg); 126 127 /* Set alternative function for GPIO pings 48..57 on PXA2X0 */ 128 #if 0 129 reg = bus_space_read_4(iot, csc->saip.sc_gpioh, GPIO_GPDR1); 130 bus_space_write_4(iot, csc->saip.sc_gpioh, GPIO_GPDR1, 131 (reg & ~0x03ff0000) | 0x00ff0000); 132 reg = bus_space_read_4(iot, csc->saip.sc_gpioh, GPIO_GAFR1_U); 133 bus_space_write_4(iot, csc->saip.sc_gpioh, GPIO_GAFR1_U, 134 (reg & ~0x000fffff) | 0x0005aaaa ); 135 #else 136 for (i=47; i <= 55; ++i) 137 pxa2x0_gpio_set_function(i, GPIO_ALT_FN_2_OUT); 138 pxa2x0_gpio_set_function(56, GPIO_ALT_FN_1_IN); 139 pxa2x0_gpio_set_function(57, GPIO_ALT_FN_1_IN); 140 #endif 141 142 /* Enable bus switch for option board */ 143 reg = bus_space_read_2(iot, bsc->sc_obioreg_ioh, G42XXEB_EXTCTRL); 144 bus_space_write_2(iot, bsc->sc_obioreg_ioh, G42XXEB_EXTCTRL, reg | 3); 145 146 /* Map on-board FPGA registers */ 147 if( bus_space_map( iot, GB225_PLDREG_BASE, GB225_PLDREG_SIZE, 148 0, &(sc->sc_ioh) ) ){ 149 aprint_error_dev(self, "can't map FPGA registers\n"); 150 } 151 152 aprint_normal("\n"); 153 154 callout_init(&sc->sc_callout, 0); 155 156 for (i=0; i < N_OPIO_INTR; ++i) { 157 sc->sc_intr[i].func = NULL; 158 sc->sc_intr[i].reported_state = 0xff; 159 sc->sc_intr[i].last_state = 0xff; 160 } 161 162 #ifdef OPIO_INTR 163 sc->sc_ih = obio_intr_establish(bsc, OPIO_INTR, IPL_BIO, 164 IST_EDGE_FALLING, opio_intr, sc); 165 #endif 166 167 #ifdef DEBUG 168 aprint_debug_dev(self, "CF_DET=%x PCMCIA_DET=%x\n", 169 bus_space_read_1(sc->sc_iot, sc->sc_ioh, GB225_CFDET), 170 bus_space_read_1(sc->sc_iot, sc->sc_ioh, GB225_PCMCIADET)); 171 #endif 172 173 /* 174 * Attach each devices 175 */ 176 config_search(self, NULL, 177 CFARG_SEARCH, opio_search, 178 CFARG_EOL); 179 } 180 181 int 182 opio_search(device_t parent, cfdata_t cf, 183 const int *ldesc, void *aux) 184 { 185 struct opio_softc *sc = device_private(parent); 186 struct obio_attach_args oba; 187 188 oba.oba_sc = sc; 189 oba.oba_iot = sc->sc_iot; 190 oba.oba_addr = cf->cf_loc[OPIOCF_ADDR]; 191 oba.oba_intr = cf->cf_loc[OPIOCF_INTR]; 192 193 if (config_probe(parent, cf, &oba)) 194 config_attach(parent, cf, &oba, opio_print, CFARG_EOL); 195 196 return 0; 197 } 198 199 void * 200 opio_intr_establish(struct opio_softc *sc, int intr, int ipl, 201 int (*func)(void *, int), void *arg) 202 { 203 sc->sc_intr[intr].arg = arg; 204 sc->sc_intr[intr].func = func; 205 206 return &sc->sc_intr[intr]; 207 } 208 209 210 #ifdef OPIO_INTR 211 /* 212 * interrupt handler for option board. interrupt sources are: 213 * CF card insertion/removal. 214 * PCMCIA card insertion/removal. 215 * USB power failure. 216 * CF/PCMCIA power failure. 217 * We need to debounce for CF/PCMCIA card insertion/removal signal. 218 */ 219 static int 220 opio_intr( void *arg ) 221 { 222 struct opio_softc *sc = (struct opio_softc *)arg; 223 struct obio_softc *bsc = 224 device_private(device_parent(sc->sc_dev)); 225 226 /* avoid further interrupts while debouncing */ 227 obio_intr_mask(bsc, sc->sc_ih); 228 229 printf("OPIO "); 230 231 if (sc->sc_debounce == ST_STABLE) { 232 /* start debounce timer */ 233 callout_reset(&sc->sc_callout, DEBOUNCE_TICKS, 234 opio_debounce, sc); 235 sc->sc_debounce = ST_BOUNCING; 236 } 237 238 return 1; 239 } 240 241 242 static int 243 do_debounce(struct opio_softc *sc, int intr, int val, int count) 244 { 245 int s; 246 247 248 struct opio_intr_handler *p = &sc->sc_intr[intr]; 249 250 if (p->last_state != val) { 251 p->debounce_count = 0; 252 p->last_state = val; 253 return 1; 254 } 255 else if (p->debounce_count++ < count) 256 return 1; 257 else { 258 /* debounce done. if status has changed, report it */ 259 if (p->reported_state != val) { 260 p->reported_state = val; 261 if (p->func) { 262 s = _splraise(p->level); 263 p->func(p->arg, val); 264 splx(s); 265 } 266 } 267 return 0; 268 } 269 /*NOTREACHED*/ 270 } 271 272 static void 273 opio_debounce(void *arg) 274 { 275 struct opio_softc *sc = arg; 276 struct obio_softc *osc = 277 device_private(device_parent(sc->sc_dev)); 278 bus_space_tag_t iot = sc->sc_iot; 279 bus_space_handle_t ioh = sc->sc_ioh; 280 int flag = 0; 281 uint8_t reg; 282 283 reg = bus_space_read_1(iot, ioh, GB225_CFDET) & CARDDET_DET; 284 flag |= do_debounce(sc, OPIO_INTR_CF_INSERT, reg, DEBOUNCE_COUNT); 285 286 reg = bus_space_read_1(iot, ioh, GB225_PCMCIADET) & CARDDET_DET; 287 flag |= do_debounce(sc, OPIO_INTR_PCMCIA_INSERT, reg, DEBOUNCE_COUNT); 288 289 reg = bus_space_read_1(iot, ioh, GB225_DEVERROR); 290 291 flag |= do_debounce(sc, OPIO_INTR_USB_POWER, reg & DEVERROR_USB, 1); 292 293 flag |= do_debounce(sc, OPIO_INTR_CARD_POWER, reg & DEVERROR_CARD, 1); 294 295 296 if (flag) { 297 /* start debounce timer */ 298 callout_reset(&sc->sc_callout, DEBOUNCE_TICKS, 299 opio_debounce, sc); 300 } 301 else { 302 sc->sc_debounce = ST_STABLE; 303 obio_intr_unmask(osc, sc->sc_ih); 304 } 305 } 306 #endif 307
Indexes created Wed Oct 01 15:09:59 GMT 2025