obio.c revision 1.3
1 /* $NetBSD: obio.c,v 1.3 2005/08/26 13:19:35 drochner Exp $ */ 2 3 /* 4 * Copyright (c) 2002, 2003, 2005 Genetec corp. All rights reserved. 5 * Written by Hiroyuki Bessho for Genetec corp. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of Genetec corp. may not be used to endorse 16 * or promote products derived from this software without specific prior 17 * written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORP. 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/device.h> 36 #include <sys/kernel.h> 37 #include <sys/reboot.h> 38 39 #include <machine/cpu.h> 40 #include <machine/bus.h> 41 #include <machine/intr.h> 42 #include <arm/cpufunc.h> 43 44 #include <arm/mainbus/mainbus.h> 45 #include <arm/xscale/pxa2x0reg.h> 46 #include <arm/xscale/pxa2x0var.h> 47 #include <arm/xscale/pxa2x0_gpio.h> 48 #include <arm/sa11x0/sa11x0_var.h> 49 #include <evbarm/g42xxeb/g42xxeb_reg.h> 50 #include <evbarm/g42xxeb/g42xxeb_var.h> 51 52 #include "locators.h" 53 54 /* prototypes */ 55 static int obio_match(struct device *, struct cfdata *, void *); 56 static void obio_attach(struct device *, struct device *, void *); 57 static int obio_search(struct device *, struct cfdata *, 58 const int *, void *); 59 static int obio_print(void *, const char *); 60 61 /* attach structures */ 62 CFATTACH_DECL(obio, sizeof(struct obio_softc), obio_match, obio_attach, 63 NULL, NULL); 64 65 static int 66 obio_spurious(void *arg) 67 { 68 int irqno = (int)arg; 69 70 printf("Spurious interrupt %d on On-board peripheral", irqno); 71 return 1; 72 } 73 74 75 /* 76 * interrupt handler for GPIO0 (on-board peripherals) 77 * 78 * On G4250ebx, 10 interrupts are ORed through on-board logic, 79 * and routed to GPIO0 of PXA250 processor. 80 */ 81 static int 82 obio_intr(void *arg) 83 { 84 int irqno, pending; 85 struct obio_softc *sc = (struct obio_softc *)arg; 86 int n=0; 87 88 #define get_pending(sc) \ 89 (bus_space_read_2( sc->sc_iot, sc->sc_obioreg_ioh, G42XXEB_INTSTS1) \ 90 & ~(sc->sc_intr_pending|sc->sc_intr_mask)) 91 92 #ifdef DEBUG 93 printf("obio_intr: pend=%x, mask=%x, pend=%x, mask=%x\n", 94 bus_space_read_2(sc->sc_iot, sc->sc_obioreg_ioh, G42XXEB_INTSTS1), 95 bus_space_read_2(sc->sc_iot, sc->sc_obioreg_ioh, G42XXEB_INTMASK), 96 sc->sc_intr_pending, 97 sc->sc_intr_mask); 98 #endif 99 100 for (pending = get_pending(sc); 101 (irqno = find_first_bit(pending)) >= 0; 102 pending = get_pending(sc)) { 103 104 /* reset pending bit */ 105 bus_space_write_2(sc->sc_iot, sc->sc_obioreg_ioh, 106 G42XXEB_INTSTS1, ~(1<<irqno)); 107 108 #if 0 109 if (sc->sc_handler[irqno].level > saved_spl_level) { 110 int spl_save = _splraise(sc->sc_handler[irqno].level); 111 (* sc->sc_handler[irqno].func)( 112 sc->sc_handler[irqno].arg); 113 splx(spl_save); 114 } 115 else 116 #endif 117 { 118 int psw = disable_interrupts(I32_bit); /* XXX */ 119 120 /* mask this interrupt until software 121 interrupt is handled. */ 122 sc->sc_intr_pending |= (1U<<irqno); 123 obio_update_intrmask(sc); 124 125 restore_interrupts(psw); 126 ++n; 127 } 128 #ifdef DIAGNOSTIC 129 if (n > 1000) 130 panic("obio_intr: stayed too long"); 131 #endif 132 } 133 134 if (n > 0) { 135 /* handle it later */ 136 softintr_schedule(sc->sc_si); 137 } 138 139 /* GPIO interrupt is edge triggered. make a pulse 140 to let Cotulla notice when other interrupts are 141 still pending */ 142 bus_space_write_2(sc->sc_iot, sc->sc_obioreg_ioh, 143 G42XXEB_INTMASK, 0xffff); 144 obio_update_intrmask(sc); 145 146 return 1; 147 } 148 149 static void 150 obio_softintr(void *arg) 151 { 152 struct obio_softc *sc = (struct obio_softc *)arg; 153 int irqno; 154 int spl_save = current_spl_level; 155 int psw; 156 157 psw = disable_interrupts(I32_bit); 158 while ((irqno = find_first_bit(sc->sc_intr_pending)) >= 0) { 159 sc->sc_intr_pending &= ~(1U<<irqno); 160 161 restore_interrupts(psw); 162 163 _splraise(sc->sc_handler[irqno].level); 164 (* sc->sc_handler[irqno].func)( 165 sc->sc_handler[irqno].arg); 166 splx(spl_save); 167 168 psw = disable_interrupts(I32_bit); 169 } 170 171 /* assert(sc->sc_intr_pending==0) */ 172 173 bus_space_write_2(sc->sc_iot, sc->sc_obioreg_ioh, 174 G42XXEB_INTMASK, 0xffff); 175 obio_update_intrmask(sc); 176 177 restore_interrupts(psw); 178 } 179 180 /* 181 * int obio_print(void *aux, const char *name) 182 * print configuration info for children 183 */ 184 185 static int 186 obio_print(void *aux, const char *name) 187 { 188 struct obio_attach_args *oba = (struct obio_attach_args*)aux; 189 190 if (oba->oba_addr != OBIOCF_ADDR_DEFAULT) 191 printf(" addr 0x%lx", oba->oba_addr); 192 if (oba->oba_intr > 0) 193 printf(" intr %d", oba->oba_intr); 194 return (UNCONF); 195 } 196 197 int 198 obio_match(struct device *parent, struct cfdata *match, void *aux) 199 { 200 return 1; 201 } 202 203 void 204 obio_attach(struct device *parent, struct device *self, void *aux) 205 { 206 struct obio_softc *sc = (struct obio_softc*)self; 207 struct sa11x0_attach_args *sa = (struct sa11x0_attach_args *)aux; 208 bus_space_tag_t iot = sa->sa_iot; 209 int i; 210 uint16_t reg; 211 212 /* tweak memory access timing for CS3. 213 the value set by redboot is too slow */ 214 if (bus_space_map(iot, PXA2X0_MEMCTL_BASE, PXA2X0_MEMCTL_SIZE, 0, 215 &sc->sc_memctl_ioh)) 216 goto fail; 217 bus_space_write_4(iot, sc->sc_memctl_ioh, MEMCTL_MSC1, 218 (0xffff & bus_space_read_4(iot, sc->sc_memctl_ioh, MEMCTL_MSC1)) 219 | (0x6888 << 16)); 220 221 /* Map on-board FPGA registers */ 222 sc->sc_iot = iot; 223 if (bus_space_map(iot, G42XXEB_PLDREG_BASE, G42XXEB_PLDREG_SIZE, 224 0, &(sc->sc_obioreg_ioh))) 225 goto fail; 226 227 /* 228 * Mask all interrupts. 229 * They are later unmasked at each device's attach routine. 230 */ 231 sc->sc_intr_mask = 0xffff; 232 bus_space_write_2(iot, sc->sc_obioreg_ioh, G42XXEB_INTMASK, 233 sc->sc_intr_mask ); 234 235 #if 0 236 sc->sc_intr = 8; /* GPIO0 */ 237 #endif 238 sc->sc_intr_pending = 0; 239 240 for (i=0; i < G42XXEB_N_INTS; ++i) { 241 sc->sc_handler[i].func = obio_spurious; 242 sc->sc_handler[i].arg = (void *)i; 243 } 244 245 obio_peripheral_reset(sc, 1, 0); 246 247 /* 248 * establish interrupt handler. 249 * level is very high to allow high priority sub-interrupts. 250 */ 251 sc->sc_ipl = IPL_AUDIO; 252 sc->sc_ih = pxa2x0_gpio_intr_establish(0, IST_EDGE_FALLING, sc->sc_ipl, 253 obio_intr, sc); 254 sc->sc_si = softintr_establish(IPL_SOFTNET, obio_softintr, sc); 255 256 reg = bus_space_read_2(iot, sc->sc_obioreg_ioh, G42XXEB_PLDVER); 257 aprint_normal(": board %d version %x\n", reg>>8, reg & 0xff); 258 259 /* 260 * Attach each devices 261 */ 262 config_search_ia(obio_search, self, "obio", NULL); 263 return; 264 265 fail: 266 printf( "%s: can't map FPGA registers\n", self->dv_xname ); 267 } 268 269 int 270 obio_search(struct device *parent, struct cfdata *cf, 271 const int *ldesc, void *aux) 272 { 273 struct obio_softc *sc = (struct obio_softc *)parent; 274 struct obio_attach_args oba; 275 276 oba.oba_sc = sc; 277 oba.oba_iot = sc->sc_iot; 278 oba.oba_addr = cf->cf_loc[OBIOCF_ADDR]; 279 oba.oba_intr = cf->cf_loc[OBIOCF_INTR]; 280 281 if (config_match(parent, cf, &oba) > 0) 282 config_attach(parent, cf, &oba, obio_print); 283 284 return 0; 285 } 286 287 void * 288 obio_intr_establish(struct obio_softc *sc, int irq, int ipl, 289 int type, int (*func)(void *), void *arg) 290 { 291 int save; 292 int regidx, sft; 293 uint16_t reg; 294 static const uint8_t ist_code[] = { 295 0, 296 G42XXEB_INT_EDGE_FALLING, /* pulse */ 297 G42XXEB_INT_EDGE_FALLING, /* IST_EDGE */ 298 G42XXEB_INT_LEVEL_LOW, /* IST_LEVEL */ 299 G42XXEB_INT_LEVEL_HIGH, /* IST_LEVEL_HIGH */ 300 G42XXEB_INT_EDGE_RISING, /* IST_EDGE_RISING */ 301 G42XXEB_INT_EDGE_BOTH, /* IST_EDGE_BOTH */ 302 }; 303 304 if (irq < 0 || G42XXEB_N_INTS <= irq) 305 panic("Bad irq no. for obio (%d)", irq); 306 307 if (type < 0 || IST_EDGE_BOTH < type) 308 panic("Bad interrupt type for obio (%d)", type); 309 310 regidx = G42XXEB_INTCNTL; 311 sft = 3 * irq; 312 if (irq >= 5) { 313 regidx = G42XXEB_INTCNTH; 314 sft -= 3*5; 315 } 316 317 save = disable_interrupts(I32_bit); 318 319 sc->sc_handler[irq].func = func; 320 sc->sc_handler[irq].arg = arg; 321 sc->sc_handler[irq].level = ipl; 322 323 /* set interrupt type */ 324 reg = bus_space_read_2(sc->sc_iot, sc->sc_obioreg_ioh, regidx); 325 bus_space_write_2(sc->sc_iot, sc->sc_obioreg_ioh, regidx, 326 (reg & ~(7<<sft)) | (ist_code[type] << sft)); 327 328 #ifdef DEBUG 329 printf("INTCTL=%x,%x\n", 330 bus_space_read_2(sc->sc_iot, sc->sc_obioreg_ioh, G42XXEB_INTCNTL), 331 bus_space_read_2(sc->sc_iot, sc->sc_obioreg_ioh, G42XXEB_INTCNTH)); 332 #endif 333 334 sc->sc_intr_mask &= ~(1U << irq); 335 obio_update_intrmask(sc); 336 337 restore_interrupts(save); 338 339 #if 0 340 if (ipl > sc->sc_ipl) { 341 pxa2x0_update_intr_masks(sc->sc_intr, ipl); 342 sc->sc_ipl = ipl; 343 } 344 #endif 345 346 return &sc->sc_handler[irq]; 347 } 348 349 void 350 obio_intr_disestablish(struct obio_softc *sc, int irq, int (* func)(void *)) 351 { 352 int error = 0; 353 int save; 354 355 save = disable_interrupts(I32_bit); 356 357 if (sc->sc_handler[irq].func != func) 358 error = 1; 359 else { 360 sc->sc_handler[irq].func = obio_spurious; 361 sc->sc_handler[irq].level = IPL_NONE; 362 363 sc->sc_intr_pending &= ~(1U << irq); 364 sc->sc_intr_mask |= (1U << irq); 365 obio_update_intrmask(sc); 366 } 367 368 restore_interrupts(save); 369 370 if (error) 371 aprint_error("%s: bad intr_disestablish\n", 372 sc->sc_dev.dv_xname); 373 } 374 375 void 376 obio_intr_mask(struct obio_softc *sc, struct obio_handler *ih) 377 { 378 int irqno; 379 int save; 380 381 irqno = ih - sc->sc_handler; 382 #ifdef DIAGNOSTIC 383 if (ih == NULL || ih->func==NULL || irqno < 0 || 384 irqno >= G42XXEB_N_INTS) 385 panic("Bad arg for obio_intr_mask"); 386 #endif 387 388 save = disable_interrupts(I32_bit); 389 sc->sc_intr_mask |= 1U<<irqno; 390 obio_update_intrmask(sc); 391 restore_interrupts(save); 392 } 393 394 void 395 obio_intr_unmask(struct obio_softc *sc, struct obio_handler *ih) 396 { 397 int irqno; 398 int save; 399 400 irqno = ih - sc->sc_handler; 401 #ifdef DIAGNOSTIC 402 if (ih == NULL || ih->func==NULL || irqno < 0 || 403 irqno >= G42XXEB_N_INTS) 404 panic("Bad arg for obio_intr_unmask"); 405 #endif 406 407 save = disable_interrupts(I32_bit); 408 sc->sc_intr_mask &= ~(1U<<irqno); 409 obio_update_intrmask(sc); 410 restore_interrupts(save); 411 } 412 413 void 414 obio_peripheral_reset(struct obio_softc *bsc, int no, int onoff) 415 { 416 uint16_t reg; 417 418 reg = bus_space_read_2(bsc->sc_iot, bsc->sc_obioreg_ioh, 419 G42XXEB_RST); 420 bus_space_write_2(bsc->sc_iot, bsc->sc_obioreg_ioh, G42XXEB_RST, 421 onoff ? (reg & ~RST_EXT(no)) : (reg | RST_EXT(no))); 422 } 423 424
Indexes created Tue Sep 30 20:09:53 GMT 2025