gemini_start.S revision 1.1
1 /* $NetBSD: gemini_start.S,v 1.1 2008/10/24 04:23:18 matt Exp $ */ 2 3 /* 4 * Machine dependant startup code for GEMINI boards. 5 * Based on omap_start.S 6 * 7 * Copyright (c) 2002, 2003 Genetec Corporation. All rights reserved. 8 * Written by Hiroyuki Bessho for Genetec Corporation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The name of Genetec Corporation may not be used to endorse or 19 * promote products derived from this software without specific prior 20 * written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 * 34 * Copyright (c) 2003 35 * Ichiro FUKUHARA <ichiro (at) ichiro.org>. 36 * All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 3. All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by Ichiro FUKUHARA. 49 * 4. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 54 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 55 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 57 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 59 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 * 65 * Copyright (c) 2007 Microsoft 66 * All rights reserved. 67 * 68 * Redistribution and use in source and binary forms, with or without 69 * modification, are permitted provided that the following conditions 70 * are met: 71 * 1. Redistributions of source code must retain the above copyright 72 * notice, this list of conditions and the following disclaimer. 73 * 2. Redistributions in binary form must reproduce the above copyright 74 * notice, this list of conditions and the following disclaimer in the 75 * documentation and/or other materials provided with the distribution. 76 * 3. All advertising materials mentioning features or use of this software 77 * must display the following acknowledgement: 78 * This product includes software developed by Microsoft 79 * 80 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 81 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 82 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 83 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTERS BE LIABLE FOR ANY DIRECT, 84 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 85 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 86 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 87 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 88 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 89 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 90 * SUCH DAMAGE. 91 */ 92 93 #include "opt_gemini.h" 94 #include "opt_com.h" 95 #include "assym.h" 96 97 #include <machine/asm.h> 98 #include <arm/armreg.h> 99 #undef DOMAIN_CLIENT /* assym.h defines as 1, but pte.h defines as 0x01 */ 100 #include <arm/arm32/pmap.h> 101 #include <arm/gemini/gemini_reg.h> 102 #include <evbarm/gemini/gemini.h> 103 104 RCSID("$NetBSD: gemini_start.S,v 1.1 2008/10/24 04:23:18 matt Exp $") 105 106 107 #define _PUTCHAR(addr, areg, breg, c) \ 108 ldr areg, addr; \ 109 1: \ 110 ldr breg, [ areg, #0x14 ]; /* LSR */ \ 111 tst breg, #0x20; /* TXRDY? */ \ 112 beq 1b; \ 113 mov breg, #(c); /* c */ \ 114 str breg, [ areg ]; /* TXDATA */ \ 115 2: \ 116 ldr breg, [ areg, #0x14 ]; /* LSR */ \ 117 tst breg, #0x40; /* TSRE? */ \ 118 beq 2b; 119 120 121 /* 122 * Kernel start routine for GEMINI Eval board. 123 * At this point, this code has been loaded into SDRAM 124 * and the MMU is off 125 */ 126 .section .start,"ax",%progbits 127 128 .global _C_LABEL(gemini_start) 129 _C_LABEL(gemini_start): 130 /* Move into supervisor mode and disable IRQs/FIQs. */ 131 mrs r0, cpsr 132 bic r0, r0, #PSR_MODE 133 orr r0, r0, #(I32_bit | F32_bit | PSR_SVC32_MODE) 134 msr cpsr, r0 135 136 _PUTCHAR(Lconsole_pbase, r4, r3, 'a') 137 138 /* 139 * Set up a preliminary mapping in the MMU to allow us to run 140 * at KERNEL_BASE with caches on. 141 */ 142 /* Build page table from scratch */ 143 ldr r0, Ltemp_l1_table 144 mov r1, r0 /* Save the page table address. */ 145 /* Zero the entire table so all virtual addresses are invalid. */ 146 mov r2, #L1_TABLE_SIZE /* in bytes */ 147 mov r3, #0 148 mov r4, r3 149 mov r5, r3 150 mov r6, r3 151 mov r7, r3 152 mov r8, r3 153 mov r10, r3 154 mov r11, r3 155 1: stmia r1!, {r3-r8,r10-r11} 156 stmia r1!, {r3-r8,r10-r11} 157 stmia r1!, {r3-r8,r10-r11} 158 stmia r1!, {r3-r8,r10-r11} 159 subs r2, r2, #(4 * 4 * 8) /* bytes per loop */ 160 bne 1b 161 162 _PUTCHAR(Lconsole_pbase, r4, r3, 'b') 163 164 /* Now create our entries per the mmu_init_table. */ 165 l1table .req r0 166 va .req r1 167 pa .req r2 168 n_sec .req r3 169 attr .req r4 170 itable .req r5 171 l1sfrm .req r6 172 ldr l1table, Ltemp_l1_table 173 adr itable, mmu_init_table 174 ldr l1sfrm, Ll1_s_frame 175 b 3f 176 2: str pa, [l1table, va] 177 add va, va, #4 178 add pa, pa, #(L1_S_SIZE) 179 adds n_sec, n_sec, #-1 180 bhi 2b 181 3: ldmia itable!, {va,pa,n_sec,attr} 182 /* Convert va to l1 offset: va = 4 * (va >> L1_S_SHIFT) */ 183 mov va, va, LSR #L1_S_SHIFT 184 mov va, va, LSL #2 185 /* Convert pa to l1 entry: pa = (pa & L1_S_FRAME) | attr */ 186 and pa, pa, l1sfrm 187 orr pa, pa, attr 188 cmp n_sec, #0 189 bne 2b 190 mov r5, r0 /* l1table */ 191 .unreq va 192 .unreq pa 193 .unreq n_sec 194 .unreq attr 195 .unreq itable 196 .unreq l1table 197 .unreq l1sfrm 198 199 _PUTCHAR(Lconsole_pbase, r4, r3, 'c') 200 201 /* 202 * using FA526 -specific cache ops here... 203 */ 204 mov r0, #0 205 mcr p15, 0, r0, c7, c5, 0 /* Invalidate Entire I cache */ 206 mcr p15, 0, r0, c7, c14, 0 /* Clean & Invalidate Entire D cache */ 207 208 ldr r2, Lctl_ID_dis /* Disable I+D caches */ 209 mrc p15, 0, r1, c1, c0, 0 /* " " " */ 210 and r1, r1, r2 /* " " " */ 211 mcr p15, 0, r1, c1, c0, 0 /* " " " */ 212 213 _PUTCHAR(Lconsole_pbase, r4, r3, 'd') 214 215 mcr p15, 0, r0, c7, c5, 6 /* invalidate BTB all */ 216 mcr p15, 0, r0, c7, c10, 4 /* Drain the write buffers. */ 217 mcr p15, 0, r5, c2, c0, 0 /* Set Translation Table Base */ 218 mcr p15, 0, r0, c8, c7, 0 /* Invalidate TLBs */ 219 220 /* Set the Domain Access register */ 221 mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT) 222 mcr p15, 0, r0, c3, c0, 0 223 224 /* 225 * set Extension Control Enable in ECR, so we can use BTB 226 */ 227 ldr r0, Lecr_set 228 mcr p15, 0, r0, c1, c1, 0 229 230 /* 231 * Enable the MMU, etc. 232 */ 233 mrc p15, 0, r0, c1, c0, 0 234 ldr r1, Lcontrol_wax 235 and r0, r0, r1 236 ldr r1, Lcontrol_clr 237 mvn r1, r1 238 and r0, r0, r1 239 ldr r1, Lcontrol_set 240 orr r0, r0, r1 241 mcr p15, 0, r0, c1, c0, 0 242 243 /* 244 * Ensure that the coprocessor has finished turning on the MMU. 245 */ 246 mrc p15, 0, r0, c2, c0, 0 /* Read an arbitrary value. */ 247 mov r0, r0 /* Stall until read completes. */ 248 249 _PUTCHAR(Lconsole_vbase, r4, r3, 'e') 250 251 /* 252 * Zero .bss 253 */ 254 ldr r0, L_edata 255 ldr r1, L_end 256 mov r2, #0 257 1: 258 str r2, [r0], #0x04 /* *r0++ = r2 */ 259 cmp r0, r1 260 bne 1b 261 262 #if 0 263 /* 264 * Jump to start in locore.S, which in turn will call initarm and main. 265 */ 266 adr r0, Ltestjmp 267 ldr pc, [r0] 268 nop 269 nop 270 nop 271 nop 272 testjmp: 273 #endif 274 275 _PUTCHAR(Lconsole_vbase, r4, r3, 'f') 276 277 adr r0, Lstart 278 ldr pc, [r0] 279 nop 280 nop 281 nop 282 nop 283 284 /* NOTREACHED */ 285 286 L_edata: 287 .word _C_LABEL(_edata) 288 L_end: 289 .word _C_LABEL(_end) 290 291 #if 0 292 Ltestjmp: 293 .word testjmp 294 #endif 295 296 Lstart: 297 .word start 298 Ll1_s_frame: 299 .word L1_S_FRAME 300 Ltemp_l1_table: 301 /* Put the temporary L1 translation table at the end of SDRAM. */ 302 .word 0x10000000 + MEMSIZE * 0x100000 - L1_TABLE_SIZE 303 304 /* 305 * Coprocessor register initialization values 306 */ 307 #if !defined(CPU_ECR_ECE) 308 # define CPU_ECR_ECE 1 309 #endif 310 /* bits to set in the Extension Control Register */ 311 Lecr_set: 312 .word CPU_ECR_ECE 313 314 #if !defined(CPU_CONTROL_BTB_ENABLE) 315 # define CPU_CONTROL_BTB_ENABLE (1 << 11) 316 #endif 317 /* bits to set in the Control Register */ 318 /* bits 6..4 SB1 */ 319 Lcontrol_set: 320 .word CPU_CONTROL_MMU_ENABLE | \ 321 CPU_CONTROL_AFLT_ENABLE | \ 322 CPU_CONTROL_DC_ENABLE | \ 323 CPU_CONTROL_WBUF_ENABLE | \ 324 CPU_CONTROL_32BP_ENABLE | \ 325 CPU_CONTROL_32BD_ENABLE | \ 326 CPU_CONTROL_LABT_ENABLE | \ 327 CPU_CONTROL_SYST_ENABLE | \ 328 CPU_CONTROL_IC_ENABLE | \ 329 CPU_CONTROL_DC_ENABLE | \ 330 CPU_CONTROL_BTB_ENABLE 331 332 /* bits to clear in the Control Register */ 333 /* bits 31..14, 10, SBZ */ 334 Lcontrol_clr: 335 .word ((~0) << 14) | \ 336 (1 << 10) 337 338 /* bits to "write as existing" in the Control Register */ 339 Lcontrol_wax: 340 .word CPU_CONTROL_BEND_ENABLE 341 342 /* bits to disable the caches */ 343 Lctl_ID_dis: 344 .word ~(CPU_CONTROL_IC_ENABLE|CPU_CONTROL_DC_ENABLE) 345 346 /* console addressing */ 347 Lconsole_pbase: 348 .word CONSADDR 349 Lconsole_vbase: 350 .word GEMINI_CONSOLE_VBASE 351 352 353 /* We'll modify va and pa at run time so we can use relocatable addresses. */ 354 #define MMU_INIT(va,pa,n_sec,attr) \ 355 .word va ; \ 356 .word pa ; \ 357 .word n_sec ; \ 358 .word attr ; 359 360 mmu_init_table: 361 /* Maintain current 1:1 addressability */ 362 MMU_INIT(KERNEL_BASE_phys, KERNEL_BASE_phys, 363 (MEMSIZE * L1_S_SIZE + L1_S_SIZE - 1) / L1_S_SIZE, 364 L1_S_PROTO | L1_S_AP(AP_KRW) | L1_S_B | L1_S_C) 365 366 /* Map Kernel base VA:PA, write-back cacheable */ 367 MMU_INIT(KERNEL_BASE_virt, KERNEL_BASE_phys, 368 (MEMSIZE * L1_S_SIZE + L1_S_SIZE - 1) / L1_S_SIZE, 369 L1_S_PROTO | L1_S_AP(AP_KRW) | L1_S_B | L1_S_C) 370 371 /* Map console UART */ 372 MMU_INIT(GEMINI_CONSOLE_VBASE, CONSADDR, 373 1, 374 L1_S_PROTO | L1_S_AP(AP_KRW)) 375 376 /* end of table */ 377 MMU_INIT(0, 0, 0, 0) 378 379
Indexes created Sun Sep 28 16:09:52 GMT 2025